Chapter 9: Sequential Logic Modules

Chapter 9: Sequential Logic Modules
Prof. Ming-Bo Lin

Department of Electronic Engineering National Taiwan University of Science and Technology

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

9-1

Chapter 9: Sequential Logic Modules

Syllabus
™ ™ ™ ™ ™ ™ ™ ™ Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

9-2

Chapter 9: Sequential Logic Modules

Objectives
After completing this chapter, you will be able to: ™ Describe how to model asynchronous and synchronous D-type flip-flops ™ Describe how to model registers (data register, register file, and synchronous RAM) ™ Describe how to model shift registers ™ Describe how to model counters (ripple/synchronous counters and modulo r counters) ™ Describe how to model sequence generators ™ Describe how to model timing generators
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-3

Chapter 9: Sequential Logic Modules

Syllabus
™ ™ ™ ™ ™ ™ ™ ™ Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

9-4

Chapter 9: Sequential Logic Modules

Basic Sequential Logic Modules
™ ™ ™ ™ ™ ™ ™ ™ ™ ™ ™ Synchronizer Finite state machine Sequence detector Data register Shift register CRC generator Register file Counters (binary, BCD, Johnson) Timing generator Clock generator Pulse generator
9-5

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

Chapter 9: Sequential Logic Modules Options for Modeling Sequential Logic ™ ™ ™ ™ ™ Behavioral statement Task with delay or event control Sequential UDP Instantiated library register cell Instantiated modules Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-6 .

John Wiley 9-7 .Chapter 9: Sequential Logic Modules Syllabus ™ ™ ™ ™ ™ ™ ™ ™ Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

Q: How would you model a D-type latch? Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-8 . reset_n. … output reg q. d. q).Chapter 9: Sequential Logic Modules Asynchronous Reset D-Type Flip-Flops // asynchronous reset D-type flip-flop module DFF_async_reset (clk. else q <= d. always @(posedge clk or negedge reset_n) if (!reset_n) q <= 0.

Chapter 9: Sequential Logic Modules Synchronous Reset D-Type Flip-Flops // synchronous reset D-type flip-flop module DFF_sync_reset (clk. John Wiley 9-9 . reset. … output reg q. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. q). always @(posedge clk) if (reset) q <= 0. d. else q <= d.

John Wiley 9-10 .Chapter 9: Sequential Logic Modules Syllabus ™ ™ ™ ™ ™ ™ ™ ™ Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

John Wiley 9-11 .Chapter 9: Sequential Logic Modules Types of Memory Elements ™ Data registers ™ Register files ™ Synchronous RAMs Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

John Wiley 9-12 .Chapter 9: Sequential Logic Modules Registers ™ Registers (or data registers) ™ A flip-flop ƒ Area: 10 to 20x of an SRAM cell ™ In Xilinx FPGAs ƒ Flip-flops ƒ Distributed memory ƒ Block memory Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

Chapter 9: Sequential Logic Modules Data Registers // an n-bit data register module register(clk. qout). din. output reg [N-1:0] qout. parameter N = 4. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-13 . // number of bits … input [N-1:0] din. always @(posedge clk) qout <= din.

Chapter 9: Sequential Logic Modules Data Registers // an n-bit data register with asynchronous reset module register_reset (clk. qout). output reg [N-1:0] qout. always @(posedge clk or negedge reset_n) if (!reset_n) qout <= {N{1'b0}}. din. reset_n. else qout <= din. parameter N = 4. John Wiley 9-14 . // number of bits … input [N-1:0] din. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

always @(posedge clk or negedge reset_n) if (!reset_n) qout <= {N{1'b0}}.Chapter 9: Sequential Logic Modules Data Registers // an N-bit data register with synchronous load and // asynchronous reset parameter N = 4. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. load. // number of bits input clk. input [N-1:0] din. output reg [N-1:0] qout. else if (load) qout <= din. John Wiley 9-15 . reset_n.

… assign douta = reg_file[rd_addra]. // number of bits in a word input clk. John Wiley 9-16 . doutb = reg_file[rd_addrb]. what happens!! Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. // number of words. reg [W-1:0] reg_file [N-1:0]. always @(posedge clk) Try to synthesize it and see if (wr_enable) reg_file[wr_addr] <= din. wr_enable. N = 2**M parameter W = 8. input [M-1:0] rd_addra. rd_addrb.Chapter 9: Sequential Logic Modules A Register File // an N-word register file with one-write and two-read ports parameter M = 4. output [W-1:0] douta. input [W-1:0] din. doutb. // number of address bits parameter N = 16. wr_addr.

// number of address bits parameter W = 4. wr. Try to synthesize it and see what happens!! Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. input [W-1:0] din. // declare an N * W memory array always @(posedge clk) if (cs) if (wr) ram[addr] <= din. reg [W-1:0] ram [N-1:0]. read-write control. // number of words parameter A = 4. input cs. // chip select. // number of wordsize in bits input [A-1:0] addr. else dout <= ram[addr]. John Wiley 9-17 . clk.Chapter 9: Sequential Logic Modules An Synchronous RAM // a synchronous RAM module example parameter N = 16. and clock signals output reg [W-1:0] dout.

John Wiley 9-18 .Chapter 9: Sequential Logic Modules Syllabus ™ ™ ™ ™ ™ ™ ™ ™ Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

Chapter 9: Sequential Logic Modules Shift Registers ™ Shift registers ™ Parallel/serial format conversion ƒ ƒ ƒ ƒ SISO (serial in serial out) SIPO (serial in parallel out) PISO (parallel in serial out) PIPO (parallel in parallel out) Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-19 .

Chapter 9: Sequential Logic Modules Shift Registers Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-20 .

John Wiley 9-21 . Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. qout). always @(posedge clk or negedge reset_n) if (!reset_n) qout <= {N{1'b0}}. output reg [N-1:0] qout. qout[N-1:1]}. reset_n. Parameter N = 4. din.Chapter 9: Sequential Logic Modules Shift Registers // a shift register module example module shift_register(clk. else qout <= {din. // number of bits ….

Chapter 9: Sequential Logic Modules A Shift Register with Parallel Load // a shift register with parallel load module example module shift_register_parallel_load (clk. else qout <= {sin. always @(posedge clk or negedge reset_n) if (!reset_n) qout <= {N{1'b0}}. reset_n. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. else if (load) qout <= din. // number of bits …. qout). din. sin. output reg [N-1:0] qout. load. John Wiley 9-22 . parameter N = 8. qout[N-1:1]}. input [N-1:0] din.

Chapter 9: Sequential Logic Modules Universal Shift Registers ™ A universal shift register can carry out ƒ ƒ ƒ ƒ SISO SIPO PISO PIPO ™ The register must have the following capabilities ƒ Parallel load ƒ Serial in and serial out ƒ Shift left and shift right Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-23 .

John Wiley 9-24 .Chapter 9: Sequential Logic Modules Universal Shift Registers Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

// qout <= qout. qout[N-1:1]}. // Parallel load endcase Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. rsi}.s0}) 2'b00: . // Shift left 2'b11: qout <= din. reset_n. s1. parameter N = 4. // Shift right 2'b10: qout <= {qout[N-2:0]. else case ({s1.Chapter 9: Sequential Logic Modules Universal Shift Registers // a universal shift register module module universal_shift_register (clk. // No change 2'b01: qout <= {lsi. …). John Wiley 9-25 . // define the default size … always @(posedge clk or negedge reset_n) if (!reset_n) qout <= {N{1'b0}}. s0.

John Wiley 9-26 .Chapter 9: Sequential Logic Modules Syllabus ™ ™ ™ ™ ™ ™ ™ ™ Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

Chapter 9: Sequential Logic Modules Counters ™ Counter ™ Types ƒ Counters ƒ Timers Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-27 .

John Wiley 9-28 .Chapter 9: Sequential Logic Modules Types of Counters ™ Types of counters ƒ Asynchronous ƒ Synchronous ™ Asynchronous (ripple) counters ƒ Binary counter (up/down counters) ™ Synchronous counters ƒ Binary counter (up/down counters) ƒ BCD counter (up/down counters) ƒ Gray counters (up/down counters) Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

Chapter 9: Sequential Logic Modules Binary Ripple Counters Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-29 .

simulators due to lacking initial always @(negedge c1) values of qout. happens!! always @(negedge c0) • The output cannot be observed from qout[1] <= ~qout[1].Chapter 9: Sequential Logic Modules Binary Ripple Counters // a 3-bit ripple counter module example module ripple_counter(clk. wire c0. always @(negedge clk) • Try to synthesize it and see what qout[0] <= ~qout[0]. qout[2] <= ~qout[2]. qout). c1 = qout[1]. John Wiley 9-30 . c1. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. // the body of the 3-bit ripple counter assign c0 = qout[0]. … output reg [2:0] qout.

always @(posedge c1 or negedge reset_n) if (!reset_n) qout[2] <= 1'b0. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. … output reg [2:0] qout. assign c0 = qout[0].Chapter 9: Sequential Logic Modules Binary Ripple Counters // a 3-bit ripple counter with enable control module ripple_counter_enable(clk. qout). c1. else if (enable) qout[1] <= ~qout[1]. reset_n. wire c0. always @(posedge c0 or negedge reset_n) if (!reset_n) qout[1] <= 1'b0. John Wiley 9-31 . always @(posedge clk or negedge reset_n) if (!reset_n) qout[0] <= 1'b0. c1 = qout[1]. else if (enable) qout[2] <= ~qout[2]. else if (enable) qout[0] <= ~qout[0]. enable.

else qout[0] <= ~qout[0]. i = i + 1) begin: ripple_counter if (i == 0) // specify LSB always @(negedge clk or negedge reset_n) if (!reset_n) qout[0] <= 1'b0. else qout[i] <= ~qout[i]. else // specify the rest bits always @(negedge qout[i-1]or negedge reset_n) if (!reset_n) qout[i] <= 1'b0.Chapter 9: Sequential Logic Modules A Binary Ripple Counter // an N-bit ripple counter using generate blocks parameter N = 4. end endgenerate Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-32 . i < N. generate for (i = 0. // define the size of counter … output reg [N-1:0] qout. genvar i.

// carry output always @(posedge clk) if (reset) qout <= {N{1’b0}}. cout). enable. output cout. else if (enable) qout <= qout + 1. // generate carry output assign #2 cout = &qout. // Why #2 is required ? Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. … output reg [N-1:0] qout. reset. John Wiley 9-33 . qout. parameter N = 4.Chapter 9: Sequential Logic Modules A Binary Counter Example module binary_counter(clk.

else qout <= qout . // carry and borrow outputs always @(posedge clk) if (reset) qout <= {N{1'b0}}. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. cout.1. else if (enable) begin if (upcnt) qout <= qout + 1. enable. // Why #2 is required ? assign #2 bout = |qout. bout. end assign #2 cout = &qout. parameter N = 4.Chapter 9: Sequential Logic Modules Binary Up/Down Counters --. output cout. upcnt. John Wiley 9-34 . qout. bout).version 1 module binary_up_down_counter_reset (clk. … output reg [N-1:0] qout. reset.

… output reg [N-1:0] qout. // generate borrow out Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. Parameter N = 4. qout. reset. // synchronous reset else if (eup) qout <= qout + 1.1. cout. assign #1 cout = (&qout)& eup. // generate carry out assign #1 bout = (~|qout)& edn. else if (edn) qout <= qout .version 2 module up_dn_bin_counter (clk. John Wiley 9-35 . edn. bout). always @(posedge clk) if (reset) qout <= {N{1'b0}}.Chapter 9: Sequential Logic Modules Binary Up/Down Counters --. eup. output cout. bout.

version 2 // the cascade of two up/down counters module up_dn_bin_counter_cascaded(clk. … output [2*N-1:0] qout. wire cout1. bout1. parameter N = 4. …). bout.eup. John Wiley 9-36 . output cout. up_dn_bin_counter #(4) up_dn_cnt2 (clk. …).eup.Chapter 9: Sequential Logic Modules Binary Up/Down Counters --. reset. …). reset. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. up_dn_bin_counter #(4) up_dn_cnt1 (clk. edn. reset.

parameter N = 4.1). else qout <= qout + 1. enable. qout. reset. // BCD counter … output reg [N-1:0] qout. end Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. parameter R= 10. John Wiley 9-37 . cout). … assign cout = (qout == R . always @(posedge clk) if (reset) qout <= {N{1'b0}}. else begin if (enable) if (cout) qout <= 0.Chapter 9: Sequential Logic Modules A Modulo r Binary Counter module modulo_r_counter(clk.

Chapter 9: Sequential Logic Modules Syllabus ™ ™ ™ ™ ™ ™ ™ ™ Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-38 .

John Wiley 9-39 .Chapter 9: Sequential Logic Modules Sequence Generators ™ We only focus on the following three circuits ƒ PR (pseudo random)-sequence generator ƒ Ring counter ƒ Johnson counter Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

Chapter 9: Sequential Logic Modules Primitive Polynomials f ( x) = ∑ ai x i = a0 + a1 x + a2 x 2 + … + an x n i =0 n Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-40 .

John Wiley 9-41 .Chapter 9: Sequential Logic Modules Maximal Length Sequence Generators Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

John Wiley 9-42 .Chapter 9: Sequential Logic Modules A PR-Sequence Generator Example ™ A 4-bit example ƒ primitive polynomial: 1 + x + x4 Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

John Wiley 9-43 . always @(posedge clk) qout <= {d. qout). parameter N = 4.Chapter 9: Sequential Logic Modules A PR-Sequence Generator Example // an N-bit pr_sequence generator module --. … assign d = ^(tap[N-1:0] & qout[N-1:0]).in standard form module pr_sequence_generate (clk. // define the default size parameter [N:0] tap = 5'b10011. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. … output reg [N-1:0] qout = 4’b0100. wire d. Q: Write an N-bit pr_sequence generator in modular form. qout[N-1:1]}.

John Wiley 9-44 . parameter N = 4. else qout <= {d.in standard form module pr_sequence_generate (clk. always @(posedge clk or posedge start) if (start) qout <= {1'b1. qout). start. qout[N-1:1]}. … output reg [N-1:0] qout.Chapter 9: Sequential Logic Modules A PR-Sequence Generator Example // an N-bit pr_sequence generator module --. // define the default size parameter [N:0] tap = 5'b10011. {N-1{1'b0}}}. wire d. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. … assign d = ^(tap[N-1:0] & qout[N-1:0]).

else qout <= {qout[N-1]. qout). … output reg [0:N-1] qout. … always @(posedge clk or posedge start) if (start) qout <= {1'b1. John Wiley 9-45 . qout[0:N-2]}. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.Chapter 9: Sequential Logic Modules Ring Counters // a ring counter with initial value module ring_counter(clk.{N-1{1'b0}}}. parameter N = 4. start.

John Wiley 9-46 . Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. parameter N = 4. … always @(posedge clk or posedge start) if (start) qout <= {N{1'b0}}. qout). start. else qout <= {~qout[N-1].Chapter 9: Sequential Logic Modules Johnson Counters // Johnson counter with initial value module ring_counter(clk. // define the default size … output reg [0:N-1] qout. qout[0:N-2]}.

John Wiley 9-47 .Chapter 9: Sequential Logic Modules Syllabus ™ ™ ™ ™ ™ ™ ™ ™ Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

Chapter 9: Sequential Logic Modules Timing Generators ™ A timing generator ™ Multiphase clock signals ƒ Ring counter ƒ Binary counter with decoder ™ Digital monostable circuits ƒ Retriggerable ƒ Nonretriggerable Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-48 .

Chapter 9: Sequential Logic Modules Multiphase Clock Signals ™ Ways of generation ƒ Ring counter approach ƒ Binary counter with decoder approach Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. John Wiley 9-49 .

John Wiley 9-50 .Chapter 9: Sequential Logic Modules Multiphase Clock Generators ™ Binary counter with decoder approach „ n = 4 and m =2 clk [1:0] enable reset + [1:0] [1:0] D[1:0] R Q[1:0] [1:0] [1:0] decode D[1:0] EQ[3:0] [3:0] [3:0] qout[3:0] bcnt_out_5[1:0] qout[3:0] bcnt_out[1:0] Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010.

reg [M-1:0] bcnt_out. … always @(bcnt_out) qout = {N-1{1'b0}. Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010. … always @(posedge clk or posedge reset) if (reset) bcnt_out <= {M{1'b0}}.Chapter 9: Sequential Logic Modules Multiphase Clock Generators // a binary counter with decoder serve as a timing generator module binary_counter_timing_generator(clk. qout). // the number of phases parameter M = 3. enable. reset.1'b1} << bcnt_out. // the bit number of binary counter … output reg [N-1:0] qout. parameter N = 8. John Wiley 9-51 . else if (enable) bcnt_out <= bcnt_out + 1.