DE THI THIET KE HE THONG SO (VHDL

)
(He Cao Dang_K12
1. D_FF dong bo
entity d is
port( D : in STD_LOGIC;
CLK : in STD_LOGIC;
Q0 : out STD_LOGIC;
Q1 : out STD_LOGIC);
end d;
architecture d of d is
begin
process (CLK,D)
begin
if CLK' event and CLK='0' then
Q0<=D ;
Q1<= NOT D;
end if;
end process;
end d;
2. D_FF khong dong bo
entity dKdb is
port(D : in STD_LOGIC;
Q0 : out STD_LOGIC;

Q1 : out STD_LOGIC);
end dKdb;
architecture dKdb of dKdb is
begin
process (D)
begin
Q0<=D ;
Q1<= NOT D;
end process;
end dKdb;
3. JK dong bo
entity jkdb is
port( J : in STD_LOGIC;
K : in STD_LOGIC;
CLK : in STD_LOGIC;
Q0 : out STD_LOGIC;
Q1 : out STD_LOGIC);
end jkdb;
architecture jkdb of jkdb is
signal x:STd_logic ;
begin
process (J,K,CLK)
begin

end if. Q1<= not x. elsif J='1' and K='1' then Q0<= not x. elsif J='0' and K='1' then Q0<='0'. JK khong dong bo entity JKkdb is port( J : in STD_LOGIC. Q0 : out STD_LOGIC. Q1<=x. 4. K : in STD_LOGIC. end if. Q1 : out STD_LOGIC). end jkdb. Q1<='1'.if CLK' event and CLK='0' then if J='0' and K='0' then Q0<=x. . elsif J='1' and K='0' then Q0<='1'. Q1<='0'. end process.

Q1<=not x. Q1<='1'. Q1<='0'. RS-FF dong bo entity rsdb is . elsif J='1' and K='0' then Q0<='1'. elsif J='1' and K='1' then Q0<=not x. elsif J='0' and K='1' then Q0<='0'. end JKkdb. architecture JKkdb of JKkdb is signal x: STd_logic . Q1<=x. end process. 5.K) begin if J='0' and K='0' then Q0<=x. begin process (J. end if.end JKkdb.

architecture rsdb of rsdb is signal x: STd_logic . Q1<='1'. if CLK' event and CLK='0' then if R='0' and S='0' then Q0<=x. Q1 : out STD_LOGIC). S. S : in STD_LOGIC. begin process (CLK. Q1<=not x. CLK : in STD_LOGIC. elsif R='1' and S='1' then . end rsdb.port(R : in STD_LOGIC. elsif R='0' and S='1' then Q0<='0'. Q0 : out STD_LOGIC. R) begin --x<=(S OR (Qn AND (NOT r))). elsif R='1' and S='0' then Q0<='1'. Q1<='0'.

end process. Q1<=not x. RS-FF khong dong bo entity RSkdb is port(R : in STD_LOGIC. end RSkdb. . Q1 : out STD_LOGIC). end rsdb. elsif R='0' and S='1' then Q0<='0'. Q1<=X. S : in STD_LOGIC. R) begin if R='0' and S='0' then Q0<=x. end if. architecture RSkdb of RSkdb is signal x: STd_logic . 6.Q0<=X. Q0 : out STD_LOGIC. begin process (S. end if.

Q1<='1'. elsif R='1' and S='1' then Q0<=X. elsif R='1' and S='0' then Q0<='1'. end process. architecture \3dauvao\ of \3dauvao\ is begin process (A. Y : out STD_LOGIC). .B. Q1<=X. Mach 3 dau vao entity \3dauvao\ is port(A : in STD_LOGIC. Q1<='0'. end RSkdb. end \3dauvao\. C : in STD_LOGIC.C) begin if A='0' and B='0' and C='0' then Y<='0'. 7. B : in STD_LOGIC. end if.

elsif A='1' and B='1' and C='0' then Y<='1'. 13. end if.elsif A='0' and B='0' and C='1' then Y<='0'. Bo dem tien entity demtien is port(clk : in STD_LOGIC. elsif A='1' and B='0' and C='0' then Y<='0'. end \3dauvao\. elsif A='1' and B='0' and C='1' then Y<='1'. y : out INTEGER range 0 to 9). elsif A='0' and B='1' and C='1' then Y<='1'. elsif A='0' and B='1' and C='0' then Y<='0'. elsif A='1' and B='1' and C='1' then Y<='1'. architecture demtien of demtien is . end process. end demtien.

14. end if. y<=a. architecture demlui of demlui is begin process (clk) variable a:integer range 9 downto 0. end demtien.begin process (clk) variable a:integer range 0 to 10. end if. end process. if (a=10) then a:=0. y : out INTEGER range 0 to 9). begin if (clk'event and clk='1') then a:=a+1. begin if (clk’event and clk=’1’) then . Bo dem lui entity demlui is port (clk : in STD_LOGIC. end demlui.

B. X2 : in STD_LOGIC. A : inout STD_LOGIC. B : inout STD_LOGIC). end if.a:=a-1. X1 : in STD_LOGIC. end demlui.X2. Bo ghep kenh 4_1 entity \4_1\ is port(X0 : in STD_LOGIC. 15. Y : out STD_LOGIC.X3) begin if A='0' and B='0' then Y<=X0.X1. if (a=0) then a:=0. end \4_1\.X0. y<=a. end process. X3 : in STD_LOGIC. end if. . architecture \4_1\ of \4_1\ is begin process (A.

X5.X3. 16. end \4_1\.X6.X2.X1. elsif A='1' and B='0' then Y<=X2. elsif A='0' and B='0' and C='1' then Y<=X1.X2. .X5.X6.X3. end process.B. Y : out STD_LOGIC.X7 : in STD_LOGIC. end if. end \8_1\.X4.X1.elsif A='0' and B='1' then Y<=X1.X0. elsif A='1' and B='1' then Y<=X3.X4. A.C. architecture \8_1\ of \8_1\ is begin process (A.X7) begin if A='0' and B='0' and C='0' then Y<=X0.B.C : inout STD_LOGIC). Bo ghep kenh 8_1 entity \8_1\ is port( X0.

. elsif A='0' and B='1' and C='1' then Y<=X3. Y0 : out STD_LOGIC. elsif A='1' and B='1' and C='0' then Y<=X6. 17. Y3 : out STD_LOGIC. elsif A='1' and B='0' and C='1' then Y<=X5. end if. Y2 : out STD_LOGIC. Bo phan kenh 1_4 entity \1_4\ is port( X : in STD_LOGIC. elsif A='1' and B='1' and C='1' then Y<=X7. end \8_1\.elsif A='0' and B='1' and C='0' then Y<=X2. end process. elsif A='1' and B='0' and C='0' then Y<=X4. Y1 : out STD_LOGIC.

Y2<='0'. end \1_4\. elsif A='1' and B='0' then Y0<='0'. architecture \1_4\ of \1_4\ is begin process (X.A : inout STD_LOGIC. Y1<='0'. Y3<='0'. Y2<='0'.B) begin if A='0' and B='0' then Y0<=X. B : inout STD_LOGIC). Y2<=X. Y3<='0'. Y1<='0'. elsif A='0' and B='1' then Y0<='0'. elsif A='1' and B='1' then . Y1<=X.A. Y3<='0'.

18.Y0<='0'. Y7 : out STD_LOGIC. C : inout STD_LOGIC ). end \1_8\. Y2<='0'. Y0 : out STD_LOGIC. end \1_4\. architecture \1_8\ of \1_8\ is . Y5 : out STD_LOGIC. Y2 : out STD_LOGIC. Y3<=X.Bo phan kenh 1_8 entity \1_8\ is port( X : in STD_LOGIC. end process. Y1 : out STD_LOGIC. Y6 : out STD_LOGIC. Y1<='0'. Y4 : out STD_LOGIC. Y3 : out STD_LOGIC. end if. A : inout STD_LOGIC. B : inout STD_LOGIC.

Y2<='0'. Y5<='0'.begin process (A. Y5<='0'. Y1<=X. Y3<='0'. Y1<='0'. Y6<='0'. Y7<='0'. elsif A='0' and B='1' and C='0' then Y0<='0'. Y3<='0'. Y6<='0'. elsif A='0' and B='0' and C='1' then Y0<='0'. Y7<='0'.C. Y4<='0'. Y2<='0'. .X) begin if A='0' and B='0' and C='0' then Y0<=X. Y4<='0'.B.

Y4<='0'. Y6<='0'. elsif A='0' and B='1' and C='1' then Y0<='0'. Y4<=X. Y3<='0'. Y5<='0'. Y1<='0'. Y2<='0'.Y1<='0'. Y3<=X. Y2<=X. Y5<='0'. Y7<='0'. Y6<='0'. Y2<='0'. . Y1<='0'. Y5<='0'. Y3<='0'. Y4<='0'. elsif A='1' and B='0' and C='0' then Y0<='0'. Y7<='0'.

Y1<='0'. elsif A='1' and B='1' and C='1' then Y0<='0'. Y2<='0'. Y5<='0'. Y7<='0'. . Y7<='0'. Y7<='0'. Y4<='0'. Y3<='0'. Y2<='0'.Y6<='0'. Y6<='0'. Y3<='0'. Y6<=X. Y5<=X. elsif A='1' and B='1' and C='0' then Y0<='0'. Y1<='0'. Y1<='0'. elsif A='1' and B='0' and C='1' then Y0<='0'. Y4<='0'.

end process. "0110011" when "0100". Y7<=X. . architecture bcd_7thanh of bcd_7thanh is begin with A select Y<="1111110" when "0000". Y6<='0'. end \1_8\.Y2<='0'. "1111001" when "0011". Y4<='0'. end bcd_7thanh. "1101101" when "0010". Y5<='0'. end if. Y3<='0'. "0110000" when "0001". "1011011" when "0101". Y : out STD_LOGIC_VECTOR(6 downto 0)). Bo chuyen ma BCD=> 7 thanh entity bcd_7thanh is port( A : in STD_LOGIC_VECTOR(3 downto 0). 21.

Y : out STD_LOGIC_VECTOR(9 downto 0)). "1111111" when "1000". "0000100000" when "0100". "0100000000" when "0001". end bcd_7thanh."1011111" when "0110". . Bo chuyen ma BCD => Thap phan entity bcd_thapphan is port(A : in STD_LOGIC_VECTOR(3 downto 0). end bcd_thapphan. "0000001000" when "0110". "0000010000" when "0101". "0000000001" when others. "0000000010" when "1000". "1111011" when others. "0000000100" when "0111". "1110000" when "0111". "0010000000" when "0010". architecture bcd_thapphan of bcd_thapphan is begin with A select Y<="1000000000" when "0000". 22. "0001000000" when "0011".

Bo chuyen ma HEX => 7 thanh entity \hex_7 thanh\ is port( X : in STD_LOGIC_VECTOR(3 downto 0). 23. "1110111" when "1010". "0111101" when "1101". "1101101" when "0010". . architecture hex_7thanh of \BCD_7 thanh\ is begin with X select Y<="1111110" when "0000". "1011011" when "0101". "0110000" when "0001". "1111001" when "0011". "1011111" when "0110". "1001110" when "1100". "1111011" when "1001". "1111111" when "1000". "0011111" when "1011".end bcd_thapphan. "0110011" when "0100". "1110000" when "0111". end \hex_7 thanh\. Y : out STD_LOGIC_VECTOR(6 downto 0)).

Bo dem so so 0 . end loop. Q : out INTEGER range 0 to 8 ). Q<=dem. end if. Bo dem so so 1 entity demso1 is port(X : in STD_LOGIC_VECTOR(7 downto 0). end demso1. for i in 0 to 7 loop if (X(i)='1') then dem:=dem+1. 27."1001110" when "1110". end hex_7thanh. "1000111" when others. 26. end demso1. end process. architecture demso1 of demso1 is begin process (X) variable dem: INTEGER range 0 to 8. begin dem:=0.

end if. . end process. end \3_8\. end demso0. architecture demso0 of demso0 is begin process (X) variable dem: INTEGER range 0 to 8.entity demso0 is port(X : in STD_LOGIC_VECTOR(7 downto 0). end loop. begin dem:=0. 29. for i in 0 to 7 loop if (X(i)='0') then dem:=dem+1. Bo ma hoa 3_8 entity \3_8\ is port(A : in STD_LOGIC_VECTOR(0 to 2). Q<=dem. Q : out INTEGER range 0 to 8). Y : out STD_LOGIC_VECTOR(0 to 7)). end demso0.

"001" when "01000000". "01000000" when "001".architecture \3_8\ of \3_8\ is begin with A select Y<="10000000" when "000". Bo ma hoa 8_3 entity \8_3\ is port( X : in STD_LOGIC_VECTOR(7 downto 0). . end \3_8\. 30. "00000100" when "101". "00001000" when "100". architecture \8_3\ of \8_3\ is begin with X select Y<="000" when "10000000". "00000001" when others. "00000010" when "110". "00100001" when "010". Y : out STD_LOGIC_VECTOR(2 downto 0)). end \8_3\. "010" when "00100001". "00010000" when "011".

HET . "100" when "00001000"."011" when "00010000". "101" when "00000100". "110" when "00000010". end \8_3\. "111" when others.