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2, FEBRUARY 2012


Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
Jaydeep P. Kulkarni, Member, IEEE, and Kaushik Roy, Fellow, IEEE
Abstract—We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read-stability as well as better write-ability compared to the standard 6T bitcell. The proposed ST bitcells incorporate a built-in feedback mechanism, achieving process variation tolerance—a must for future nano-scaled technology nodes. A detailed comparison of different bitcells under iso-area condition shows that the ST-2 bitcell can operate at lower supply voltages. Measurement results on ten test-chips fabricated in 130-nm CMOS technology show that the proposed ST-2 bitcell gives 1.6 higher read static noise margin, 2 higher write-trip-point and 120-mV lower read- min compared to the iso-area 6T bitcell.


Index Terms—Low-voltage SRAM, process tolerance, SchmittTrigger (ST), min .




ORTABLE electronic devices have extremely low power requirement to maximize the battery lifetime. Various device-/circuit-/architectural-level techniques have been implemented to minimize the power consumption [1]. Supply voltage scaling has significant impact on the overall power dissipation. With the supply voltage reduction, the dynamic power reduces quadratically while the leakage power reduces linearly (to the first order) [1]. However, as the supply voltage is reduced, the sensitivity of circuit parameters to process variations increases. This limits the circuit operation in the low-voltage regime, particularly for SRAM bitcells employing minimum-sized transistors [2], [3]. These minimum geometry transistors are vulnerable to interdie as well as intradie process variations. Intradie process variations include random dopant fluctuation (RDF) and line edge roughness (LER). This may result in the threshold voltage mismatch between the adjacent transistors in a memory bitcell, resulting in asymmetrical characteristics [4]. The combined effect of the lower supply voltage along with the increased process variations may lead to increased memory failures such as read-failure, hold-failure, write-failure, and
Manuscript received April 01, 2010; revised August 30, 2010; accepted December 01, 2010. Date of publication January 31, 2011; date of current version January 18, 2012. This work was supported in part by Boeing, Defense Advanced Research Projects Agency (DARPA), Semiconductor Research Corporation (SRC), Focus Center Research Program (FCRP-C2S2), and Intel Foundation Ph.D. Fellowship Program. J. P. Kulkarni is with Circuit Research Laboratory, Intel Corporation, Hillsboro, OR 97124 USA (e-mail: K. Roy is with School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-1285 USA (e-mail: kaushik@ecn.purdue. edu). Digital Object Identifier 10.1109/TVLSI.2010.2100834

access-time failure [4]. Moreover, it is predicted that embedded cache memories, which are expected to occupy a significant portion of the total die area, will be more prone to failures with scaling [2]. In a given process technology, the maximum supply voltage ) for the transistor operation is determined (referred to as by the process constraints such as gate-oxide reliability limits. is reducing with the technology scaling due to scaling of gate-oxide thickness. The minimum SRAM supply voltage, ), is for a given performance requirement (referred to as limited by the increased process variations (both random and die-to-die) and the increased sensitivity of circuit parameters at is inlower supply voltage. With the technology scaling, and [5]. creasing, and this closes the gap between Hence, to enable SRAM bitcell operation across a wide voltage has to be further lowered. Various design solutions range, such as read-write assist techniques and bitcell configurations have been explored. Read-write assist techniques control the magnitude and the duration of different node biases (such as word-lines, bitlines, bitcell VSS node, and bitcell VCC node) can be lowered without adding [5]. In this case, SRAM extra transistors to the six–transistor (6T) bitcell. Various bitcell topologies are also proposed to enable low-voltage operation. In this work, we focus only on various bitcell configurations. We believe that read-write assist circuits can be applied to these bitreduction. cell configurations for further The remainder of this paper is organized as follows. Section II describes various previously published SRAM bitcells. Section III briefly presents the Schmitt-Trigger (ST)-based SRAM bitcells. Section IV shows the detailed comparison of various bitcell topologies. Section V presents the measurement results. Section VI summarizes the low-voltage SRAM design discussion.

II. PREVIOUS SRAM BITCELL RESEARCH Several SRAM bitcells have been proposed having different design goals such as bit density, bitcell area, low voltage operation and architectural timing specifications. Fig. 1 lists the SRAM bitcells having four to ten transistors [6]–[27]. In the four–transistor (4T) loadless bitcell, pMOS devices act as access transistors [6]. The design requirement is such that pMOS OFFstate current should be more than the pull-down nMOS transistor leakage current for maintaining data “1” reliably. With increasing process variations and exponential dependence of the subthreshold current on the threshold voltage, satisfying this design requirement across different process, voltage, and temperature (PVT) conditions may be challenging.

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20. The intermediate read bitline precharge voltage requires a dc–dc converter.320 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. FEBRUARY 2012 Fig. 2. 5T bitcell consists of asymmetric cross coupled inverters with a single bitline [7]. 1. Tracking the read precharge voltage across PVT corners would require additional design margins in bitcell sizing and may limit its ap- . NO. VOL. Published SRAM bitcell configurations [6]–[24]. Separate bitline precharge voltages are used for read and write operations.

. 2. This robust process tolerance can be an essential attribute for SRAM scaling into future nanoscaled technology nodes. In a single-ended 9T bitcell. The first ST-based SRAM bitcell has been presented in our earlier work [30]. the contents of which can be accessed by two nMOS access transistors. Two novel bitcell designs are proposed. [20]. as shown in input transition. read-bitline toggling is avoided. if the the accessed data are unchanged. device sizing has been adopted to mitigate the effect of process variations.KULKARNI AND ROY: ULTRALOW-VOLTAGE PROCESS-VARIATION-TOLERANT ST-BASED SRAM DESIGN 321 plicability. Liu and Kursun have proposed a 9T bitcell with differential read-disturb-free operation [18]. have proposed a single-ended transmission-gate 10T bitcell [25]. The ST-1 bitcell utilizes differential sensing with ten transistors. differential 8T bitcells utilizing RWL/WWL cross-point array and data-dependent VCC have also been reported [21]. This results in higher switching threshold of the inverter with very sharp transfer characteristics. we need a different design approach for successful low voltage SRAM design in nanoscaled technologies. A 6T bitcell comprises of two cross-coupled CMOS inverters. Single-ended 10T bitcells are similar to the single-ended 8T bitcell except for the read port configurations. In all of the previously reported bitcells. SCHMITT TRIGGER (ST) SRAM BITCELLS In order to resolve the conflicting read versus write design requirements in the conventional 6T bitcell. This results in read-disturb-free operation. input-dependent transfer characteristics of the Schmitt trigger improves both read-stability as well as write-ability of the SRAM bitcell.” by a higher switching threshold with sharp transfer characteristics of the Schmitt trigger gives robust read operation. Single-ended write operation in this 7T bitcell needs either asymmetrical inverter characteristics or differential VSS/VCC bias. A Schmitt trigger is used to modulate the switching threshold of an inverter depending on the direction of the input transition [29]. we apply the Schmitt Trigger (ST) principle for the cross-coupled inverter pair. 2. the extra transistor is turned OFF. [24]. Fig. Thus. Write-ability is achieved by modulating the virtual-VCC and virtual-VSS of one of the inverters. Takeda et al. Successful write operation necessitates skewed inverter sizing. A. [10]. the stability of the cross-coupled inverter is important. Feedback transistors NFL/NFR raise the switching threshold of the inverter input transition giving the ST action. the ST bitcell in [30] is termed the “ST-1” bitcell while the other ST bitcell in [31] is termed the “ST-2” bitcell. A single-ended 6T bitcell uses a full transmission gate at one side [8]. input transition. During read mode. Chang et al. [22]. extra transistors are added to the conventional 6T bitcell to separate read and write operation [13]–[17]. In the proposed ST SRAM bitcells. the feedback mechanism is used only in the pull-down path. and Suzuki consists of single-ended write operation and a separate read port [9]. device sizing is not effective in improving the bitcell stability at very low supply voltage [28]. the basic element for the data storage is a cross-coupled inverter pair. Since a read-failure is initiated input transition for the inverter storing logic “1. A similar 10T cell with column-assist technique is also reported. Detailed during the operation of the ST-1 bitcell can be found in [30]. and two bitlines (BL/BR). have proposed a read-disturb-free differential 10T bitcell which is suitable for bit-interleaved architecture [26]. A differential 10T bitcell with two separate ports for read-disturb. Noguchi et al. one word-line (WL). 3 shows the schematics of the ST-1 bitcell. ST-1 Bitcell Fig. Traditionally. ! Hence. Transistors PL-NL1-NL2-NFL form one ST inverter while PR-NR1-NR2-NFR form another ST inverter. Extra transistors are added to decouple the read and write operations. Additional transistors are used to control the read bitline leakage [23]. [27]. the feedback mechanism For the is not operation has also been reported [25]. the feedback transistor Fig. separate read port is used to decouple read and write operation which is similar to the single-ended 8T bitcell. Also. For successful SRAM operation under PVT variations. To maintain the clarity of the discussion. resulting in asymmetrical noise margins. Thus. However. This results in smooth transfer characteristics that are essential for easy write operation. The single-ended 7T bitcell proposed separately by Tawfik et al. Stacked read access transistors are used to reduce the bitline leakage [19]. Conceptual ST schematics: the gate connection of the feedback transistor is connected to the VCC to show the feedback mechanism during 0 1 input transition. isolating the corresponding storage node from VSS. have proposed another single-ended 7T bitcell in which an extra transistor is added in the pull-down path of one of the inverters [11]. In a differential 7T bitcell. read bitline does not require precharge and keeper transistor. In this work we propose Schmitt Trigger based SRAM bitcell having built-in feedback mechanism that exhibits the process variation tolerance. III. series-connected write access transistors degrade the write-ability of the bitcell and needs write-assist circuits such as word-line boosting for a successful write operation. the feedback between the two inverters is cut off during the write operation [12]. In a single-ended 8T bitcell. The bitcell contents are buffered using an inverter and then transferred to the read bitline whenever the bitcell is accessed. Recently. During ) node by (NF) tries to preserve the logic “1” at output ( raising the source voltage of pull-down nMOS (N1). Another ST-based SRAM bitcell which further improves the bitcell stability has been reported in [31]. The 6T bitcell is the “de facto” memory bitcell used in the present SRAM designs. Use of the transmission gate eliminates domino-style read-bitline sensing. None of the previously reported bitcells incorporate process variation tolerance for improving the stability of the cross coupled inverter pair of an SRAM bitcell operating at ultralow supply voltage. However.

This would increase the bitline capacitance and hence the bitline power consumption. the 8T iso-area bitcell evaluated at iso-subarray area condition. the vertical dimension is determined ANALYSIS by the poly pitch while lateral dimension is determined by the device sizing. Thus. all transistors in the 6T mincell are upsized uniformly to improve the readstability and write-ability simultaneously. [31]. while WWL signal is asserted during the write operation. During the hold-mode. 4 shows the schematics of the ST-2 bitcell utilizing differential sensing with ten transistors. In the ST-2 bitcell. Once the storage nodes start transitioning from one state to another state. In a thin-cell layout approach. Local bitline (LBL) containing 8/16/32 bitcells is evaluated using the read-merge logic (NAND gate in Fig. Fig. the 6T mincell device widths need to be upsized by 4 . This would increase word-line capacitance and hence word-line switching power. 1) 6T Iso-Area Bitcell: In this work. IV. Hence. respectively. Hence. 6 shows the single-ended sensing 8T bitcell organization [34]. in order to estimate the . to maintain the dynamic node voltage. 5 shows the thin-cell illustrative layout of the 6T mincell and the proposed ST-2 bitcell. A second stage of Global bitline (GBL) combines multiple LBL stages. Due to a difference should be in the array efficiency. hierarchical bitline sensing is used. However. we use 6T mincell device widths of 100. Bitcell areas are normalized to 6T mincell area. present 6T bitcell designs utilize differential sensing mechanism resulting in 65%–75% array efficiency [36]–[39]. Bitcell failure probability is estimated assuming Gaussian distribution of the threshold voltage [3]. Iso-Area Bitcells area compared The ST bitcells consumes approximately with the 6T mincell [30]. FEBRUARY 2012 Fig. separate control signal WL is employed for achieving stronger feedback. Careful examination of various industrial minimum–sized 6T bitcell layouts reveal that only 30%–35% of the lateral dimension contributes to the device widths while remaining lateral dimension is used for the contact and diffusion spacing [32]. The bitcell area is estimated following the layout rules in [33]. and two bitlines (BL/BR). 100. For 2 larger area. ST-2 bitcell schematics. Since bitline power is the dominant component of the overall power consumption. single-ended 8T bitcell array efficiency is 30–50% [5]. [33]. Monte Carlo simulations are performed using 65-nm industrial process technology models which include systematic as well as random process variations. The keeper device supplies the leakage current of the pull-down path. the channel lengths of SRAM transistors may not be set to arbitrary value in a scaled process due to lithography limitations. To improve the feedback mechanism. VOL. B. the feedback mechanism is lost. feedback is provided by separate control signal (WL) unlike the ST-1 bitcell. Due to large signal sensing and delay/noise tradeoff at the local bitline node. due to segmented bitline and the associated read-merge logic. 4. where in feedback is provided by the internal nodes. the vertical dipoly-pitch) for the mension along the bitline is unchanged ( bitcell upsizing. 2. two word-lines (WL/WWL). [30]. We can upsize the 6T mincell in various ways. the SRAM bitcell area is dominated by the contact and the diffusion spacing. In general. 3. In the ST-1 bitcell. it would affect its write-ability and vice versa. Hence. The WL signal is asserted during read as well as the write operation. Detailed operation of the ST-2 bitcell is explained in our earlier work [31]. For the LBL stage. If the bitcell is upsized to be more read-stable. 6). Table I shows the split-up of the total subarray area containing 6T/8T/ST bitcells. a tradeoff exists between the LBL evaluation delay and the noise immunity. 8T (ST) bitcell area is 30% (100%) larger than the 6T mincell [13]–[17]. As seen in Fig. [35]. Any upsizing is realized in the lateral direction by increasing the device widths along the word-line. it is only fair to compare the bitminimum supply voltage cells under iso-area condition. the feedback mechanism is effective as long as the storage node voltages are maintained. Increasing the channel length increases bitcell area along the bitline direction. and 200 nm for pull-up/access/pulldown transistors. both WL and WWL are OFF. Fig. Note that. only one word-line in the subarray is active during a read/write operation. ST-1 bitcell schematics. 20. [31]. SRAM BITCELL A. a weak pMOS device called a keeper is used. increasing device widths linearly increases the bitcell area sublinearly. 2) 8T Iso-Area Bitcell: Fig.322 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. On the other hand. 5. NO. ST-2 Bitcell Fig. The array efficiency for single-ended . this approach of bitcell upsizing would result in minimal increase in power dissipation. As keeper device opposes discharging of the LBL node.

any additional area is used to increase the write-access transistor by 2 for iso-area comparison. Note that any other suitable threshold criteria can be used in is determined at estimating read-failure probability. Therefore.KULKARNI AND ROY: ULTRALOW-VOLTAGE PROCESS-VARIATION-TOLERANT ST-BASED SRAM DESIGN 323 Fig. As shown in Table I.e. Single-ended sensing 10T bitcells occupy 1.6 area compared with the 6T mincell area [23]. the bitcell contents can be flipped due to thermal noise. 7). any additional area increase can be used for upsizing the write access transistors to improve the . bitcell topologies used for B. As 8T bitcell can be upsized by has read-disturb-free operation. the write access transistors in this bitcell are upsized by 2 to give the same area as that of the ST bitcells (Fig. TABLE I SUBARRAY AREA ANALYSIS OF 6T/8T/ST BITCELL transistors are upsized by 3 compared to the 6T mincell case (Fig. Hence. for iso-area condition. 5. The differential 10T bitcell with two separate read ports consumes larger area compared with the 6T mincell. Read-Failure Probability Read static noise margin (SNM) is used to quantify the readstability of the SRAM bitcells. The 10T bitcell proposed by Chang et al. These bitcells together are referred to as “differential 10T bitcells” hereafter. the 6-sigma read-failure probability (i. For iso-area comparison. 6. is another differential sensing bitcell without any read-disturbs [26].. 8T SRAM: hierarchical bitline sensing mechanism. 6T bitcell upsizing approach: area versus device widths. for iso-area condition 8T bitcell . any additional area is used to upsize the write-access transistors. 8). Table II lists device sizing for various analysis. [24]. Read-failure ) is estimated as probability ( and the differential sensing is assumed to be 50% and 70% respectively. 3) 10T Iso-Area Bitcell: A 10T bitcell with additional read ports sutilize differential sensing without disturbing the bitcell nodes during a read operation [25]. Therefore. The SNM is estimated graphically as the length of a side of the largest square that can be embedded inside the lobes of the butterfly curve [40]. . Single-ended 10T bitcells utilize read-disturb free operation. Fig. Read). for iso-area 8T bitcell. the write-access write- If read SNM is lower than the thermal voltage ( 26 mV at 300 K).

read-failure probability in 8T/10T bitcell is lower than the ST bitcells. Fig. . 20. read-stability is same as the hold-mode stability as bitcell nodes are not disturbed during the read operation. As the cross-coupled inverter size in the 8T/10T bitcell is same as that for the 6T mincell. Lower read-failure probability would transin 8T/10T bitcell compared with the late into lower readST bitcells. 9 plots read-failure probability versus supply voltage for various 6T bitcell sizing. 10. 8. Thus. FEBRUARY 2012 Fig. 7. Iso-area 8T thin-cell layout. VOL. For 8T and 10T bitcells. NO.324 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2. It is found that built-in process tolerance in the ST-2 bitcell gives lower read-failure probability compared with the iso-area 6T bitcell. TABLE II DEVICE SIZING FOR VARIOUS BITCELL TOPOLOGIES Fig. it would show similar hold-failure probability as shown in Fig. Iso-area differential 10T cell layout.

10 shows the hold-failure probability variation versus supply voltage for 6T and ST bitcells. WL and WWL control signals are asserted. ) is calculated as write-failure probability ( 0 mV Writeis determined at the 6-sigma write-failure proba). Single-ended 10T bitcells would result in writesimilar to the 8T bitcell.e. 10. absence of a feedback mechanism and series-connected Fig. The higher the 0-side bitline write-trip-point voltage. As ) is estimated shown in inset. This gives lower compared to the hold-failure probability and lower holdminimum sized ST-1 and ST-2 bitcells. D. Hold-Failure Probability Similar to the read stability case. Hence. ST bitcells compared with the 8T/10T bitcell. hold-failure probability ( as Holdis determined at the 6-sigma hold failure probability ). bitcells give lower writeFor ST-2 bitcell. 12 shows the comparison of write-failure probability for 8T and ST bitcells under iso-area condition. Upsizing the write-access transistor in 8T bitcell improves its write-ability. Write-trip-point defines the maximum 0-side bitline voltage needed to flip the cell content [41]. Write-Failure Probability Write-ability of a bitcell gives an indication of how easy or difficult it is to write to the bitcell. the easier it is to write to the cell.KULKARNI AND ROY: ULTRALOW-VOLTAGE PROCESS-VARIATION-TOLERANT ST-BASED SRAM DESIGN 325 Fig. In case of ST-1 and ST-2 bility (i. Consequently. 9. Fig. 4). dimensions give robust inverter characteristics. It is observed that upsizing 6T device (i. bitcell. As explained above. WL and WWL control signals are OFF during the hold-mode (Fig. hold-stability is estimated by computing the hold SNM. ST bitcells with series connected pull-down transistors give lower write-failure probability and lower writecompared to 8T bitcell. As shown in inset. Fig. For the ST-2 bitcell. 10. ST bitcells show lower hold-failure probability compared with the 6T mincell. Fig. C. Fig. 11 shows the write-failure probability variation versus supply voltage. 6T versus ST bitcell: read-failure probability comparison. resulting in lower write-failures compared with the ST-1 bitcell.. As shown in Fig. 11. However.. 13 shows the writefailure probability comparison of the differential 10T bitcells and the ST bitcells under iso-area condition. 6T versus ST bitcell: write-failure probability comparison. the cross-coupled inverter pair size in 8T /10T bitcell and 6T mincell are same. pull-down nMOS transistors result in higher write-trip point compared with the 6T bitcell.e. Fig. the proposed ST compared with the 6T bitcell. would yield lower holdNote that ST-1 bitcells having internal node-based feedback give improved hold-failure characteristics compared with the ST-2 bitcell. it would result in similar hold-failure probabilities. 6T versus ST bitcell: hold-failure probability comparison. The proposed ST-2 bitcell gives the lowest write-failure probability and hence the .

e. 8T versus ST bitcell: write-failure probability comparison. E. Fig.. Hence. the access-time failure depends on array organization viz.326 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. word-line pulse-width. minimum bitline differential). 12. It has been shown that. 13. bitline leakage. lowest writecompared with the differential 10T bitcells. bitcell read-current. 15. 15 shows the . VOL. Fig. In this case. Data pattern for the worst case bitline leakage is used (i. One hundred twenty-eight bitcells are assumed on a column. in. As the bitline differential depends on the word-line pulse-width. sense amplifier’s output may not resolve correctly resulting in incorrect data value. is determined at the 6-sigma access time failure Accessprobability (i. If this bitline differential is less than the sense amplifier input offset voltage. it is essential to obtain the variation of clock frequency with the supply voltage scaling (Fig. access-time failure probability ( calculated as where word-line pulse-width. NO. The differential 10T bitcell proposed by Chang et al. Clock frequency variation with supply voltage. 14). contains two series-connected write-access transistors which degrades the write-ability of the bitcell. Fig. ). FEBRUARY 2012 Fig. 6T versus ST bitcell: access-time failure probability comparison. Fig. 10T versus ST bitcell: write failure probability comparison. 2. the delay of 20 minimum-sized FO4 (fan out of 4) inverters is assumed to be one clock period. the inverse of gives normal distribution stead of ) is [42]. The SRAM cycle time is one clock period in which the word-line is activated in the first phase and the sense amplifier is activated in the next phase. For a given supply voltage. 20.e. column multiplexer series resistance and sense amplifier offset voltage. bitline capacitance (number of bitcells/column). Access-Time Failure Probability ) is defined as the time required to Access-time ( 50 mV) produce a prespecified voltage difference ( between two bitlines. 14.

it would result in similar access-time failure characteristics (Fig. Fig. higher write-trip-point in . resulting in lower access-time failure probability and lower ac. 128 bitcells are arranged as shown in Fig. ST-2 bitcell gives higher read current compared with cessthe ST-1 bitcell. The delay from RWL turn-ON to global bitline (GBL) evaluation is termed as the access-time. Iso-Area Comparison for various bitcell Table III compares the estimated comparison of 6T/8T/10T/ST topologies. At iso-area condition. 17. Built-in feedback mechanism in ST-2 bitcell improves the read-stability. This analysis indicates that differential sensing can give higher performance compared to the single-ended sensing. Iso-area V Fig. ). differential sensing ST bitcells show improved access time compared to the single-ended sensing 8T bitcell. Fig. F. 16. ST-1 bitcell shows better access-time failure probability due to lower bitline capacitance compared with the ST-2 bitcell case. as observed in [43]. 6. In addition. For the differential 10T bitcell. the read access transistors are sized to have same read current as that of the 6T bitcell. It is found that upsized 6T bitcells give higher read-current compared with ST-1 and ST-2 bitcells. is calculated as at 6-sigma failure probability ( As seen in Fig. access-time failure probability variation versus supply voltage for 6T and ST bitcells. For the 8T bitcell. the ST-2 bitcell shows the lowest of 617 mV. 17 shows of a bitcell is determined bitcells under iso-area condition.KULKARNI AND ROY: ULTRALOW-VOLTAGE PROCESS-VARIATION-TOLERANT ST-BASED SRAM DESIGN 327 Vmin COMPARISON OF VARIOUS BITCELL TOPOLOGIES TABLE III Fig. 15). Single-ended 10T bitcells would show access-time characteristics similar to 8T bitcells. 16 shows the access-time failure probability comparison of the 8T bitcell and ST bitcells. However. 17. comparison of 6T/8T/10T/ST bitcells. 8T versus ST bitcell: access-time failure probability comparison.

We believe that these techniques can be apreduction. 20. Captured read and hold mode characteristics at 300 mV. VOL. 21). Iso-area bitcell leakage current comparison. Fig. ST-2 bitcell improves the write-ability. Read-SNM measurements on 10 test-chips show that the proposed ST-2 bitcell on an average gives 58% higher read-SNM ). 22. isolated-cell SNM measurement would be equivalent to the actual SRAM array bitcells. FEBRUARY 2012 Fig. built-in self-test circuit was designed [44]. the proposed ST-2 bitcell exhibits improved read/hold mode characteristics compared to the conventional 6T bitcell. Fig. ( 110 C. SRAM tester circuit is described in our earlier work [31]. In order to characterize the memory failure statistics. It is found that iso-area 6T bitcell due higher leakage as to 4 upsized transistors consumes compared with the ST bitcells. The finger structure would result in transistors having threshold voltage ( ) same as that of the transistor used in the bitcell array. Measurements were done on ten different test-chips to fully characterize both 6T and ST bitcell.3 ) to achieve reduction. NO. Read SNM measurement with ten test-chips. Thus. Note that the by 3. 6T mincell transistor widths need to be upsized by 8 (bitcell area increased same as the ST-2 bitcell. 19 shows the captured voltage transfer characteristics during the and axes represent read and the hold mode in which the the voltages at the storage nodes. 20 ( The hold-SNM for 6T and ST-2 bitcell is found to be almost same (Fig.328 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 10T differential and ST bitcells show comparable leakage current. separate isolated 6T/ST-2 bitcells with each transistor having ten fingers were fabricated. Fig. The improvement in ST-2 bitcell read-SNM is consistent across different supply voltages as shown in Fig. the ST-2 bitcell consumes lower leakage than the ST-1 bitcell. This is because. The write-trip-point was determined by performing the weak-write-test [45]. we do not account the effect of various read/write assist techniques [5]. For DC measurements. Further. typical corner). plied to the bitcell topologies for further G. In spite of the read-disis limited turb-free operation in 8T and 10T bitcells. 2. For this technology. This graph clearly shows that Fig. in the ST-2 bitcell. 18. Guard rings and dummy fingers (transistors) were implemented for the isolated cell layout in order to minimize the effect of process bias on the finger structures. 20. Measured results show that the ST-2 higher write-trip-point compared to the 6T bitcell gives . their by the write operation. MEASUREMENT RESULTS A test-chip with 2Kb SRAM array containing 6T and ST-2 bitcells has been fabricated in 130-nm CMOS technology. 19. Leakage Current Comparison Leakage current is an important parameter in the bitcell design. 18 shows bitcell leakage comparison of 6T/8T/10T/ST bitcells under iso-area condition in 65 nm technology. In this bitcell upsized ST bitcells show further analysis. compared with 6T bitcell as shown in Fig. both feedback transistors are OFF in the hold mode unlike the ST-1 bitcell in which only one of the feedback transistors is OFF. V.

26. Write-trip-point measurement with ten test-chips. Using the on chip tester circuit. Fig. Fig. Measured write-trip-point versus VCC for one test-chip. Fig. 25. 28 shows the die photograph and the test-chip measurement summary. As shown in Fig. At 300 mV.KULKARNI AND ROY: ULTRALOW-VOLTAGE PROCESS-VARIATION-TOLERANT ST-BASED SRAM DESIGN 329 Fig. Also. Supply voltage was reduced gradually and read failures were counted using the built-in counter. Hold SNM measurement with ten test-chips. the operating frequency is 270 kHz with leakage Fig. the proposed ST-2 bitcell with built-in feedback mechanism compared to the standard achieves 120 mV lower read6T bitcell. Supply voltage was reduced gradually to determine the correct read functionality. The clock frequency was kept low to avoid access-time failures. 27). 26). 24. was determined as the highest supply voltage Readwhere the first read failure occurred. Fig. Fig. 23. 24). Measured read failure statistics for ten test-chips. it is found that the weak-write-test (WWT) voltage is higher in the ST-2 bitcell compared to the 6T bitcell. for the proposed ST-2 bitcell was The best case read150 mV at 500 Hz (Fig. Fig. Since the ST bitcells consume 2 . ten test-chips were characterized for failure statistics. power consumption of 0. Measured leakage current versus VCC for five test-chips. bitcell ( 300 mV.11 W (Fig. 21. Measured read/hold SNM versus VCC. 25. 29 shows the possible application space for the proposed ST-2 bitcell. 22. Fig. 23) which is consistent across wide range of supply voltage (Fig.

and A. 2001. Noda. 1st ed. [8] B. Circuit Design Technol. D. Electron Devices. Mahmoodi. Yoshinobu. 2. we evaluated ST-based SRAM bitcells suitable for ultra-low-voltage applications. Kursun. K. 24. “A loadless CMOS four-transistor SRAM cell in a 0. vol. for a given constraint. Solid State Circuits Conf. FEBRUARY 2012 the proposed ST bitcells can potentially be useful in applications requiring ultra low voltage. Alvandpour. and J. Takayuki. pp. Park for their help during the measurements. 2007. Int. [1] K. 1859–1880. Sylvester. Circuits Syst.. Devel. However.. low-voltage SRAM operation in future nanoscaled technologies. “Read and write circuit assist techniques for improving Vccmin of dense 6T SRAM cell. 2851–2855. Apr. “Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. 4. no. CONCLUSION Lowering the supply voltage is an effective way to achieve ultra-low-power operation. Recently. Carlson. . Fig. 12. Blaauw.” in Proc. pp. H. [2] N. Res. The authors would also like to thank MOSIS for testchip fabrication REFERENCES Fig. 658–665. X.. at iso-area. 20. and V. S. Integr. Solid State Circuits Conf/. T. no.” in Proc. “The impact of intrinsic device fluctuations on CMOS SRAM cell stability. Comput. 215–218. 15). D. P. pp. K. pp. vol. Andersson. Int. H. Zhai. [3] A. De. Int. The built-in feedback mechanism in the proposed ST bitcell can be effective for process-tolerant. Khellah. vestigated for achieving lower ACKNOWLEDGMENT The authors would like to thank Dr. Dec. have proposed the use of ST-1 bitcell for tag-arrays to achieve low voltage cache operation [46]. and K. 27.” IEEE Trans. pp. Meindl. pp. no. ST bitcells offer low voltage operation with 2 area overhead. no. the effectiveness of read/write assist techniques for each of the bitcell topology needs to be in. “A sub-200 mV 6 T SRAM in 0. 5T SRAM for embedded caches. [4] S. Measurement results with a 130-nm test-chip clearly demonstrate the effectiveness of the proposed ST-2 bitcell for successful ultralow-voltage operation. 47. the upsized 6T bitcell has better performance compared with the ST bitcells (Fig. 28. 2008. Hence. Circuits Syst. Tang. Bhavnagarwala. larger area compared with the 6T mincell. Masahi. with lower area overhead. Future Work In this paper.” IEEE J. Symp. On the other hand. Natarajan. due to built-in process tolerance. S. [7] I. 6T/8T/10T/ST SRAM bitcell topologies are analyzed for achieving low voltage operation. Karnik. 30th Eur. [6] K. 5/6. Fig.330 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. Tawfik and V. pp. various read/write assist techniques achieve significant reduction. 29. [5] M. Somasekhar. A.” in Proc. vol. Roy and S. D. ST SRAM bitcells: application space. [9] S. Nakamura.18-m logic technology. Keshavarzi.. Monte Carlo simulations in for the proposed ST-2 65-nm technology predict lower bitcell under the iso-area condition. K. 2008.. VI. low leakage. VOL. 2005. Matsui. and K. M. Takeda. ST-2 bitcell read operation at 150 mV/500 Hz. 332–333.13 m CMOS. NO. “Low power and robust 7T dual-Vt SRAM circuit. 525–552. Dec. In this work. 12. “A high density. 2003. Low Power CMOS VLSI Circuit Design. Conf. 1452–1455. 2001. 2004. 12. Hanson. 185–189. Sep. K. Itoh. New York: Wiley. 2000. “Review and future prospects of low-voltage RAM circuits.-Aided Design (CAD) Integr.” IBM J. vol. Kim and S.” in Proc. Prasad. Thus. Solid-State Circuits. and S. Jun.” IEEE Trans. A. optimal combination of the bitcell topology read/write assist technique should be chosen for minimal area/power overhead. Wilkerson et al. Mukhopadhyay. Die photograph and chip measurement summary. Roy. and N. pp. 36. Feb.

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Kharagpur. VLSI testing and verification. the ATT/Lucent Foundation Award. K. the Purdue College of Engineering Research Excellence Award. TX. where he is currently a Professor and holds the Roscoe H. the 2000 IEEE International Symposium on Quality of IC Design. 2000) and Low-Voltage Low-Power VLSI Subsystems (McGraw-Hill. the IBM Faculty Partnership Award. He was a Research Visionary Board Member of Motorola Labs (2002) and held the M. the 2006 IEEE/ACM International Symposium on Low Power Electronics & Design. Texas Instruments. Roy was the recipient of the National Science Foundation Career Development Award in 1995.D. Dr. the 2003 IEEE Latin American Test Workshop. Urbana. IN. He has authored or coauthored more than 500 papers in refereed journals and conferences. degree in electronics and electrical communications engineering from the Indian Institute of Technology. and the 2006 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Best Paper Award. the 2005 IEEE Circuits and System Society Outstanding Young Author Award (with Chris Kim). FEBRUARY 2012 Kaushik Roy (F’09) received the B. 2. He was with the Semiconductor Process and Design Center. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign. and the Ph.332 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. the 2005 SRC Technical Excellence Award. West Lafayette. graduated 50 Ph. and the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 20. VOL. and reconfigurable computing. and is the coauthor of two books. in 1993. NO. He was Guest Editor for special issue on low-power VLSI in IEEE Design and Test (1994) and the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (June 2000). students. 2003 IEEE Nano. Dallas. He joined the Electrical and Computer Engineering Faculty. He was a guest editor for a special issue on low-power VLSI for IEE Proceedings—Computers and Digital Techniques (July 2002).Tech. the 2004 IEEE International Conference on Computer Design. holds 15 patents. He has been in the editorial board of IEEE Design and Test. George Chair of Electrical and Computer Engineering. . the SRC Inventors Award. low-power electronics for portable computing and wireless communications. India. His research interests include spintronics. Low-Power CMOS VLSI Circuit Design (Wiley. and Best Paper Awards at the 1997 International Test Conference. VLSI design/CAD for nano-scale silicon and non-silicon technologies. the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. Gandhi Distinguished Visiting faculty at the Indian Institute of Technology (Bombay). the Humboldt Research Award in 2010. IL.D. Purdue University. He is a Purdue University Faculty Scholar. where he was involved with FPGA architecture development and low-power circuit design. 2004). in 1990.