76 views

Uploaded by Rishi Kant Sharma

Thevenins theorm STUDY MATERIAL IMP FOR GATE, IES etc

Thevenins theorm STUDY MATERIAL IMP FOR GATE, IES etc

Attribution Non-Commercial (BY-NC)

- Circuits+Lab+Manual Lab2
- Circuit Theory - Solved Assignments - Semester Summer 2007
- EEE 209 Presentation 3 (Circuits Cont)
- Thevenin Norton
- May 2015
- VLSI_CHP14
- Nd Lab Manual
- Signal_Integrity
- Battery Testing
- EEE1-lecture02
- Magnitic theroy
- Direct Digital-Frequency Synthesis by Analog Interpolation
- Usm 36 Operation Manuals Espanol
- تكنولوجيا الإنتاج الوصف التفصيلي
- Chap9 Network Theorems
- memrister
- final_04
- TEA1532P
- Max 17020
- P-97-17.ps

You are on page 1of 12

1.1 Background

Thevenins theorem: Consider a network consisting of dc independent sources (current/voltage sources), dependent sources (linear), and resistors. We are interested in the port behaviour of this circuit, i.e., in a simplied description of the circuit as seen from the port AB (see Fig. 1.1 (a)). Thevenins theorem gives us this simplied description (see Fig. 1.1 (b)) in terms of a single voltage source VTh and a single resistor RTh .

Circuit (resistors, voltage sources, current sources, CCVS, CCCS, VCVS, VCCS) (a)

A RT h VT h B

(b)

Figure 1.1: (a) An electrical network, (b) Thevenin equivalent circuit as seen from AB .

To determine VTh for a network, we simply nd the open-circuit voltage Voc across AB , i.e., the voltage VA VB when nothing is connected on the right side in Fig. 1.1 (a); then, we have VTh = Voc . To nd RTh , we can use two methods: (a) Deactivating the independent sources in the given network is equivalent to deactivating VTh in its Thevenin equivalent circuit (see Fig. 1.2 (a)), leaving only RTh . Therefore, RTh is simply the resistance seen from AB in the original network (Fig. 1.1 (a)) with all independent sources deactivated. Note that deactivating a voltage source amounts to making Vs = 0 V , i.e., replacing it with a short circuit. Similarly, deactivating a current source, i.e., making Is = 0 V , is equivalent to replacing it with an open circuit. Note also that, in the above procedure, the dependent sources are to be left untouched, i.e., they should not be deactivated. Once the independent sources in the network are deactivated, the resistance seen from the port of interest can often be found by inspection. In some cases, we may need to connect a test voltage source V0 , nd the current I0 through it (see Fig. 1.2 (b)), and 1.1

1.2

A

Circuit (resistors, voltage sources, current sources, CCVS, CCCS, VCVS, VCCS)

A I0 V0 B

(a)

A RT h

A RT h RT h I0 B B

(b)

V0

Figure 1.2: (a) Deactivating independent sources and its eect on the Thevenin equivalent circuit, (b) Computation of RTh .

then use RTh = V0 /I0 . Alternatively, we could connect a test current source I0 , nd the voltage V0 across it, and use RTh = V0 /I0 . (b) If the port AB is shorted, then the short-circuit current Isc is VTh /RTh (see Figs. 1.3 (a) and (b)). This gives us an alternate method to nd RTh : Obtain the open-circuit voltage Voc (which is equal to VTh , as seen earlier) and the short-circuit current Isc . Then, RTh = VTh /Isc .

A

Circuit (resistors, voltage sources, current sources, CCVS, CCCS, VCVS, VCCS)

A RT h Isc VT h Isc

B

(a) (b)

Figure 1.3: Short-circuit current Isc (a) for the original network, (b) for the Thevenin equivalent.

Source transformation: Consider the circuit shown in Fig. 1.4 (a). The Thevenin voltage for this circuit is, VTh = Voc = Is Rp . To nd RTh , we deactivate the current source (i.e., replace it with an open circuit) and view the circuit from AB to get RTh = Rp . In other words, the circuit in Fig. 1.4 (a) is equivalent to that in Fig. 1.4 (b), which is already in the Thevenin form, if Rs = Rp and Vs = Is Rp .

A Rs Is Rp B

(a) (b)

A Vs B

The source transformation described above can be used to convert a Thevenin equivalent circuit into a Norton equivalent circuit, which is of the form shown in Fig. 1.4 (a).

1.3

Superposition: The system of equations that applies to a circuit with resistors, dc independent sources, and dependent sources is a linear system, and therefore we can use the principle of superposition to analyse the circuit by performing the following steps. (a) Denote the independent sources in the circuit by S1 , S2 , , SN . (b) For each source Si , compute the variables of interest (currents or voltages), say y1 , y2 , , yn , with all other independent sources deactivated. Denote the values of the (i) (i) (i) variables by, y1 , y2 , , yn .

N

net yj

=

i=1

yj .

(i)

Maximum power transfer: Consider the power absorbed by RL in the circuit shown in Fig. 1.5 (a) where VTh , RTh represent the Thevenin equivalent of a general network containing dc voltage or current sources, dependent sources, and resistors. The power absorbed by RL is PL = i2 L RL = VTh RTh + RL

2

RL .

(1.1)

By dierentiating PL with respect to RL and equating the derivative to zero, it can be shown that PL is maximum when RL = RTh (see Fig. 1.5 (b)).

PL

max PL

RT h

A iL

VT h

RL

B RL

(a)

RL = RT h

(b)

1.2

Examples

1. For the circuit shown in Fig. 1.6 (a), nd the currents i1 and i2 using source transformation. Converting the circuit with Is and R2 into an equivalent form (voltage source in series with a resistance), we get the circuit shown in Fig. 1.6 (b). The computation of i1 now 5V 6V = 0.143 A. Coming back to the original circuit becomes trivial, viz., i1 = 7

1.4

5 R1 Vs 5 V Is B

(a) (b)

i1 A i2 3A R2 2 5 i1 A R1 Vs 5V B 6V 2

Figure 1.6: (a) Circuit for Example 1, (b) Equivalent circuit after source transformation.

(Fig. 1.6 (a)), we get i2 = i1 + Is = 2.857 A. Note that the source Is is delivering power while Vs is absorbing power. The reader is encouraged to verify power balance (i.e., the total power absorbed is equal to the total power delivered). SEQUEL le: ee101 network 1.sqproj 2. For the circuit shown in Fig. 1.6 (a), nd the current i2 by superposition.

5 R1 Vs 5V i2 R2 2 5 R1 Is 3A i2 R2 2

(a)

(b)

Figure 1.7: Circuit of Fig. 1.6 (a): (a) with Vs active and Is deactivated, (b) with Is active and Vs deactivated.

Since there are two independent sources (Vs and Is ) in the circuit, we consider two cases: Vs = 0.714 A (see Fig. 1.7 (a)). R1 + R2 (b) Is active, Vs deactivated: In this case, by current division, we get, R1 (2) i 2 = Is = 2.143 A (see Fig. 1.7 (b)). R1 + R2 (a) Vs active, Is deactivated: In this case, i2 =

(1)

Adding the individual contributions, we get, i2 = i2 + i2 = 2.857 A. 3. For the circuit shown in Fig. 1.8, R1 = 4 , R2 = 2.5 , R3 = 1 , R4 = 4 , Vs1 = 5 V , Vs2 = 2 V , Is = 5 A. Find the current iR3 using superposition. How will iR3 change if the source values are changed to Vs1 = 30 V , Vs2 = 20 V , Is = 15 A. We have the following three cases to consider, corresponding to the three independent sources, Vs1 , Vs2 , Is . (a) Only Vs1 active (Fig. 1.9 (a)): iR3 =

(2) (1)

(1)

(2)

Vs1 = 0.67 A. R1 + R2 + R3

A R2 C R4 Vs 2 Vs 1 D

1.5

R1 B

Is R3 iR3

(c) Only Is active (Fig. 1.9 (c)): iR3 = Is between two resistors in parallel).

A R2 C R4 A R2

(3)

R4 Vs 2

R2

R4

R1 B

Vs 1 R3 iR3 D

(a)

R1 B

R3 iR3 D

(b)

R1 B

Is R3 iR3 D

(c)

Figure 1.9: Circuit of Fig. 1.8: (a) only Vs1 active, (b) only Vs2 active, (c) only Is active.

(1) (2) (3)

The net value of iR3 is therefore iR3 = iR3 + iR3 + iR3 = 2 A. When the source values are changed to Vs1 = 30 V , Vs2 = 20 V , Is = 15 A, we can nd the new iR3 by using linearity of the circuit. Since Vs1 , Vs2 , Is have been scaled (with respect to their earlier values) by factors of 6, 10, 3, respectively, we have (3) (2) (1) iR3 = 6 iR3 + 10 iR3 + 3 iR3 = 4 A. SEQUEL le: ee101 network 2.sqproj 4. In the R-2R ladder network shown in Fig. 1.10 (a), nd Vo using superposition.

A0 A0 2R 2R Vs 0 R A1 2R Vs 1

(a)

R 2R

A1 2R

A2 2R

A3 2R Vo

A2 2R Vs 2

A3 Vo 2R Vs 3 2R Vs 0

Vs 1

(b)

Vs 2

Vs 3

Figure 1.10: (a) Circuit for Example 4, (b) Circuit redrawn with sources shown explicitly.

1.6

M. B. Patil, IIT Bombay We take up each of the voltage sources separately and then add their contributions: (a) Vs3 only (Fig. 1.11 (a)): Using Thevenins theorem, the circuit can be simplied to (1) that shown in Fig. 1.11 (b), and we get Vo = Vs3 /2.

A0 2R 2R Vs 3 R A1 2R R A2 2R R A3 2R 2R Vs 3 A3 2R Vo

(a)

(b)

Figure 1.11: Circuit of Fig. 1.10 (a) with only Vs3 active.

A2 2R 2R Vs 2 Vs 2 / 2 R A3 2R A2 R R A3 2R Vo

(a)

(b)

Figure 1.12: Circuit of Fig. 1.10 (a) with only Vs2 active.

A1 2R 2R Vs 1 Vs 1 / 2 Vs 1 / 4 R A2 2R R A3 2R A1 R R A2 2R R A3 2R A2 R R A3 2R Vo

(a)

(b)

(c)

Figure 1.13: Circuit of Fig. 1.10 (a) with only Vs1 active.

(b) Vs2 only: Using Thevenins theorem, this case can be simplied to the circuit shown in Fig. 1.12 (a) and can be further simplied to that shown in Fig. 1.12 (b), giving (2) Vo = Vs2 /4. (c) Vs1 only: Using Thevenins theorem, this case can be progressively simplied to the (3) circuits shown in Figs. 1.13 (a), (b), (c), giving Vo = Vs1 /8. (d) Vs0 only: Using the above procedure, the reader can show that Vo = Vs0 /16.

(4)

Some useful techniques The net value of Vo is therefore Vo = 1 20 Vs0 + 21 Vs1 + 22 Vs2 + 23 Vs3 . 16

1.7

SEQUEL le: ee101 network 3.sqproj 5. For the circuit shown in Fig. 1.14 R1 = 4 , R2 = 2 , R3 = 4 , Is = 3 A, Vs1 = 4 V . Find the current iR2 by superposition.

2 vx 3 Vs 2 A iR2 R 2 R1 B Is R3 vx Vs 1 D C

There are two independent sources in the circuit, and we will consider each of them separately. Note that the dependent source must be retained in each circuit and not deactivated. (a) Is only (Fig. 1.15 (a)): This case is simplied considerably with source transformation (see Fig. 1.15 (b)). Writing KVL for the simplied circuit, we obtain,

2 vx 3 Vs 2 A iR2 R 2 R1 B

(a)

2 vx 3 R1 C i 12 V Vs 2 A iR2 R2 C A i R1 D vx

(b)

2 vx 3 Vs 2 iR2 R 2 Vs 1 D vx

(c)

Is R3 D vx

R3 B

R3 B

Figure 1.15: (a) Circuit of Fig. 1.14 with only Is active, (b) Circuit of (a) after source transformation, (c) Circuit of Fig. 1.14 with only Vs1 active.

(1)

(1.2)

1.8 (b) Vs1 only (Fig. 1.15 (c)): Writing KVL for this circuit, we get 2 Vs1 + (R1 + R3 ) i (R3 i) = 0 , 3 which gives, i = 0.75 A, and iR2 = 1 A. The net value of iR2 is therefore 2 A. SEQUEL le: ee101 network 4.sqproj

(2)

(1.3)

6. Simplify the circuit shown in Fig. 1.16 (a) using Thevenins theorem and nd the current iL .

3k R1 Vs 5V R3 2k 1k R2 A iL RL 0.5 k B

(a) (b)

3k R1 Vs 5V R3 2k

1k R2 Voc

A RT h VT h B

(c)

A iL RL 0.5 k B

Figure 1.16: (a) Circuit for Example 6, (b) Computation of Voc , (c) Simplied circuit diagram.

To obtain the Thevenin equivalent circuit as seen from AB (see Fig. 1.16 (a)), we deactivate (short) the voltage source and obtain RTh = (R1 R3 ) + R2 = 2.2 k. VTh = Voc R3 is obtained from Fig. 1.16 (b) as Voc = Vs = 2 V . The simplied circuit is shown R1 + R3 VTh in Fig. 1.16 (c), giving iL = = 0.74 mA. RTh + RL SEQUEL le: ee101 network 5.sqproj 7. For the circuit shown in Fig. 1.17 (a), nd the Thevenins equivalent circuit as seen from AB .

R1 i 20 5i Vs 20 V R2 2 R3 8 B

(a) (b)

R1 A i 20 Vs 20 V

R2 6i 2 5i R3 8

A Voc B

Figure 1.17: (a) Circuit for Example 7, (b) Computation of VTh = Voc .

The open-circuit voltage Voc is found from Fig. 1.17 (b), by writing KVL: Vs = R1 i + 6 i (R2 + R3 ) , (1.4)

Some useful techniques giving i = 0.25 A and VTh = Voc = 6 i R3 = 12 V . RTh can be obtained in two ways: (a) We nd the short-circuit current Isc as shown in Fig. 1.18 (a). KVL gives Vs = R1 i + 6 i R2 i = 5 A, 8

1.9

(1.5)

R1 i 20 Vs 20 V R2 6i 2 5i

(a)

R1 A R3 8 Isc i 20

R2 6i 2 5i R3 8

I0

A V0 B

B

(b)

Figure 1.18: Computation of RTh for the circuit of Fig. 1.17: (a) by computing the short-circuit current, (b) by using a test source.

(b) We deactivate the independent source (see Fig. 1.18 (b)) and use a test source V0 to obtain RTh . KVL gives V0 = (6 i + I0 ) R3 = (i R1 + 6 i R2 ) . Eliminating i from Eq. 1.6 gives RTh = V0 /I0 = 3.2 . How do we check our results with circuit simulation? Consider the circuit in Fig. 1.19 in which the Thevenin equivalent of a network has been represented by VTh and RTh . KVL gives Vs = VTh Is RTh . (1.7) If Vs is plotted against Is , the y -intercept gives VTh , and the x-intercept gives Isc = VTh /RTh . These values can be checked against our computed results for the network.

RT h VT h Is Vs

(1.6)

1.10

8. Find the Thevenin equivalent of the network shown in Fig. 1.20 (a), as seen from AB .

v1 R2 1 R1 4 C R3 1 I0 2 A v1 /2 B

(a) (b)

v1 A R1 4 R2 1

R3 1 I0 2 A v1 /2

A Isc

(a) Computation of Voc : Taking node B as the reference node (i.e., VB as 0 V ), KCL at node C gives, 1 R2 VC I0 VC = 0 , (1.8) R1 + R2 2 R1 + R2 v1 which gives VC = 20 V . Voc is then given by Voc = VA = VC + R3 = 22 V . 2 (b) Computation of Isc : Again, taking VB = 0 V , KCL at node C gives, VC VC I0 + = 0, R1 + R2 R3 giving VC = 1.67 V . The current Isc is then given by KCL at node A: Isc = VC v1 = 1.83 A . + R3 2 (1.10) (1.9)

RTh is therefore equal to Voc /Isc = 12 . SEQUEL le: ee101 network 7.sqproj 9. For the circuit shown in Fig. 1.21 (a), R1 = 20 , R2 = 40 , RL = 4 , Vs = 50 V . Find iL using Thevenins theorem. (a) Computation of Voc : Writing KVL for the circuit in Fig. 1.21 (b), we get R2 i1 + (R1 + R2 ) i1 + Vs = 0 , 4 (1.11)

giving i1 = 1 A, and Voc = R2 i1 + Vs = 10 V . (b) Computation of Isc : The short-circuit current can be found from Fig. 1.21 (c). In vx 1 Vs 5 5 this case, we have vx = Vs , i1 = = A, i2 = = A, and 4 R1 8 R2 4 5 Is = i1 i2 = A. 8

A iL R1 R2 RL vx /4 B

(a)

1.11

A i1 vx R1 Voc vx /4 B

(b)

A i1 R2 vx R1 Isc Vs vx /4 B

(c) (d)

A i2 R2 vx RT h RL VT h B iL

Vs

Vs

Figure 1.21: (a) Circuit for Example 9, (b) Computation of Voc , (c) Computation of Isc , (d) Computation of iL .

From the above values, we get RTh = Voc /Isc = 16 . The original circuit in Fig. 1.21 (a) VTh = 0.5 A. is thus equivalent to that shown in Fig. 1.21 (d), giving iL = RTh + RL SEQUEL le: ee101 network 7a.sqproj

1.3

Exercise Set:

1. In the circuit shown in Fig. 1.22 (a), nd the current i by superposition. Verify your result with simulation. SEQUEL le: ee101 network 8.sqproj

i1 3 12 V 1

(a)

R2 2 1A 2 i1 5A i2 1 R1 10

10 V

i 8

R3 8

16 i1

(b)

Figure 1.22: (a) Circuit for Exercises 1 and 2, (b) Circuit for Exercise 3.

2. In the circuit shown in Fig. 1.22 (a), nd the current i1 by source transformation. 3. In the circuit shown in Fig. 1.22 (b), nd the currents i1 and i2 by superposition. Verify your results with simulation. SEQUEL le: ee101 network 9.sqproj 4. For the circuit shown in Fig. 1.23 (a), (a) Find the value of RL for maximum power transfer.

max (b) Calculate PL , the maximum power absorbed by RL .

(c) Obtain a plot PL versus RL by simulation, and verify the answers you obtained for (a) and (b).

1.12

M. B. Patil, IIT Bombay (d) How will the above plot change if the voltage source is changed from 18 V to 12 V ? SEQUEL le: ee101 network 10.sqproj

R1 3k Vs 6k 18 V R2

(a)

(b)

Figure 1.23: (a) Circuit for Exercises 4. (b) Circuit for Exercise 5.

5. Using superposition, obtain a general expression for the current i (see Fig. 1.23 (b)) in terms of the source currents Is0 , Is1 , Is2 , Is3 . For each of the following combinations, compute i using your expression, and verify with simulation results. (a) Is1 = Is0 = 3 mA, others are zero. (b) Is3 = Is1 = 3 mA, others are zero. SEQUEL le: ee101 network 11.sqproj

- Circuits+Lab+Manual Lab2Uploaded byVithursan Thangarasa
- Circuit Theory - Solved Assignments - Semester Summer 2007Uploaded byMuhammad Umair
- EEE 209 Presentation 3 (Circuits Cont)Uploaded byMert Yılmaz
- Thevenin NortonUploaded byaakashtrivedi
- May 2015Uploaded byΘωμαςΣτεφανιδης
- VLSI_CHP14Uploaded byfeki2607
- Nd Lab ManualUploaded bySurya Narayan Sahu
- Signal_IntegrityUploaded bydhfsi7496
- Battery TestingUploaded byHamilton Qrn
- EEE1-lecture02Uploaded byJosh King
- Magnitic theroyUploaded byaminmomin
- Direct Digital-Frequency Synthesis by Analog InterpolationUploaded byYermakov Vadim Ivanovich
- Usm 36 Operation Manuals EspanolUploaded byHUGO COLORADO
- تكنولوجيا الإنتاج الوصف التفصيليUploaded byibraheem
- Chap9 Network TheoremsUploaded bytolera
- memristerUploaded byShashi Nawab
- final_04Uploaded byTaha Etem
- TEA1532PUploaded byFreddy
- Max 17020Uploaded byAndrej Povh
- P-97-17.psUploaded byPak
- Sanyo Ac5 g1Uploaded byRicky Baquir
- Abbott - Keeping the Energy Debate Clean How Do We Supply the World's Energy Needs - 2010Uploaded byAshutosh Kumar
- Chapter 25 - DC Load Flow AnalysisUploaded byohmouz
- UP2 HW Ch 28 S Direct Current CircuitsUploaded bykui
- Connecting Solar Cells Through SimulinkUploaded bypraveshkafle
- TRB Polytechnic Syllabus Electronics and InsrumentationUploaded byIndhu
- 00682760Uploaded byAmmineni Jaswanth
- su2015Uploaded bysanjeev
- Pspice TutorialUploaded byalebex
- Impatt LargeUploaded byTonoy Dhar

- Matlab Robust Control ToolboxUploaded byRishi Kant Sharma
- Power Electronics.pdfUploaded byAjju K Ajju
- Tutorial Singlephase TransformerUploaded byRishi Kant Sharma
- Assignment Three Phase TransformerUploaded byRishi Kant Sharma
- Objective Type Electrical Engineering Paper IUploaded byAjay Gahlot
- Electrical Measurements for GATE & Competitive Exams !Uploaded bysatishfactory
- Tutorial EMEC-I Dc MachinesUploaded byRishi Kant Sharma
- Sail MT 2015 electrical engg samplePaperUploaded byRishi Kant Sharma
- State regulatorUploaded byRishi Kant Sharma
- Chapter 1 Circuit Concepts and Network Specification TechniquesUploaded byKarthikeyan Ramalingam
- Sensors and transducersUploaded byRishi Kant Sharma
- Super Capacitors modelling in matlabUploaded byRishi Kant Sharma
- ENGG SERVICES GENERAL ABILITY QUESTION PAPER FOR YEAR 2013Uploaded byRishi Kant Sharma
- Types of Control ValvesUploaded byRishi Kant Sharma
- AE10_solUploaded bySriram Chandu
- Gate ControlUploaded byAbhishek Gupta
- CONV_E&T_IIUploaded bysaurabhjain2009
- Current AffairsUploaded byRishi Kant Sharma
- network theormsUploaded byRishi Kant Sharma
- ENGG SERVISES ELECTRICAL ENGG OBJECTIVE PAPER II 2012Uploaded byRishi Kant Sharma
- UTTAR PRADESH UP PCS UPPSC Prelims Exam 2009 General Studies Solved PaperUploaded byRishi Kant Sharma
- Instument AmplifierUploaded byRishi Kant Sharma
- UPPSC Solved Paper 26 June 2011 Www.upscportalUploaded byPawan Kumar
- Integration FormulasUploaded byJoyen Sanjana
- Ies 2012 General Ability Set cUploaded byRishi Kant Sharma
- GATE Electrical Engineering Sample Paper 2010Uploaded byRishi Kant Sharma
- OBJ_E&T_IIUploaded bycreovation
- OBJ_E&T_IUploaded byROHITCHOURASIYA

- T2-2 T.pdfUploaded byManav Nair
- Trunnion AssemblyUploaded byvibishnan
- Physics Lab 4Uploaded byDesiree Mae Ibon
- Tesla_12Uploaded byAhmad Kelixo De Ramirez
- SimXpert R3.2 Explicit Workspace GuideUploaded bypaulkastle
- 83347 16PP Product GuideUploaded byP.p. Arul Ilancheeran
- integrated scienceUploaded bySheila Padaoan Garcia
- Chapter 11 Balanced three phase circuitsUploaded byاغريسة
- 1.5 Analysing Interference Of Waves.pptUploaded byCik Rokiah Ghani
- chap9Uploaded bysubhajit
- I Am Trying to Design a Bus Brace for a 3 Phase Busbar SyatemUploaded bySanjeewa Hemaratne
- 5_DrivenHarmonicOscillatorUploaded byLiana Ritter
- Electrostatic Particle-InCell Simulation Techinique for Quasineutral PlasmaUploaded byjorge
- Protective Schemes for Transformer AndUploaded bysriknthk8
- The Johsnon EngineUploaded byschnellarbeiter
- Efficiency trends in electric machines and drivesUploaded bysadeq03
- F5C1(tutorial1.7)Uploaded byChewLee Tan
- 220767_1Uploaded byNilay Thakkar
- Fluid Mechanics.pdfUploaded bySanjan KS
- C.1Uploaded byRaymondSanchez
- MagnetoquasistaticsUploaded byratansrikanth
- 04 AtwoodUploaded byunregistered000
- brakes-clutches.pdfUploaded byMarvin
- ContactorsUploaded byLaurentiu Catalin
- Impact of jetUploaded byShafiz
- 4Uploaded bymadhukuvce
- Glossary of Physics TermsUploaded byDjoanna Joy Carandang
- Response of MDOF to Ground Excitation With EXAMPLES_2012_handoutUploaded byAfham Ahmad
- 27190504 Power Transformers and ReactorsUploaded byroyclhor
- Schneider Electrical+Installation Guide 2010Uploaded byali_naghib