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1.1 Introduction
The VHSIC Hardware Description Language is an industry standard language used to describe hardware from the abstract to the concrete level. VHDL resulted from work done in the '70s and early '80s by the U.S. Department of Defense. VHDL usage has risen rapidly since its inception and Is used by literally tens of thousands of engineers around the globe to create sophisticated electronic products, This chapter will start the process of easing the reader into the complexities of VHDL. VHDL is a powerful language with numerous language constructs that are capable of describing, very complex behavior. Learning all the features of VHDL is not a simple task. In 1986, VHDL was proposed as an IEEEstandard. It went through a number of revisions and changes until it was adopted as the IEEE 1076 standard in December 1987, Then VHDL 1076-1993 and the latest VHDL 1076-2002. All the examples have been described in IEEE 1076 VHDL.

1.2 Levels of representation

There are two levels of representation, which are supported by VHDL: 1-Behavioral level: this describes system in terms of what it does (or how it behaves). 2-Structural level: this describes a system as a collection of gates and components Figure 1.1 shows the two levels of representation.

Figure 1.1 Levels of representation

1.3 Structure of a VHDL file

To create a VHDL file the following steps are necessary: 1.3.1 Design Entity Figure 1.2 shows that Entity Declaration is considered as the interface to the outside world, which defines the input and output signals as well as the Architecture contains the description of the entity and is composed of interconnected entities, processes and components.

The code of the entity declaration Syntax: Entity NAME_OF _ENTITY is Port (signal names: mode type; signal names: mode type; . . signal names: mode type); End NAME_OF_ENTITY; Mode: is one of the reserved words to indicate the signal direction (in - out - buffer - inout). Type: a built-in or user-defined signal type. ( bit, bit_vector, Boolean, character, std_logic, integer ... ) The following example explain the declaration of a D flip-flop with set and reset inputs

Entity D_flip is Port (D, CLK, S, R : in std_logic; Q, Qnot : out std_logic); End D_flip; 1.3.2 Architecture Body An entity or circuit can be specified in a variety of ways, such as behavioral, structural, or a combination of both. The architecture body looks as follows: Architecture architecture_name of NAME_OF_ENTITY is -- Declarations -- Components declarations -- Signal declarations -- Constant declarations -- Type declarations . . Begin -- Statements . . End architecture_name; 1.3.3 Library & Packages A library can be considered as a place where the compiler stores information about a design project, and a VHDL package is a file or module that contains declarations of commonly used objects, data type, component declarations, signal, procedures and functions. To specify the library and package, use the "library" and the "Use" keywords. For example to include the std_logic_1164 package that exists in the library IEEE library IEEE; Use IEEE.std_logic_1164.all; The .all extension indicates to use the entire ieee.std_logic_1164 package.