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TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS

SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

D Very Low Power Consumption D Typical Supply Current . . . 200 µA
(Per Amplifier)

D Wide Common-Mode and Differential D D
Voltage Ranges Low Input Bias and Offset Currents Common-Mode Input Voltage Range Includes VCC+

D D D D D

Output Short-Circuit Protection High Input Impedance . . . JFET-Input Stage Internal Frequency Compensation Latch-Up-Free Operation High Slew Rate . . . 3.5 V/µs Typ

TL061, TL061A . . . D, P, OR PS PACKAGE TL061B . . . P PACKAGE (TOP VIEW)

TL062 . . . D, JG, P, PS, OR PW PACKAGE TL062A . . . D, P, OR PS PACKAGE TL062B . . . D OR P PACKAGE (TOP VIEW)

OFFSET N1 IN− IN+ VCC−

1 2 3 4

8 7 6 5

NC VCC+ OUT OFFSET N2

1OUT 1IN− 1IN+ VCC−

1 2 3 4

8 7 6 5

VCC+ 2OUT 2IN− 2IN+

NC 1OUT NC VCC+ NC

1OUT 1IN− 1IN+ VCC+ 2IN+ 2IN− 2OUT

1 2 3 4 5 6 7

14 13 12 11 10 9 8

4OUT 4IN− 4IN+ VCC− 3IN+ 3IN− 3OUT

NC 1IN− NC 1IN+ NC

4 5 6 7 8

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

NC 2OUT NC 2IN− NC

1IN+ NC VCC+ NC 2IN+

4 5 6 7 8

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

1IN− 1OUT NC 4OUT 4IN− 4IN+ NC VCC− NC 3IN+
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

TL064 . . . D, J, N, NS, PW, OR W PACKAGE TL064A, TL064B . . . D OR N PACKAGE (TOP VIEW)

TL062 . . . FK PACKAGE (TOP VIEW)

TL064 . . . FK PACKAGE (TOP VIEW)

description/ordering information
The JFET-input operational amplifiers of the TL06_ series are designed as low-power versions of the TL08_ series amplifiers. They feature high input impedance, wide bandwidth, high slew rate, and low input offset and input bias currents. The TL06_ series features the same terminal assignments as the TL07_ and TL08_ series. Each of these JFET-input operational amplifiers incorporates well-matched, high-voltage JFET and bipolar transistors in an integrated circuit. The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from −40°C to 85°C, and the M-suffix devices are characterized for operation over the full military temperature range of −55°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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2IN− 2OUT NC 3OUT 3IN−

NC VCC− NC 2IN+ NC

NC − No internal connection

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SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
description/ordering information (continued)
ORDERING INFORMATION
TA VIOMAX AT 25°C PDIP (P) PDIP (N) PACKAGE† Tube of 50 Tube of 25 Tube of 75 Reel of 2500 Tube of 75 SOIC (D) 15 mV Reel of 2500 Tube of 50 Reel of 2500 SOP (PS) SOP (NS) Reel of 2000 Reel of 2000 Tube of 150 TSSOP (PW) Reel of 2000 Tube of 90 Reel of 2000 0°C to 70°C PDIP (P) PDIP (N) Tube of 50 Tube of 25 Tube of 75 Reel of 2500 6 mV Tube of 75 SOIC (D) Reel of 2500 Tube of 50 Reel of 2500 SOP (PS) PDIP (P) PDIP (N) 3 mV SOIC (D) Reel of 2000 Tube of 50 Tube of 25 Tube of 75 Reel of 2500 Tube of 50 Reel of 2500 ORDERABLE PART NUMBER TL061CP TL062CP TL064CN TL061CD TL061CDR TL062CD TL062CDR TL064CD TL064CDR TL061CPSR TL062CPSR TL064CNSR TL062CPW TL062CPWR TL064CPW TL064CPWR TL061ACP TL062ACP TL064ACN TL061ACD TL061ACDR TL062ACD TL062ACDR TL064ACD TL064ACDR TL061ACPSR TL062ACPSR TL061BCP TL062BCP TL064BCN TL062BCD TL062BCDR TL064BCD TL064BCDR 062BC TL064BC TL064AC T061A T062A TL061BCP TL062BCP TL064BCN 062AC 061AC T062 T064 TL061ACP TL062ACP TL064ACN TL064C T061 T062 TL064 TL062C TL061C TOP-SIDE MARKING TL061CP TL062CP TL064CN

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

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TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

description/ordering information (continued)
ORDERING INFORMATION (continued)
TA VIOMAX AT 25°C PDIP (P) PDIP (N) PACKAGE† Tube of 50 Tube of 25 Tube of 75 Reel of 2000 −40°C to 85°C 6 mV SOIC (D) Tube of 75 Reel of 2000 Tube of 50 Reel of 2500 TSSOP (PW) CDIP (JG) 6 mV −55 C 125°C −55°C to 125 C 9 mV LCCC (FK) CDIP (J) CFP (W) LCCC (FK) Reel of 2000 Tube of 50 Tube of 55 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER TL061IP TL062IP TL064IN TL061ID TL061IDR TL062ID TL062IDR TL064ID TL064IDR TL062IPWR TL062MJG TL062MFK TL064MJ TL064MW TL064MFK TL064I TL062I TL062MJG TL062MFK TL064MJ TL064MW TL062I TL061I TOP-SIDE MARKING TL061IP TL062IP TL064IN

TL064MFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

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SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
symbol (each amplifier)
IN+ IN− + − OUT

OFFSET N1

OFFSET N2

Offset Null/Compensation TL061 Only

schematic (each amplifier)
VCC+

IN+ IN− 50 Ω

100 Ω

C1

OFFSET N1

OFFSET N2

OUT

VCC−

TL061 Only C1 = 10 pF on TL061, TL062, and TL064 Component values shown are nominal.

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TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
TL06_C TL06_AC TL06_BC Supply voltage, VCC+ (see Note 1) Supply voltage, VCC− (see Note 1) Differential input voltage, VID (see Note 2) Input voltage, VI (see Notes 1 and 3) Duration of output short circuit (see Note 4) D (8-pin) package D (14-pin) package N package NS package Package thermal impedance, θJA (see Notes 5 and 6) P package PS package PW (8-pin) package PW (14-pin) package FK package Package thermal impedance, θJC (see Notes 7 and 8) J package JG package W package Operating virtual junction temperature, TJ Case temperature for 60 seconds Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds Lead temperature 1,6 mm (1/6 inch) from case for 10 seconds FK package J, JG, U, or W package D, N, NS, P, PS, or PW package 260 260 150 150 18 −18 ±30 ±15 Unlimited 97 86 80 76 85 95 149 113 TL06_I 18 −18 ±30 ±15 Unlimited 97 86 80 76 85 95 149 113 5.61 15.05 14.5 14.65 150 260 300 °C °C °C °C °C/W °C/W C/W TL06_M 18 −18 ±30 ±15 Unlimited UNIT V V V V

Storage temperature range, Tstg −65 to 150 −65 to 150 −65 to 150 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values except differential voltages are with respect to the midpoint between VCC+ and VCC−. 2. Differential voltages are at IN+ with respect to IN−. 3. The magnitude of the input voltage should never exceed the magnitude of the supply voltage or 15 V, whichever is less. 4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded. 5. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 6. The package thermal impedance is calculated in accordance with JESD 51-7. 7. Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) − TC)/θJC. Operating at the absolute maximum TJ of 150°C can affect reliability. 8. The package thermal impedance is calculated in accordance with MIL-STD-883.

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SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
electrical characteristics, VCC± = ±15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS† MIN VIO αV
IO

TL061C TL062C TL064C TYP 3 MAX 15 20 10 5 30 200 5 400 10 ±11 −12 to 15 ±13.5 6 1 12 10 70 86 80 ±11 ±10 ±10 4 4 MIN

TL061AC TL062AC TL064AC TYP 3 MAX 6 7.5 10 5 30 100 3 200 7 −12 to 15 ±13.5 6

UNIT

Input offset voltage Temperature coefficient of input offset voltage Input offset current Input bias current‡ Common-mode input voltage range Maximum peak output voltage swing Large-signal differential voltage amplification Unity-gain bandwidth Input resistance Common-mode rejection ratio Supply-voltage rejection ratio (∆VCC±/∆VIO) Total power dissipation (each amplifier) Supply current (each amplifier)

VO = 0, RS = 50 Ω

TA = 25°C TA = Full range

mV µV/°C pA nA pA nA V

VO = 0, RS = 50 Ω, TA = Full range VO = 0 VO = 0 TA = 25°C TA = Full range TA = 25°C TA = Full range

IIO IIB

VICR

TA = 25°C RL = 10 kΩ, RL ≥ 10 kΩ, VO = ± 10 V, RL ≥ 10 kΩ RL = 10 kΩ, TA = 25°C TA = Full range TA = 25°C TA = Full range TA = 25°C

VOM AVD B1 ri CMRR

±10 ±10 3 3

V V/mV

TA = 25°C VIC = VICRmin, VO = 0, RS = 50 Ω, TA = 25°C VCC = ± 9 V to ± 15 V, VO = 0, RS = 50 Ω Ω, TA = 25°C VO = 0, TA = 25°C, No load VO = 0, No load TA = 25°C,

1 12 10 86

MHz Ω dB

kSVR PD ICC

70

95

80

95

dB

6 200

7.5 250

6 200

7.5 250

mW µA

VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB † All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full range for TA is 0°C to 70°C for TL06_C, TL06_AC, and TL06_BC and −40°C to 85°C for TL06_I. ‡ Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 15. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.

6

POST OFFICE BOX 655303

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TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

electrical characteristics, VCC± = ±15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS† MIN VIO αV Input offset voltage Temperature coefficient of input offset voltage Input offset current Input bias current‡ Common-mode input voltage range Maximum peak output voltage swing Large-signal differential voltage amplification Unity-gain bandwidth Input resistance Common-mode rejection ratio Supply-voltage rejection ratio (∆VCC±/∆VIO) Total power dissipation (each amplifier) Supply current (each amplifier) VO = 0, RS = 50 Ω TA = 25°C TA = Full range TL061BC TL062BC TL064BC TYP 2 MAX 3 5 10 5 30 −12 to 15 ±13.5 6 1 1012 80 86 80 100 3 200 7 ±11 TA = 25°C TA = Full range TA = 25°C TA = Full range ±10 ±10 4 4 ±11 ±10 ±10 4 4 1 1012 86 6 V/mV MHz Ω dB −12 to 15 ±13.5 30 10 5 100 10 200 20 MIN TL061I TL062I TL064I TYP 3 MAX 6 9 mV µV/°C pA nA pA nA V UNIT

IO

VO = 0, RS = 50 Ω, TA = Full range VO = 0 VO = 0 TA = 25°C RL = 10 kΩ, RL ≥ 10 kΩ, VO = ± 10 V, RL ≥ 10 kΩ RL = 10 kΩ, TA = 25°C TA = Full range TA = 25°C TA = Full range

IIO IIB VICR

VOM AVD B1 ri CMRR

V

TA = 25°C TA = 25°C VIC = VICRmin, VO = 0, RS = 50 Ω, TA = 25°C VCC = ± 9 V to ± 15 V, VO = 0, RS = 50 Ω Ω, TA = 25°C VO = 0, TA = 25°C, No load VO = 0, No load TA = 25°C,

kSVR PD ICC

80

95

80

95

dB

6 200

7.5 250

6 200

7.5 250

mW µA

VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB † All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified. Full range for TA is 0°C to 70°C for TL06_C, TL06_AC, and TL06_BC and −40°C to 85°C for TL06_I. ‡ Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 15. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.

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SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
electrical characteristics, VCC± = ±15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS† MIN VIO αV
IO

TL061M TL062M TYP 3 MAX 6 9 10 5 100 20* 20 30 200 50* 50 ±11.5 −12 to 15 ±13.5 ±11.5 ±10 ±10 6 4 4 MIN

TL064M TYP 3 MAX 9 15 10 5 100 20* 20 30 200 50* 50 −12 to 15 ±13.5

UNIT

Input offset voltage Temperature coefficient of input offset voltage

VO = 0, RS = 50 Ω

TA = 25°C TA = −55°C to 125°C

mV µV/°C pA nA pA nA

VO = 0, RS = 50 Ω, TA = −55°C to 125°C VO = 0 TA = 25°C TA = −55°C TA = 125°C TA = 25°C

IIO

Input offset current

IIB

Input bias current‡

VO = 0

TA = −55°C TA = 125°C

VICR

Common-mode input voltage range Maximum peak output voltage swing Large-signal differential

TA = 25°C RL = 10 kΩ, RL ≥ 10 kΩ, VO = ±10 V, RL ≥ 10 kΩ RL = 10 kΩ, TA = 25°C TA = −55°C to 125°C TA = 25°C TA = −55°C to 125°C TA = 25°C

V

VOM

±10 ±10 4 4

V

6 V/mV MHz

AVD B1 ri CMRR

voltage amplification Unity-gain bandwidth Input resistance Common-mode rejection ratio Supply-voltage rejection ratio (∆VCC±/∆VIO) Total power dissipation (each amplifier) Supply current (each amplifier)

TA = 25°C VIC = VICRmin, VO = 0, RS = 50 Ω, TA = 25°C VCC = ±9 V to ±15 V, VO = 0, RS = 50 Ω, TA = 25°C VO = 0, No load VO = 0, No load TA = 25°C, TA = 25°C,

1012 80 86 80

1012 86

Ω dB

kSVR PD ICC

80

95

80

95

dB

6 200

7.5 250

6 200

7.5 250

mW µA

VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB * This parameter is not production tested. † All characteristics are measured under open-loop conditions, with zero common-mode voltage, unless otherwise specified. ‡ Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 15. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.

operating characteristics, VCC± = ±15 V, TA = 25°C
PARAMETER SR tr Slew rate at unity gain (see Note 5) Rise time Overshoot factor Vn Equivalent input noise voltage NOTE 5: Slew rate at −55°C to 125°C is 0.7 V/µs min. TEST CONDITIONS VI = 10 V, RL = 10 kΩ, VI = 20 mV, CL = 100 pF, RS = 20 Ω, CL = 100 pF, See Figure 1 RL = 10 kΩ, See Figure 1 f = 1 kHz MIN 1.5 TYP 3.5 0.2 10% 42 MAX UNIT V/µs µs s nV/√Hz

8

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TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

PARAMETER MEASUREMENT INFORMATION

10 kΩ − OUT + CL = 100 pF RL = 2 kΩ VI VI

Figure 1. Unity-Gain Amplifier

Figure 2. Gain-of-10 Inverting Amplifier

IN−

TL061 IN+ N2 N1 100 kΩ +

OUT

1.5 kΩ VCC−

Figure 3. Input Offset-Voltage Null Circuit

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− OUT + RL CL = 100 pF 9

1 kΩ

SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
TYPICAL CHARACTERISTICS Table of Graphs
FIGURE Maximum peak output voltage vs Supply voltage Maximum peak output voltage vs Free-air temperature Maximum peak output voltage vs Load resistance Maximum peak output voltage vs Frequency Differential voltage amplification vs Free-air temperature Large-signal differential voltage amplification vs Frequency Phase shift vs Frequency Supply current vs Supply voltage Supply current vs Free-air temperature Total power dissipation vs Free-air temperature Common-mode rejection ratio vs Free-air temperature Normalized unity-gain bandwidth vs Free-air temperature Normalized slew rate vs Free-air temperature Normalized phase shift vs Free-air temperature Input bias current vs Free-air temperature Voltage-follower large-signal pulse response vs Time Output voltage vs Elapsed time Equivalent input noise voltage vs Frequency 4 5 6 7 8 9 9 10 11 12 13 14 14 14 15 16 17 18

10

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TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS†
MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE
±15 VOM − Maximum Peak Output Voltage − V RL = 10 kΩ TA = 25°C See Figure 2 VOM − Maximum Peak Output Voltage − V ±15

MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE

±12.5

±12.5

±10

±10

±7.5

±7.5

±5

±5

±2.5

0 0 2 4 6 8 10 12 14 16 |VCC±| − Supply Voltage − V

Figure 4
MAXIMUM PEAK OUTPUT VOLTAGE vs LOAD RESISTANCE
±15 VOM − Maximum Peak Output Voltage − V VOM − Maximum Peak Output Voltage − V VCC± = ±15 V TA = 25°C See Figure 2 ±15

VCC± = ±15 V

±12.5 ±10

±12.5

VCC± = ±12 V

±10

±7.5

±7.5 ±5

±5

VCC± = ±5 V

±2.5

±2.5

0 100 200 400 700 1 k 2k 4k 7 k 10 k RL − Load Resistance − Ω

0 1k 10 k 100 k f − Frequency − Hz 1M 10 M

Figure 6

Figure 7

† Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the various devices.

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ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ

ÁÁÁÁÁ ÁÁÁÁÁ

ÁÁ ÁÁ ÁÁ ÁÁ

ÁÁ ÁÁ ÁÁ ÁÁ

±2.5

0 −75

VCC± = ±15 V RL = 10 kΩ See Figure 2 −50 −25 0 25 50 75 100 125

TA − Free-Air Temperature − °C

Figure 5
MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUENCY
RL = 10 kΩ TA = 25°C See Figure 2

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SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
TYPICAL CHARACTERISTICS†
DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE
10 AVD − Differential Voltage Amplification − V/mV VCC± = ±15 V RL = 10 kΩ

7

4

2

1 −75

−50

−25 0 25 50 75 100 TA − Free-Air Temperature − °C

125

Figure 8
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY
100 VCC± = ±15 V Rext = 0 RL = 10 kΩ TA = 25°C Phase Shift (right scale)

AVD − Large-Signal Differential Voltage Amplification − V/mV

10

1

45°

0.1 AVD (left scale)

90°

0.01

135°

0.001 1 10 100 1k 10 k 100 k 1M f − Frequency − Hz

180° 10 M

Figure 9
† Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the various devices.

12

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Phase Shift

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS†
SUPPLY CURRENT vs SUPPLY VOLTAGE
250 TA = 25°C No Signal No Load I CC ± − Supply Current − µA ICC 200 250

SUPPLY CURRENT vs FREE-AIR TEMPERATURE

I CC ± − Supply Current − µA ICC

200

150

150

100

50

0 0 2 4 6 8 10 12 14 16 |VCC±| − Supply Voltage − V

Figure 10

TOTAL POWER DISSIPATION vs FREE-AIR TEMPERATURE
30 CMRR − Common-Mode Rejection Ratio − dB 87

P D − Total Power Dissipation − mW PD

25 VCC± = ±15 V No Signal No Load TL064

20

15 TL062 10 TL061

5

0 −75

−50

−25

0

25

50

75

100

125

TA − Free-Air Temperature − °C

Figure 12

† Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the various devices.

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ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Á Á ÁÁ ÁÁ
50 VCC± = ±15 V No Signal No Load −50 −25 0 −75 0 VCC± = ±15 V RL = 10 kΩ 86 85 84 83 82 81 −75 −50 −25 0

100

ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ

25

50

75

100

125

TA − Free-Air Temperature − °C

Figure 11
ALL EXCEPT TL06_C COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE

25

50

75

100

125

TA − Free-Air Temperature − °C

Figure 13

• DALLAS, TEXAS 75265

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SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
TYPICAL CHARACTERISTICS
NORMALIZED UNITY-GAIN BANDWIDTH, SLEW RATE, AND PHASE SHIFT vs FREE-AIR TEMPERATURE
Normalized Unity-Gain Bandwidth and Slew Rate 1.3 Unity-Gain Bandwidth (left scale) 1.03

1.2

1.02 Phase Shift (right scale) 1.01 Slew Rate (left scale) Normalized Phase Shift

1.1

1

1

0.9

0.99

0.8

VCC± = ±15 V RL = 10 kΩ f = B1 for Phase Shift −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C

0.98

0.7 −75

0.97 125

Figure 14
VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE vs TIME
6 Input 4 Input and Output Voltages − V

INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE
100 40

IIB − Input Bias Current − nA IIB

10 4

1 0.4

0.1

0.04 0.01 −50

14

ÁÁÁÁÁ
−25 0 25 50 75 100 TA − Free-Air Temperature − °C 125

VCC± = ±15 V

2

0 Output −2 VCC± = ±15 V RL = 10 kΩ CL = 100 pF TA = 25°C 0 2 4 6 t − Time − µs 8 10

ÁÁ ÁÁ

−4

−6

Figure 15

Figure 16

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• DALLAS, TEXAS 75265

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE vs ELAPSED TIME
28 V n − Equivalent Input Noise Voltage − nV/ Hz 24 VO − Output Voltage − mV 20 90% 16 12 8 4 10% 0 tr −4 0 0.2 0.4 0.6 0.8 1 t − Elapsed Time − µs 1.2 1.4 VCC± = ±15 V RL = 10 kΩ TA = 25°C 100 90 80 70 60 50 40 30 20 10 0 10 40 100 400 1 k 4 k 10 k f − Frequency − Hz 40 k 100 k

EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY

Overshoot

Figure 17

Figure 18

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ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ
VCC± = ±15 V RS = 20 Ω TA = 25°C 15

ÁÁ ÁÁ

SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
APPLICATION INFORMATION
Table of Application Diagrams
APPLICATION DIAGRAM Instrumentation amplifier 0.5-Hz square-wave oscillator High-Q notch filter Audio-distribution amplifier Low-level light detector preamplifier AC amplifier Microphone preamplifier with tone control Instrumentation amplifier IC preamplifier PART NUMBER TL064 TL061 TL061 TL064 TL061 TL061 TL061 TL062 TL062 FIGURE 19 20 21 22 23 24 25 26 27

VCC+ 10 kΩ 0.1% TL064 + VCC− VCC+ VCC− 100 kΩ − Input B + TL064 − VCC− 10 kΩ 0.1% 10 kΩ 0.1% RF = 100 kΩ 15 V − 3.3 kΩ Output Input TL061 CF = 3.3 µF + 1 kΩ R3 C2 −15 V 3.3 kΩ f+ 2p 1 RF CF 9.1 kΩ C1 − VCC+ − 10 kΩ 0.1% − 100 kΩ Input A 16

TL064 100 kΩ VCC+ 1 MΩ +

Output

TL064 + VCC−

100 kΩ

Figure 19. Instrumentation Amplifier
VCC+ TL061 R2 VCC− R1 = R2 = 2 × R3 = 1.5 MΩ C1 + C2 + C3 + 110 pF 2 1 + 1 kHz fo + 2p R1 C1 + Output

R1 C3

Figure 20. 0.5-Hz Square-Wave Oscillator

Figure 21. High-Q Notch Filter

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION
VCC+ Output A − VCC+ − 10 kΩ 10 kΩ + TIL601 10 kΩ 10 kΩ 10 kΩ 100 pF TL061 − Output

1 MΩ VCC+ −

TL064 + VCC+ TL064 + TL064 +

Input 100 kΩ

100 kΩ 100 µF 100 kΩ

Figure 22. Audio-Distribution Amplifier

10 kΩ

5 kΩ

Figure 23. Low-Level Light Detector Preamplifier

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

1 µF

TL064 +

Output B

VCC+ Output C

15 V

−15 V

17

SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
APPLICATION INFORMATION
VCC+

0.1 µF 10 kΩ 10 kΩ 50 Ω − TL061 + N2 0.1 µF 10 kΩ N1 250 kΩ 1 MΩ Output

Figure 24. AC Amplifier
10 kΩ 0.1 µF + TL061 − 1.2 MΩ 2.7 kΩ 100 kΩ 270 Ω + 20 µF 0.003 µF 0.001 µF 100 kΩ 50 kΩ 10 kΩ 1 µF 10 kΩ 0.002 µF 0.06 µF 100 kΩ 1 kΩ 0.06 µF

47 kΩ

100 kΩ

50 kΩ

0.02 µF

Figure 25. Microphone Preamplifier With Tone Control

IN+

+ TL062 −

Output 100 kΩ

1 kΩ 1 kΩ 100 kΩ − TL062 +

IN−

Figure 26. Instrumentation Amplifier

18

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TL061, TL061A, TL061B, TL062, TL062A TL062B, TL064, TL064A, TL064B LOW POWER JFET INPUT OPERATIONAL AMPLIFIERS
SLOS078J − NOVEMBER 1978 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION
IC PREAMPLIFIER RESPONSE CHARACTERISTICS
25 20 15 Voltage Amplification − dB 10 5 0 −5 −10 −15 −20 −25 Min Bass 40 Max Bass Max Treble

20 220 kΩ 0.00375 µF 0.01 µF 27 kΩ VCC+ 100 Ω Input 100 Ω Balance 10 pF 75 µF + 50 pF 47 kΩ + TL062 − VCC−

100 200 400

1k 2k

4k

f − Frequency − Hz

10 kΩ MIN 100 kΩ Bass MAX

0.03 µF MIN 100 kΩ Treble MAX

10 kΩ 0.03 µF

1 µF

10 kΩ 10 pF + 47 µF 68 kΩ

5 kΩ Gain

Figure 27. IC Preamplifier

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

ÁÁÁ ÁÁÁ

ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ
VCC± = ±15 V TA = 25°C

ÁÁÁ ÁÁÁ

Min Treble

10 k 20 k

0.003 µF

3.3 kΩ

VCC+ + TL062 −

Output

0.003 µF

VCC−

19

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PACKAGING INFORMATION
Orderable Device 81023012A 81023022A 8102302HA 8102302PA 81023032A 8102303CA 8102303DA TL061ACD TL061ACDE4 TL061ACDR TL061ACDRE4 TL061ACP TL061ACPE4 TL061ACPSR TL061ACPSRE4 TL061BCD TL061BCP TL061BCPE4 TL061CD TL061CDE4 TL061CDR TL061CDRE4 TL061CP TL061CPE4 TL061CPSR TL061CPSRE4 TL061CPWLE TL061ID TL061IDE4 Status (1) OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE Package Type LCCC LCCC CFP CDIP LCCC CDIP CFP SOIC SOIC SOIC SOIC PDIP PDIP SO SO SOIC PDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP SO SO TSSOP SOIC SOIC Package Drawing FK FK U JG FK J W D D D D P P PS PS D P P D D D D P P PS PS PW D D Pins Package Eco Plan (2) Qty 20 20 10 8 20 14 14 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 75 75 50 50 75 75 1 1 1 1 1 1 75 75 TBD TBD TBD TBD TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish Call TI A42 SNPB A42 SNPB A42 SNPB A42 SNPB CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU MSL Peak Temp (3) Call TI N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Call TI N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM

POST-PLATE N / A for Pkg Type

POST-PLATE N / A for Pkg Type

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 Pb-Free (RoHS) Pb-Free (RoHS)

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) TBD Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 Pb-Free (RoHS) Pb-Free (RoHS)

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) TBD Green (RoHS & no Sb/Br) Green (RoHS &

Addendum-Page 1

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Orderable Device

Status (1)

Package Type SOIC SOIC PDIP PDIP CDIP CDIP SOIC SOIC SOIC SOIC CDIP PDIP PDIP SO SO SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC

Package Drawing D D P P JG JG D D D D JG P P PS PS D D D D P P D D D D D D

Pins Package Eco Plan (2) Qty no Sb/Br) 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 50 50 75 75 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

Lead/Ball Finish

MSL Peak Temp (3)

TL061IDR TL061IDRE4 TL061IP TL061IPE4 TL061MJG TL061MJGB TL062ACD TL062ACDE4 TL062ACDR TL062ACDRE4 TL062ACJG TL062ACP TL062ACPE4 TL062ACPSR TL062ACPSRE4 TL062BCD TL062BCDE4 TL062BCDR TL062BCDRE4 TL062BCP TL062BCPE4 TL062CD TL062CDE4 TL062CDG4 TL062CDR TL062CDRE4 TL062CDRG4

ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU

Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Call TI Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Call TI N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) TBD Pb-Free (RoHS) Pb-Free (RoHS)

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 75 75 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 75 75 75 Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS &

Addendum-Page 2

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Orderable Device

Status (1)

Package Type CDIP PDIP PDIP SO SO SO TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP SOIC SOIC SOIC SOIC SOIC SOIC CDIP PDIP PDIP TSSOP TSSOP LCCC CDIP CDIP SOIC SOIC

Package Drawing JG P P PS PS PS PW PW PW PW PW PW D D D D D D JG P P PW PW FK JG JG D D

Pins Package Eco Plan (2) Qty no Sb/Br) 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 20 8 8 14 14 50 50 50 50 TBD Pb-Free (RoHS) Pb-Free (RoHS) TBD 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 150 150 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 75 75 75 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

Lead/Ball Finish

MSL Peak Temp (3)

TL062CJG TL062CP TL062CPE4 TL062CPSLE TL062CPSR TL062CPSRE4 TL062CPW TL062CPWE4 TL062CPWLE TL062CPWR TL062CPWRE4 TL062CPWRG4 TL062ID TL062IDE4 TL062IDG4 TL062IDR TL062IDRE4 TL062IDRG4 TL062IJG TL062IP TL062IPE4 TL062IPWR TL062IPWRE4 TL062MFKB TL062MJG TL062MJGB TL064ACD TL064ACDE4

OBSOLETE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

Call TI CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU

Call TI N / A for Pkg Type N / A for Pkg Type Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Call TI N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) TBD Pb-Free (RoHS) Pb-Free (RoHS)

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 1 1 1 50 50 TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

POST-PLATE N / A for Pkg Type A42 SNPB A42 SNPB CU NIPDAU CU NIPDAU N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM

Addendum-Page 3

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18-Nov-2006

Orderable Device TL064ACDR TL064ACDRE4 TL064ACN TL064ACNE4 TL064BCD TL064BCDE4 TL064BCDR TL064BCDRE4 TL064BCN TL064BCNE4 TL064CD TL064CDBR TL064CDBRE4 TL064CDE4 TL064CDR TL064CDRE4 TL064CN TL064CNE4 TL064CNSR TL064CNSRE4 TL064CPW TL064CPWE4 TL064CPWLE TL064CPWR TL064CPWRE4 TL064ID

Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE

Package Type SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP SOIC SSOP SSOP SOIC SOIC SOIC PDIP PDIP SO SO TSSOP TSSOP TSSOP TSSOP TSSOP SOIC

Package Drawing D D N N D D D D N N D DB DB D D D N N NS NS PW PW PW PW PW D

Pins Package Eco Plan (2) Qty 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 25 50 50 Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU

MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 25 50 Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br)

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 50 Green (RoHS & no Sb/Br)

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 25 Pb-Free (RoHS) Pb-Free (RoHS)

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 90 90 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 50 Green (RoHS & no Sb/Br)

Addendum-Page 4

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18-Nov-2006

Orderable Device TL064IDE4 TL064IDG4 TL064IDR TL064IDRE4 TL064IDRG4 TL064IN TL064INE4 TL064INS TL064INSG4 TL064INSR TL064INSRG4 TL064MFK TL064MFKB TL064MJ TL064MJB TL064MWB
(1)

Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

Package Type SOIC SOIC SOIC SOIC SOIC PDIP PDIP SO SO SO SO LCCC LCCC CDIP CDIP CFP

Package Drawing D D D D D N N NS NS NS NS FK FK J J W

Pins Package Eco Plan (2) Qty 14 14 14 14 14 14 14 14 14 14 14 20 20 14 14 14 50 50 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU

MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 25 50 50 Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 1 1 1 1 1 TBD TBD TBD TBD TBD

POST-PLATE N / A for Pkg Type POST-PLATE N / A for Pkg Type A42 SNPB A42 SNPB A42 SNPB N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

Addendum-Page 5

PACKAGE OPTION ADDENDUM
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18-Nov-2006

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 6

MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8)
0.400 (10,16) 0.355 (9,00) 8 5

CERAMIC DUAL-IN-LINE

0.280 (7,11) 0.245 (6,22)

1

4 0.065 (1,65) 0.045 (1,14)

0.063 (1,60) 0.015 (0,38)

0.020 (0,51) MIN

0.310 (7,87) 0.290 (7,37)

0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN

0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20)

0°–15°

4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

MECHANICAL DATA
MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)
28 TERMINAL SHOWN

LEADLESS CERAMIC CHIP CARRIER

18

17

16

15

14

13

12

NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20

A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)

B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)

19 20 21 B SQ 22 A SQ 23 24 25

26

27

28

1

2

3

4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)

0.020 (0,51) 0.010 (0,25)

0.055 (1,40) 0.045 (1,14)

0.045 (1,14) 0.035 (0,89)

0.028 (0,71) 0.022 (0,54) 0.050 (1,27)

0.045 (1,14) 0.035 (0,89)

4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004

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• DALLAS, TEXAS 75265

MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999

P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5

PLASTIC DUAL-IN-LINE

0.260 (6,60) 0.240 (6,10)

1

4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gage Plane

0.020 (0,51) MIN

0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M

0.430 (10,92) MAX

4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M

PLASTIC SMALL-OUTLINE

0,25 0,09 5,60 5,00 8,20 7,40

Gage Plane 1 A 14 0°– 8° 0,25 0,95 0,55

Seating Plane 2,00 MAX 0,05 MIN 0,10

PINS ** DIM A MAX

14

16

20

24

28

30

38

6,50

6,50

7,50

8,50

10,50

10,50

12,90

A MIN

5,90

5,90

6,90

7,90

9,90

9,90

12,30 4040065 /E 12/01

NOTES: A. B. C. D.

All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)
14 PINS SHOWN

PLASTIC SMALL-OUTLINE PACKAGE

0,65 14 8

0,30 0,19

0,10 M

0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0°– 8° 0,75 0,50

Seating Plane 1,20 MAX 0,15 0,05 0,10

PINS ** DIM A MAX

8

14

16

20

24

28

3,10

5,10

5,10

6,60

7,90

9,80

A MIN

2,90

4,90

4,90

6,40

7,70

9,60

4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

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