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A REVIEW ON PERFORMANCE ANALYSIS OF FIELD EFFECT DEVICES AT MICROWAVE FREQUENCIES

Sudhanshu Arya
hodece@mitrc.ac.in

Lecturer , Modern Institute Of Technology & Research Centre. AbstractThe important noise sources in FET devices, from a microscopic point of view are scattering mechanism such as alloy fluctuations and interface roughness on heterojunction. In communication theory, noise and bandwidth limit the information that can be transferred in a communication channel. Noise can be subtle and elusive. Whereas most signals have frequency, waveform, or modulation we can control, noise usually looks just like noise and is difficult to trace or localize. Classical noise analysis is based on the power resulting from thermal noise but the measured power will depend on the system gain and the measurement bandwidth.

A gate schottky contact is directly realized in the active channel layer. It is to be noted that the mobility of the free electrons located in the channel under the gated, i.e. under the depleted layer decreases due to the presence of ionized doping atoms. GaAs is an insulator, which make monolithic microwave integrated circuits (MMICs) practical. Pure silicon is a better conductor than pure GaAs, so it tends to dissipate electric fields that are necessary for transmission modes.

I.

INTRODUCTION

Field effect transistor (FET) technology constitutes the best low noise technology so far. And this is only possible because Field Effect Transistor technology has continuously evolved. In order to provide a clear picture of this evolution, let us consider the cross section of three FET devices: a gallium arsenide (GaAs) metal semiconductor FET (MESFET), a III V high electron mobility transistor (HEMT) and a silicon MOSFET.

Figure1. GaAs MESFET III V HEMT With the development of III V HEMT during the early eighties, the FET technology continued to improve. In this technology, a heterojunction is built up through the association of a doped schottky barrier layer with a channel layer. The schottky barrier layer has the higher bandgap. This system offers high flexibility in terms of channel engineering (that is, the cost of higher mobility material for the small bandgap channel layer).

GaAs MESFET The basic device operation can be interpret as: 1. An electrostatic control of the channel charge operated by the dc gate to source voltage, and 2. A flow of current from source to drain controlled by the dc drain to source voltage (field effect).

The important noise sources, from a microscopic point of view are scattering mechanism such as alloy fluctuations and interface roughness on heterojunction. This will have an major impact on the device parameters such as resistances. The lower heterojunction interface of the channel, in case of HEMT, is very important, as it is clear from the conduction band diagram and the electron distribution at the low noise bias point, i.e., near VT.

Figure2. HEMT In this system, the interaction between electrons forming the channel and ionized doping atoms (from which electrons were released) is suppressed, and hence the mobility increases, as compered to the GaAs MESFET. By optimizing the intrinsic trasconductance Gm, a very high current gain cut off frequency (fT) can be achieved, and hence low noise FET technology can be obtained. fT = 1

Figure3. 2 dimensional electron gas To have a reasonable voltage gain, >= 10, where Gd is the FET output conductance, there must required a reasonable aspect ratio (LG / A >= 5) to maintain good channel charge control by the gate electrode. Moreover, due to the presence of extrinsic parasitic resistances featuring thermal noise, the total noise generated by the FET at its output becomes higher. As a consequences, special effort must be paid to achieve a lower source resistance RS (that is to optimize the source contact resistance) and gate resistance Rg (that is, to realize mushroom gates fro III V HEMTs or multigate fingers for silicon MOSFETs), respectively. Reasonable output conductance

where Cgs = gate to source capacitance, Cgd = gate to drain capacitance. The high value of fT made both through gate length down scaling and channel engineering (that is, channel material is chosen to increase the mobility and peak velocity for III V HEMTs). At high frequencies, the principle source of noise added by the transistor are related to power dissipation in the resistances of the device. At lower frequencies, generation and recombination process becomes dominant.

HIGH FREQUENCY NOISE IN FETs

Among the different figures of merit available to illustrate the low noise characteristics of FET technologies, noise figure (NF) is among the most important. Lets conseder a two port device:

noise FET technologies. The overcome this problem, the minimum NF, NFmin which corresponds to NF obtained when the (complex) admittance generator is equal to the optimum noise source admittance Yout = Gopt + j.Bopt) Yopt, is much more suitable. For and generator admittance Ys = Gs + j.Bs, NF is given by NF(Ys) = NFmin + | | 2, ..........3

Figure4. Noisy two port device. NF is defined in [1] as:

Where Rn, having the dimension of a resistance, is called the equivalent noise resistance. Thus, a full characterization of nosie properties of any two port device (passive or active) requires the knowledge of four parameters: NFmin, Rn, Gopt, Bopt. From (3) it is clear that, when designing a low noise amplifier, Rn has to be as low as possible to prevent a potential mismatch (more details in [2]).

NF =

; Ys at To = 290 K 2

where Ys is the admittance of the ac current generator, To is the standard noise temperature, and Sout and Sin are the input and output available signal power, respectively. Nin is the input available noise power ( = k.To. f, where f is the frequency bandwidth), and Nout is the output available noise power. The available power gain can be defined as Ga = Sout/Sin, and consider that the two port device adds a noise power Na at the output, NF may be written as NF = = = 1 + 3 ; Ys at To = 290 K Figure5. NF and Gain versus Drain Current.

It is clear from the equation - (3), that NF 1 (or 0 dB). The NF depends on Ys, and this complicates the benchmarking of different low

Though the NFmin of a GaAs pHEMT already enables good low noise performance, it still too high to address a number of important applications in W (75 110 GHz) and G (140 220 GHz) bands, respectively, for which LNAs operate at cryogenic temperature. For such applications, the best low nosie FET

technology is InP HEMT. This technology perfroms better than GaAs pHEMT technology, achieving Nfmin of 1.4 dB [3] at 95 GHz. While LG = 0.15 m in [3] is larger than for the GaAs pHEMT, the technology benefits from higher Gm / fT values, which are explened by better dynamic properties (improved mobility and peak velocity in the channel). Rg, Rs, and Lg / A were also optimized (fmax = 405 GHz in [3]). All of this contributes to make InP HEMT the best low noise technology currently. This technology has been widely used at cryogenic temperatures to develop extremely low noise amplifiers [4]. The low cost silicon CMOS technology features good NFmin but does not outperform GaAs pHEMT despite and aggressive gate length downscaling [5]. CONCLUSION In this article, a short presentation of available FET technologies (GaAs MESFET, III V HEMT, and silicon CMOS) has been presented. InP HEMT technology undoubtedly constitutes the best low noise technology (espacially to address applications in W or G Band). The noise perfromance of silicon MOSFET technology, which is widely used in many applications because of its low cost, does not outperform that of GaAs pHEMT technology, unless channel engineering is performed.

[3] P.C. Chao, A.J. Tessmer, K.H. G. Duh, P. Ho. M.Y. Kao, P. M. Smith, J.M. Ballingall, S.M.J. Liu, and A. A. Jabra, W band low noise InAlAs / InGaAs lattice matched HEMTs, IEEE Electron Device Lett., vol. 11, no. 1, pp. 59 62, Jan. 1990. [4] M.W. Pospieszalski, Extremely low noise amplification with cryogenic FETs and HFETs: 1970 2004, IEEE Microwave Mag., vol. 6, no. 3, pp. 62 75, Sept. 2005. [5] S. Lee, L. Wagner, B. Jagannathan, S. Csutak, J. Pekarik, N. Zamdmer, M. Breitwish, R. Ramachandran, and G. Freeman, Record RF performance of sub 46 nm LGATE NFETs in microprocessor SOI CMOS technologies, in Proc. IEEE Int. Electron Device Meeting (IEDM 2005), Dec. 2005, pp. 251 254. [6] A. Van der Ziel, Thermal noise in field effect transistor, Proc. IRE, vol. 50, pp. 1808 1812, Aug. 1962. [7] A. Van der Ziel, Gate noise in field effect transistors at moderately high frequencies, Prco. IRE, vol. 51, pp. 461 467, Mar. 1963. [8] T. C. Lim, R. Valentin, G. Dambrine, and F. Danneville, MOSFETs RF noise optimization via channel engineering, IEEE Electron Device Lett., vol. 29, no. 1, pp. 118 121, Jan. 2008. [9] M. Ding and R. Vemuri., A Combined Feasibility and Performance Macromodel for Analog Circuits, in Proc. IEEE Design Automation Conference, pp. 63-68, 2005. [10] R. Sangeetha and B. Kalpana., Identifying Efficient Kernel Function in Multiclass Support Vector Machines, International Journal of Computer Applications, vol. 28, no. 8, 2011.

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