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Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240

Literature Number: BPRA072 Texas Instruments Europe November 1997

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Copyright © 1997, Texas Instruments Incorporated

Contents

Contents
1. Introduction.............................................................................................................. 1 2. Sensorless Brushless DC Drive Presentation.......................................................... 1 2.1 The motor ..................................................................................................... 1 2.2 The control hardware .................................................................................... 1 2.3 The Power Electronics Hardware ................................................................. 2 2.3.1 The Power Conversion Dedicated Hardware .............................. 2 2.3.2 The Sensorless Dedicated Hardware .......................................... 3 2.4 The control algorithm .................................................................................... 4 3. Sensorless Principles .............................................................................................. 4 3.1 Theoretical Background ................................................................................ 5 3.2 Practical Point of View .................................................................................. 6 3.2.1 Neutral Point Voltage Computation ............................................. 6 3.2.2 Bemf Zero Crossing Point Computation ...................................... 8 3.2.3 Electrical Behaviour at Commutation Points................................ 8 3.2.4 Some Bemf Zero Crossing Results ............................................. 9 3.2.5 Commutation Instants Computation .......................................... 10 3.2.6 Self Correction of Phase Use Imbalance................................... 11 3.2.7 Startup Procedure ..................................................................... 13 4. Software Organization ........................................................................................... 15 4.1 DSP Controller Setup ................................................................................. 15 4.2 Software Variables Initialization .................................................................. 16 4.2.1 Bemf Scanning function variables ............................................. 16 4.2.2 Commutation Algorithm Variables ............................................. 17 4.2.3 Rotor Magnetic Stall Variables .................................................. 17 4.2.4 Current Loop Variables.............................................................. 17 4.2.5 Speed Loop Variables ............................................................... 18 4.3 Interrupts Flow Charts................................................................................. 18 4.3.1 PWM Unit Interrupt Flowchart ................................................... 18 4.3.2 ADC Unit Interrupt Flowchart..................................................... 20 4.4 SEQUENCE Function Flow Chart............................................................... 21 5. Summary ............................................................................................................... 22 References ................................................................................................................ 23 Appendix A Sensorless BLDC Drive Control Assembly Code .................................. 24 Appendix B Linker File.............................................................................................. 37

Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240

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Contents

List of Figures
Figure 1: Top View of TMS320F240 EVM Board .............................................................. 2 Figure 2: Power Electronics Topology .............................................................................. 3 Figure 3: Basic Sensorless Additional Hardware .............................................................. 4 Figure 4: Stator Terminal Electrical Model ........................................................................ 5 Figure 5: Bemf Wave-form Shapes................................................................................... 6 Figure 6: PWM Strategy and Operating System ............................................................... 8 Figure 7: Zero Crossing Results at Different Running Speeds.......................................... 9 Figure 8: Computed Commutation Instants vs Hall Effect Sensor Outputs ..................... 11 Figure 9: Balanced and Unbalanced Phase Use ............................................................ 12 Figure 10: Phase Use Imbalance Correction Module...................................................... 12 Figure 11: Phase Use without and with Imbalance Corrector ......................................... 13 Figure 12: Global Structure of the Sensorless Control Code .......................................... 15 Figure 13: PWM Interrupt Flowchart ............................................................................... 19 Figure 14: ADC Interrupt Flowchart ................................................................................ 20 Figure 15: SEQUENCE Function Flowchart.................................................................... 21

Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240

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The thooless stator is made of ironless windings. In this Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 1 . provides the sensorless control DSP Controller software and demonstrates some really effective benefits.8mNm/A. It is assumed to have trapezoidal back electromotive force (Bemf) wave form shapes and is supplied with direct current. This document describes a method for commutation of a BLDC motor requiring no rotor position sensor and suppressing the position sensor cost at no cost other than software. it is desirable to eliminate the rotor position sensor used to operate the Brushless Direct Current (BLDC) motor. The DC bus voltage is 18V. This application report covers the TMS320F240 DSP Controller. The present application note describes how a sensorless.2 The control hardware The control hardware can be either the TMS320F240 Evaluation Module introduced by Texas Instruments or the MCK240 developed by Portescap/Technosoft. 2. In order to reduce the system cost.Implementation of a Sensorless Speed Controlled Brushless DC Drive using the TMS320F240 ABSTRACT The DSP Controller TMS320F240 from Texas Instruments is suitable for a wide range of motor drives.045mH (measured at 1kHz) and the phase resistance is 300mΩ. TMS320F240 provides a single chip solution by integrating on-chip not only a high computational power but also all the peripherals necessary for electric motor control. The control described here operates in closed loop from zero speed. The initial rotor position is fixed by energizing one. brushless DC drive can be implemented using TMS320F240. Introduction Controlling a synchronous permanent magnet trapezoidal Bemf shape motor by direct current results in a simple low cost drive with a high mechanical power density. This document shows that this sensorless solution is single chip and really cost effective in comparison with the sensored solution. It has one magnetic non-salient pole pair on the rotor. 1. 2. The maximum permissible current at 5000rpm is 2.9A and the torque constant is equal to 11. arbitrarily selected phase. Sensorless Brushless DC Drive Presentation 2. speed controlled. The stator phase inductance is 0.1 The motor The synchronous machine with permanent magnets used in this application note is a three-phase Y-connected motor.

application. The power switches used are power MOSFETs IRFP054. varistor peak current protection). Clearfault. The pre-driver output signals go through a resistor and then directly to the power switches.3. Figure 1: Top View of TMS320F240 EVM Board 2. Fault. The sizing of the shunt resistor is such that. Current sensing is achieved by a low cost shunt resistor. Its voltage drop is interfaced with TMS320F240 as shown in Figure 3. See the figure below depicting the EVM board. at maximum allowed current. The figure below shows the converter which is used here. the second board can be plugged directly onto the power electronics board. The reader can find a complete detailed technical description of this inverter in a separate dedicated report [5]. All the power device security features are hard-wired (Shutdown. The two boards contain a DSP controller TMS320F240 and its oscillator. This hardware configuration allows hard chopping as well as soft chopping operation. The RC cell is designed to filter Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 2 . The converter topology supports either sinusoidal currents (Three phases ON operation) or direct currents (two phases ON operation). Itrip. The relative ground of the upper half-bridge is realized with bootstrap capacitors. The chosen PWM strategy is the soft chopping mode with symmetrical modulation. The pre-driver component selected is the IR2131 and the TMS320F240 PWM output signals are directly connected (no buffers).1 The Power Conversion Dedicated Hardware The power board is designed to support an 18V DC voltage supply and a 300W power range. reverse battery diode.5V (Voltage threshold to enable the driver’s over-current protection). a RS232 link and the necessary output connectors.3 The Power Electronics Hardware 2. a JTAG. The latter control is implemented in this application note. the voltage drop across the shunt is equal to 0.

A feedback gain is set so that the shunt voltage drop range utilizes the whole ADC input voltage range. 2.not only the commutation noises but also the chopping noise. the feedback gain should be set to ten. So if the ADC voltage reference is set to five volts. Also due to this small electrical time constant. This feature is not used in the control software described because of the very small electrical time constant and hence the small amount of time necessary to get the Direct Current out of the windings. In fact the sensorless BLDC drive presented here is much more cost effective than the ASIC or MCU based ones as these must include several additional operational amplifiers and/or ICs on the power board. Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 3 . which require a new ASIC design and/or new op amp adjustments.2 The Sensorless Dedicated Hardware The figure below shows the basic hardware necessary to run the sensorless control described. Note also that this hardware may be easily and freely modified to fit different motor characteristics. This shows that the system cost saving is highly efficient as the mechanical position sensor is fully replaced in terms of hardware by very low cost resistors. A break feature is realized with another MOSFET and a power resistor. This makes this sensorless dedicated hardware more upgradable and versatile than ASIC and MCU based solutions. M1 M3 M5 FULL COMPARE UNIT M2 M4 M6 Load Shunt Resistor ADCIN05 Figure 2: Power Electronics Topology The bold arrows on the wires depict the Direct Current flowing into two motor phases.3. the chopping frequency is set at 80kHz.

to get more precise information about speed and current regulation please refer to [3]. The innermost one is to get the rotor position in order to correctly commutate the stator flux. By contrast. The filtering capacitor should filter the chopping frequency.4 The control algorithm According to [3]. no star connection wired out of the motor Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 4 . Assuming that the stator flux is proportional to the current flowing in the stator coils. the magnitude of the stator flux has to be generated and controlled. achieving a BLDC speed control requires three control layers to be performed. The outermost control loop is the speed regulation loop. Nevertheless. Once the rotor position is known. As the motor and the power electronics board used in this application are the same as the ones used in [3]. Note that the DSP Controller F240 ADC Unit requires a 1µs sample time per kΩ on the analog line. 2. So if the ADC reference voltages are set to zero and five volts and if the DC bus voltage is 18V. The sensorless algorithm is based only on the three terminal voltage measurements and thus requires only four ADC input lines out of the 16 available. the control of the stator flux magnitude is equivalent to the control of the input current. 3. the bridge ratio should be equal to 0.Stator Phase #x Cable ADCINx ADCIN05 Figure 3: Basic Sensorless Additional Hardware The resistance bridge is specified such that the maximum bridge output utilizes the full ADC conversion range. the means of obtaining the rotor position and the corresponding software will be fully explained. so only very small values are necessary (in the range of nF).27. Sensorless Principles The aim of this document is to present a DSP based solution able to deliver to the classic BLDC drive control the necessary rotor position without any help other than the F240 DSP Controller capabilities (no additional ICs. the corresponding software is included with the software given in the appendix.

The next paragraph shows how it is possible to get the three Bemfs and their zero crossings. where L is the phase inductance. dt As only two currents flow in the stator windings at any one time. This implies that only six commutation signals are sufficient to drive a BLDC motor. an efficient control implies a synchronization between the phase Bemf and the phase supply so that the Bemf crosses zero once during the non-fed 60º sector. Vn is the star connection voltage referenced to ground and Vx is the phase voltage referenced to ground. The following description gives a succinct theoretical background and covers every practical aspect. two phase currents are opposite and the third one is equal to zero.housing). R is the phase resistance. Furthermore. Furthermore. The figure below depicts the motor terminal model. Vx voltages are measured by means of the DSP controller ADC Unit and via the resistance bridge depicted in figure 3. 3. knowing that the sum of the three stator currents is equal to zero (star wound stator) and given the following instantaneous Bemf wave forms: Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 5 . the phases are commutated once every 60º mechanical rotation of the rotor. E is the back electromotive force. Ex R Ix L Vx Shunt Resistor Vn Figure 4: Stator Terminal Electrical Model Each stator terminal voltage can be modelled as follows: dIx Vx = RIx + L + Ex + Vn .1 Theoretical Background According to [4] in the sensored control structure.

thanks to the DSP Controller. Each software module will be addressed by one dedicated sub chapter.5µs. 3 3 For the non-fed phase (zero current flowing). So we have Vn = 1 * 3 x =1 ∑ Vx . They Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 6 . 3. Due to the very small phase electrical time constant the chopping frequency has been set at 80kHz. Let us explain how the ADC is managed in order to perform this real time task. 3. ∑ Vx . It also deals with the theory limitations and the practical solutions used to overcome them.1 Neutral Point Voltage Computation As shown above. The above mentioned equations are implemented in the code given below.1 revolution Ea Eb Ec θ Figure 5: Bemf Wave-form Shapes the sum of the three stator terminal voltages is equal to three times the neutral point voltage (Vn). it is possible to derive the six required items of information regarding the commutation.2 Practical Point of View This chapter presents the practical implementation of the above theory. So four PWM period flags occur in one current loop period. The PWM period is then equal to 12. the neutral point voltage computation requires that we should know the three instantaneous terminal voltages referenced to ground.2. the stator terminal voltage can be rewritten as follows: 1 Enon fed = Vnonfed − Vn = Vnonfed − * 3 x =1 As each of the Bemfs crosses zero twice per mechanical revolution. and as the Bemfs are numerically easy to compute. The current regulation loop period has been set to 50µs.

At the End Of Conversion an interrupt to the core is requested.are all acknowledged by the DSP Controller Core and the corresponding interrupt subroutine is initiated. Only when the current PWM period ISR is the first or the second (among the four available during one current control loop) is a conversion is started by software. acknowledged and initiates processing of the two results. The following plot depicts the organization of the interrupts. Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 7 .

Current Loop Period PWM Period End Of Conversion Interrupt PWM Interrupt 12. 3. the two conversion results and reloading of the current and second terminal voltage channels. Once these two results have been processed. high dV/dt and dI/dt glitches may occur due.2. As we are interested in the zero crossing of the Bemf it is possible to look solely at the Bemf sign change.2.5 50 Time in µs Figure 6: PWM Strategy and Operating System The first conversion gives the phase current. the computation of the neutral point voltage according to the formula given above. this only assumes that the Bemf scanning loop period is much shorter than the mechanical time constant.5µs).2 Bemf Zero Crossing Point Computation Once the neutral point voltage is available it is necessary to get the Bemf of the non-fed phase.6µs 37. Note that this real time sampling structure fits any chopping and regulation frequencies: for a motor requiring a 20kHz chopping frequency we can easily imagine a current regulation loop frequency at 10kHz and still having the three terminal voltages. The second End Of Conversion subroutine handles two tasks: firstly. once every 50µs and out of any ISR during the PWM duty cycle update. This function is computed after the three terminal voltage samples. 3.3 Electrical Behaviour at Commutation Points At the instants of phase commutation. secondly. these glitches. for example. can lead to a misreading of the computed neutral voltage. the ADC input channels dedicated to the two other phase terminal voltage measurements are selected. In addition to the Electro-Magnetic Interference troubles that they might generate. This solution assumes that the variation of the phase terminal voltage is negligible during one PWM period (12. This problem Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 8 . These is achieved by subtracting the computed neutral voltage from the non-fed phase terminal voltage. to the direct current level or to the parasitic inductance and capacitance of the power board. and the second the phase terminal voltage information. as well as the non-symmetrical three phase system created by the power stage.5 25 6.

is solved by discarding the first scans of the Bemf once a new phase commutation occurs. This parameter is system-dependent and should be set to a large value in the early development stages. The duration depends on the power switches. channel #2 is the corresponding half. the power board design.4 Some Bemf Zero Crossing Results Figure 7: Zero Crossing Results at Different Running Speeds On each oscilloscope picture the channel #1 represents one phase current. channel #3 is the computed neutral point voltage Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 9 . 3.2. the phase inductance and the driven direct current. The discard duration is fully customizable as this is a software module.bridge voltage. Later on it is possible to tune to a very small discard duration in order to achieve a better control.

Channel #1 spikes represent the computed commutation points.and the channel #4 gives one peak each time the software detects the zero crossing of the scanned Bemf. The most interesting information is given by the neutral voltage computation: even if there are very high commutation glitches and/or measurement noises the software recognizes them as glitches thus making it possible to detect the right Bemf sign change. 3. this early arrival of the commutation point will tend to accelerate the motor.5 Commutation Instants Computation In an efficient sensored control the Bemf zero crossing events are displaced 30º from the instants of phase commutation. Two charts are presented below which show the computation of the commutation point in comparison with the three Hall effect sensor outputs. There will be an opposite controller reaction if the motor accelerates. Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 10 . 1000 and 2000rpm. In spite of this advantage this shift time solution assumes that the motor speed variation between two revolutions is not too critical in comparison with the system dynamic behaviour. is added to the speed control loop. A question might be asked regarding the transient response of the system. The computed shift time will be too short in comparison with the actual shift time necessary. assume that the motor slows down and see how the control reacts. depending on the different desired speed ranges. channel #2. therefore. So before running the sensorless BLDC motor with help of the six zero crossing events it is necessary to compute the 30º shift of commutation points. We can imagine an additional software function giving the shift angle as output and taking the mechanical speed as input. This synchronization between the Bemf and the 60º sector is the main result to achieve in order to get the highest motor performance. In this control software it is implemented as follows: let T be the time that the rotor spent to complete the previous revolution and α be the desired shift angle. This is achievable because of the high frequency of neutral point voltage computation loop. The Bemf zero crossing algorithm has been successfully tested down to 30rpm. In fact. 3. So a position interpolation function should be realized. 4 represent the Hall sensor output. The different speeds tested here are respectively 600. In the software described. The channel #4 spikes (representing the Bemf zero crossing) find themselves in the middle of the non-fed sector. Let us. By dividing α by 360º and multiplying the result by T we obtain the amount of time (let us call it ‘shift time’) to be spent before commutating the next phase pair. α is fixed to 30º. So a kind of natural robustness. The left chart shows results at low speed (380rpm) and the right chart the results at high speed (2030 rpm). This high frequency can be reached thanks to the autonomous ADC peripheral and to the high DSP Controller CPU power. arising from the control algorithm. the angle shift might be to any angle.2.

6 Self Correction of Phase Use Imbalance Some imbalance in the phases’ use might be present when we simply apply the above algorithm (detection of the zero crossing point and waiting for the shift time to elapse before commutating the phases). A slight shift between the Hall sensor’s output and the computed commutation is noticeable. this is compensated by means of a phase use imbalance corrector. Another possible algorithm which could improve the dynamic behaviour is to compute the time spent by the rotor to achieve one third of a revolution. This is depicted below: Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 11 . then the computation of Tk − Tk −1 2 gives a smoother change in the shift time. It can simply be implemented by saving not only the revolution time at stage k but also the revolution time at stage k-1.2. thus improving the transient behaviour. For noise or system dynamics problems it is possible to design some slightly more complex algorithms: for example a low pass filter on the speed feedback could improve the transient behaviour.Figure 8: Computed Commutation Instants vs Hall Effect Sensor Outputs These charts show that very good results can be achieved at low or high speed. By ‘imbalance’ we understand that instead of having six equal 60º sectors per revolution we can have 40º wide and 80º wide sectors. This algorithm for determining the commutation point is based on the time spent by the rotor to make the previous revolution. 3. This last algorithm has a quicker reaction to speed variation but is much more sensitive to measurement noise.

. The imbalance is application dependent but can be approximated as a linear function of the mechanical speed and can be corrected thanks to software offset on the Bemf computation.0º 300º 60º 60º 80º 300º 40º 0º 80º 60º 60º 40º 60º 240º 180º 120º 240º 180º 120º Figure 9: Balanced and Unbalanced Phase Use This imbalance is created by the asymmetrical behaviour of the three phase system and of the terminal voltage measurement resistor bridges. Position K1 . The following structure solves this problem and is implemented in the code given below. K6 Va Vb Vc + + + + + 1/3 Corrected Bemf - Neutral Computation Bemf Computation Imbalance Corrector Figure 10: Phase Use Imbalance Correction Module The two ‘scope pictures below show the phase use without (left chart) and with (right chart) this additional correction module.. Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 12 .

2.7 Startup Procedure This sensorless BLDC drive DSP solution does not need any open loop starting strategy.1 First Shift Time Calculation The sensorless control software needs the shift time as a parameter to perform the first revolution.7.T. This time can be calculated off line by knowing the motor Torque constant and the braking torque (including friction losses and load) at startup. Step 3: the 60º sector adjacent to the initial rotor position is fed with Direct Current and the Bemf zero crossing detection algorithm is immediately started. If the motor shows a reluctance variation around the air gap the reluctance based method should be implemented to ensure the exact initial rotor position determination and to fix the direction of rotation. These charts make obvious the need for Bemf computation correction. The paragraphs below describe how to give the control software the a priori value of the shift time. The choice between the two initial position strategies is made according to the motor reluctance characteristics. Step 1: the algorithm gets the initial rotor position.2.Figure 11: Phase Use without and with Imbalance Corrector The imbalance corrector code might be improved by setting sector specific coefficients and by correcting the Bemf in each commutation sector (in the code below only one offset is computed and this offset is applied only on three of the six sectors). After one complete revolution the initial shift time (set a priori) is replaced by the computed one. The following steps are the procedure implemented to start the sensorless BLDC drive. 3. The fundamental dynamic principal applied to rotational systems: Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 13 . and two ways of getting the initial rotor position. 3. For a motor with no reluctance variation around the air gap (such as the motor used for this drive) the Rotor Magnetic Stall must be implemented. Step 2: the shift time algorithm is fed with an a priori shift time value.

The current flowing in the supplied phase pair is regulated to a value fixed a priori at the beginning of the software.3 Reluctance Based Rotor Initial Position If there is significant reluctance variation around the air gap (salient poles on the rotor…) we can measure each phase pair current response to a voltage pulse applied to each winding for a short and constant period of time.7. as we control the current flowing and as we know the torque constant ([Nm/A]). So at startup is it necessary to energize one arbitrary phase pair and wait for the rotor to be aligned with the stator flux that is created.7. This first shift time T is then given by the relation: T= 1 2 ∑ Ti i 4Jπ This calculated value should be divided by the Bemf scan loop period and the result should be stored into the software shift time variable. a constant measured signal means no rotor movement. To improve this sensorless drive the two questions above might be answered by scanning the non-fed phase and the results can be interpreted as follows: an oscillation of the measured voltages means back and forth movements of the rotor. Such an interpretation leads to an adaptive phase current level and to a time optimized function for obtaining initial rotor position. The system inertia can be calculated from the load characteristics.2. θ is the angular position and Ti represents torque) gives a double integral equation.2 Rotor Magnetic Stall When there is no reluctance variation around the motor air gap (as in the motor we used in this drive) it might be impossible to estimate the initial rotor position.and one that we can calculate. this equation needs to know system torque and inertia.2. Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 14 . 3. To be solved. Nevertheless the algorithm must address the following questions: how long should the algorithm wait for the shaft to stop oscillating prior starting the control loops? Is the applied torque enough to let the load move? In this application a counter is set so that the magnetic stall is performed for long enough to allow the to shaft to move and then stop oscillating. 3. The solution to this equation is the time necessary for the motor to perform one revolution. By evaluating the relative magnitude of the current flow through the phase windings it is possible to get the initial rotor position and thus to determine the proper starting phase of the motor. The torque sum might be considered as constant .J d 2θ dt 2 = ∑ Ti i (where J is the system inertia.

The overview of this software is given in the flow chart below: Start DSP Controller EV Setup Software Variables Init Power Drive Init Initialization Step Magnetic Stall Closed Loop Sensorless Control Run Mode End Figure 12: Global Structure of the Sensorless Control Code The following chapters deal with every module of the global flowchart presented. First of all the PLL unit is set so that the CPUCLK runs at 20MHz based on the 10MHz quartz crystal provided on the EVM board. Software Organization This chapter presents the overall software structure. The second module is the BLDC control dedicated software. The first one is performed only once at the beginning. This software is based on two modules: the initialization and the run module. The waiting loop can easily be replaced by a user’s interface (to get the reference speed and/or to monitor the control variables).1 DSP Controller Setup This part is dedicated to the handling of the different DSP Controller resources (Core settings and peripherals settings). and then set the two watchdog dedicated registers to be inactive. In this sensorless application the interrupts coming from the PWM unit and from the ADC unit are acknowledged. The last thing to do to complete the DSP Controller core initialization is to set the core mask register correctly. Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 15 .4. For the development stage it is necessary to disable the watchdog unit: first set the Vccp pin voltage to five volts by means of the EVM jumper. 4. the variables and the Interrupt Sub Routine flowcharts.JP5. It is based on a waiting loop interrupted by both the PWM Unit and the ADC Unit.

2. V2 and V3 are used in the ADC interrupt to save the respective phase terminal converted voltages. V2. 4. The PWM unit is also set to generate one interrupt when the timer counter reaches the timer 1 period value. CUR_COUNT is used in the PWM period interrupt as a PWM interrupt counter. To generate the necessary pulsed signals to the power electronics board the Full Compare Unit is used. When this flag is equal to one. Fifteen CPU cycles are saved in this way. OFFSET and FLAG. This is to make sure that there will not be any ripple in the sign change detection. the ADC unit is set to receive the Start Of Conversion from software and to generate an interrupt request to the core when the conversion is finished.Now let us have a look at the initialization of the peripherals. It is set to generate symmetrical non-complementary PWM signals at the frequency of 80kHz with TIMER1 as time base and with the DEADBAND unit disabled. It is used in order to know whether or not a conversion should be started (cf figure 6).2 Software Variables Initialization The second initialization step is the variable initialization. to the commutation algorithm. Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 16 .1 Bemf Scanning function variables The six variables used for this function are CUR_COUNT. V1. All of these variables are initialized to zero. NEUTRAL simply contains the sum of the three phase voltages rather than one third of the sum of the three phase voltages. to the rotor magnetic stall. thus making it possible to achieve very precise commutation angles. NEUTRAL. In this software 19 variables are needed. it is subtracted from the Bemf before comparing the Bemf to zero. Finally. 4. FLAG is set to one when the Bemf changes sign. they are described in this chapter. V3. As it takes a shorter time to perform a multiplication than a division. to the current regulator and to the speed regulator. the sign change detection is no longer performed until the next phase pair has been commutated. The PWM resolution is equal to the CPUCLOCK period: 50ns. The Bemf computation is performed by subtracting Neutral from three times the desired phase voltage. OFFSET is the single Bemf correction computed in this software. V1. NEUTRAL is also used in the ADC interrupt to store the computed neutral voltage. They can be sorted into five categories: variables which are dedicated to the Bemf scanning function. The new duty cycle reloads are made on the timer counter zero crossing at the frequency of 20kHz. OFFSET is computed in the speed control loop but is used in the SEQUENCE function.

This implies that the motor runs the first revolution with a regulated constant torque. direct current driven) and should be adjusted to each new drive. 10. Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 17 .2. The current 60º sector is stored in the CAPT variable. As soon as the Bemf crosses zero this counter is loaded with the computed shift time. BCOUNT and STALL. This counter increments every 50µs (every current regulation loop) until a preset value. SPEEDFLAG is a flag variable which (when set to one) disables any speed regulation during the first revolution. once loaded. the values that it can take are 0. the STALL variable is set to one. COMP and FLAGCUR. This counter is reset to zero every time a phase commutation occurs. BCOUNT is used in the ADC interrupt during the rotor magnetic stall as a counter. Once the BCOUNT counter reaches the predefined value. Before reaching the predefined value the computed Bemf is not taken into account.3 Rotor Magnetic Stall Variables The variables used in this function are SPEEDFLAG. Idc_errorK. ASYM is used as a counter in the SEQUENCE function. As CAPT is used in the SEQUENCE function to branch to the code which gives the right ACTR register setting. This preset value defines how many times the software has to stall the rotor in order to let the shaft stop oscillating prior starting the closed loop control. 3. 4.2. It increments at each new current regulation loop (in other words at each new neutral point voltage computation or. B2COUNT. They are all initialized to zero. 2. 4. 6). This counter. This flag is reset to zero when the first revolution has been completed thus allowing the speed control to run in closed loop. every 50µs) and up to the time it reaches the predefined value. 6.2 Commutation Algorithm Variables The variables used to compute the phase commutation point are ASYM. 12 (corresponding respectively to sector #1.4 Current Loop Variables The variables used for this function are Idc_ref. 8. 4. This counter function filters the imbalance of the three phase system created by the commutation. This variable is used as a flag which enables the closed loop control when set to one.2. which is set equal to the PWM period. decrements every 50µs and when it reaches zero the phases are commutated. 2. 4. 5. The predefined value is application dependent (power board design. These variables are initialized to zero apart from COMP. CAPT.4. that is. B2COUNT is used as a counter in the ADC interrupt.

three phase system asymmetry correction and PWM output. 4. Calling the outside functions is ensured by flags that are polled in the waiting loop and set inside the interrupts. SPEED_COUNT is used in the ADC interrupt to know if it is time to update the speed regulation loop. current regulation. 4. So in this software the lowest speed reachable is 19rpm. during closed loop control. If FLAGUP is equal to one. SPEED_COUNT.1 PWM Unit Interrupt Flowchart The interrupt request is generated every PWM period (cf figure 6.4MIPS among the 20 available.Idc_ref is the variable used to store the direct current reference given by the speed regulation. 4. In this case a conversion should be started at every PWM period. The PWM period interrupt lasts a maximum of 30 CPU cycles (1.27s (the time to complete one revolution). BCOUNT is the variable which contains the shift time (this shift time will be loaded into B2COUNT after any BEMF zero crossing).3 Interrupts Flow Charts The time diagram of the incoming interrupts is given by figure 6. The forthcoming chapters present the interrupt internal organizations. Some software features are realized in the interrupt subroutines and some are performed outside. The largest value that AR3 might contain is #0FFFFh (65535). then the revolution time is divided by 12 (one twelfth of a revolution is a 30º shift angle) and the result is stored into BCOUNT. So there is no longer any need to acknowledge the PWM Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 18 . BCOUNT.5µs) and thus needs 2. FLAGUP is initialized to zero and is set to one once a mechanical revolution has been completed.5 Speed Loop Variables The variables used here are SPEED_REF. Interrupt operations performed inside are: the starts of conversion.3. neutral point voltage computation. So after one complete revolution AR3 register contains the previous revolution time. Idc_errorK is used to store the current error before using it. note that the PWM period interrupt is NOT the PWM Timer period interrupt). Every 50µs the auxiliary register AR3 is incremented at the beginning of the SEQUENCE function.2. FLAGCUR is the flag used to tell the background waiting loop that it is time to give the inverter the new ACTR settings and the new duty cycle. Multiplying by 50µs gives 3. Interrupt operations performed outside are: Bemf computation. After completion of these tasks FLAGCUR is reset to zero in the SEQUENCE function. speed update calculation and phase commutation. With some changes the scheme below can be used with another chopping frequency: let us assume a 20kHz chopping frequency and a 10kHz current loop frequency. FLAGUP and the auxiliary register AR3. Bemf sign change detection. SPEED_REF is used to store the desired speed value. So. COMP is the output of the current regulator (in other words this is the updated duty cycle). The flowchart below depicts the ISR organization.

Start of PWM ISR Context Save & Interrupt Vector Reset Cur_count=Cur_count+1 Cur_count-2>0 Yes Cur_count-4<0 Yes No Start Of Conversion No Cur_count=0 Context Restore Endof PWM ISR Figure 13: PWM Interrupt Flowchart Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 19 . This would spare some more CPU power.interrupt request and the Start Of Conversion should be given automatically by the DSP Controller Event Manager.

The flowchart below depicts what operations are performed in this interrupt.2 ADC Unit Interrupt Flowchart The interrupt request is generated when the End Of Conversion signal reaches the DSP Controller core. Flagcur=1 Reload Idc & V2 Reset AR3 Set BCOUNT STALL=1 Speeflag=1 Context Restore Figure 14: ADC Interrupt Flowchart Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 20 . Start of ADC ISR Context Save No STALL<>0 SPEEDFLAG=0 No No Time to Speed Loop Speed Regulation Speedcount=Speed count+1 Reset Int Vector No Store V1 & V3 FLAG<>0 No First Conv Store Idc & V2 Current Regulator Stall=0 Output PWM Stall Count Increment No No End of Stall Speedflag=0 Bcount=AR3 ÷12 AR3=0 Flagcur=1 Reload V1 & V3 Context Restore End of ADC ISR Context Restore Flagup=0 No Revolution Completed No B2count=B2count-1 No B2count=0 Capt=Capt+2 Flag=0 Asym=0 Neutral calc.4.3.

4.What is missing at this point is the Bemf sign change detection as well as the output of PWM in the running mode. Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 21 . particularly at a high chopping frequency. If the sequence function were called from the ADC ISR there would be insufficient time to acknowledge the subsequent PWM period interrupt at the right point. This allows the ADC interrupt not to be too long.4 SEQUENCE Function Flow Chart Start of Sequence AR3 = AR3+1 Current 60º Sector Determination Output PWM Commutation Glitches Filtered No No FLAG=0 Bemf Computation & Sign Change Detection End of Sequence Return from Call Figure 15: SEQUENCE Function Flowchart The SEQUENCE is called by the waiting loop when Flagcur variable has been set to one (in the ADC interrupt). The ADC interrupt occurs 6.5µs. This is covered in the following chapter.6µs after the PWM period interrupt and the PWM period is equal to 12.

it is apparent that this sensorless drive might advantageously replace the sensored solution in a wide range of speed control applications. Summary This document deals with obtaining the rotor position of a sensorless Brush Less DC drive by means of software. Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 22 . This single chip solution is based entirely on the TMS320x24x DSP Controller capabilities: namely.5. Furthermore. this solution increases the drive reliability as the position information will no longer be sensitive to temperature or vibration. This makes the sensorless solution really cost effective and reliable. Assuming that the initial rotor position is detectable and knowing that this solution runs closed loop from quasi zero speed. This solution replaces the position sensor cost at no cost other than software development. high 2xx DSP core CPU power and extremely versatile peripherals.

Texas Instruments Inc. 5.Reference Set: Vol.Reference Set: Vol.1..1997 part #BPRA055. Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 23 ..References References 1. 1997. 1997. Texas Instruments Inc. DC 12-24V 30A Three Phase Power Hardware for either PMSM or AC Induction Machine. 1997 part #BPRA064. 4. 3. Texas Instruments Inc. Implementation of a Speed Controlled Brushless DC Drive using TMS320F240.1997 part #BPRA071. 2.. TMS320C24x DSP Controllers . TMS320C24x DSP Controllers .2 Texas Instruments Inc. Texas Instruments Inc. DSP Solutions for BLDC Motors.

1 .bss Idc_ref.bss V2. Bemf measurement.set 280 .1 . .bss SPEEDFLAG.1 .h" .bss Idc_errorK.bss CUR_COUNT. . capt indication .1 .Current regulator coeff setting .bss FLAGUP.asm .====================================== .Assign PWM interrupt vector Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 24 .bss NEUTRAL. File Name : sensor. Commutation dV/dt and dI/dT filtering . Reset & interrupt vectors .------------------------------------------.------------------------------------------.12 .1 .1 .1 .******************************************************** .1 .sect "vectors" RSVECT B _c_int0 .Date September 1997 .bss ASYM.bss FLAG. Target System : c240 evm .====================================== . Phases’ use imbalance Correction .1 .6 . .------------------------------------------.Q11 (1=2048) Kp=0.bss BCOUNT.bss B2COUNT.bss V1.------------------------------------------Kps .1 .include "c240app.1 .set 100 . Magnetic Stall at start up.1 .------------------------------------------.1 . .bss FLAGCUR. .bss STALL. 40W 18V July/97 .1 .bss V3.Speed regulator coeff setting .set 100 Kis .1 .1 .bss SPEED_REF.1 .1 .1 .bss OFFSET.bss stack.bss COMP.1 . Description : BLDC motor speed controlled .bss CAPT.------------------------------------------Kp . Sensorless Speed control based on .space 16*2 INT2 B PWMINT .********************************************************* .bss SPEED_COUNT. Variable definitions .Appendix A Sensorless BLDC Drive Control Assembly Code Appendix A Sensorless BLDC Drive Control Assembly Code .

WD_KEY .Appendix A Sensorless BLDC Drive Control Assembly Code INT6 .*+ #0.*+ #0.*+ #0. PLL disabled SPLK #00b1h. WD_CNTL SPLK #05555h.*+ #0.Reset sign extension mode .set up PLL clockin=10Mhz. set WDT for 1 .*+ #0.#stack AR3.WSGR .*+ #0.Set global interrupt mask .I/O setting p11-11 LDP #00E1h Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 25 .*+ AR2. Set up CLKOUT to be SYSCLK p6-6 SPLK #40C0h.global _c_int0 _c_int0 SETC CLRC SETC CLRC SETC MAR LAR SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK LAR LAR LAR CNF OVM SXM XF INTM *. initialize WDT registers SPLK #06Fh. Disable WDT. WD_CNTL .#0300h AR1.Assign ADC interrupt vector .Set up one Wait States for I/O space (DAC needs one wait state) MAR *.CKCR0 .SYSCLK=10Mhz SPLK #0002h.CKCR1 SPLK #0081h.AR1 LACC #0004h SACL * OUT *.*+ #0.*+ #0.#0307h .Auxiliary Registers Init .*+ #0. clear WDFLAG.*+ #0.Reset debugging pin .space 16*6 B ADCINT .space 16*38 .*+ #0.CKCR0 .Reset overflow mode .text .*+ #0.Disable watchdog (Vccp=5v)& watchdog counter reset p6-12 LDP #00E0h SPLK #0006Fh.#0300h #0. WD_KEY SPLK #0AAAAh.CPUCLOCK=20Mhz.*+ #0.AR2 AR2.SYSCR LACC SYSSR AND #069FFh SACL SYSSR .

DBTCON SPLK #00125.COMCON SPLK #2800h.CMPR2 SPLK #00125. PBDATDIR PBDATDIR . OCRB #02800h. Vector & Flag reset p11-46 LDP #0E8h Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 26 .COMCON SPLK #8287h.Clear Core Flag Register .T2CON SPLK #0000h.T3CMP SPLK #0000h.EV Mask Setting.no capture enable SPLK #00ffh.T3CNT SPLK #0000h.T2CNT SPLK #0000h.DBTCON SPLK #0000h.T2CMP SPLK #0000h.T1CON SPLK #2840h.CAPCON SPLK #00ffh.PWM Unit setting SPLK #0125.no timer enable SPLK #0000h.Core Mask Setting LDP #0 LACC #022H SACL IMR LACC IFR SACL IFR .T1PER SPLK #0000h.CMPR1 SPLK #00125.CMPR3 SPLK #0287h.no timer features enable SPLK #0000h.T1CNT SPLK #0000h.ACTR SPLK #0000h.GPTCON .COMCON SPLK #0000h.Capture Unit Setting SPLK #0b0fch.CAPFIFO LACC FIFO1 LACC FIFO2 LACC FIFO3 .T1PER .SCMPR3 SPLK #0000h.Clear Fault and no Shut Down .T3CON SPLK #0000h.CMPR2 SPLK #0000h.CAPCON .T3PER SPLK #0000h. OCRA #0070h.Appendix A Sensorless BLDC Drive Control Assembly Code SPLK SPLK SPLK LACC #0000fh.T1CON SPLK #0000h.CMPR3 SPLK #0000h.SCMPR1 SPLK #0000h.SACTR SPLK #0000h.T1CMP SPLK #0000h. Clear EV control registers LDP #0E8h SPLK #0000h.CAPFIFO .CMPR1 SPLK #0000h.T2PER SPLK #0000h.SCMPR2 SPLK #0000h.ADC and Group A Interrupt Core Mask .ACTR SPLK #0508h.T1CON .T1CNT SPLK #0FFFh.

Load Duty Cycle and Set .SPEED_COUNT #0000H.ADCTRL2 SPLK #1b6ah.Is Cleared .NEUTRAL #0000H.ACTR CMPR1 #0FFFH.CUR_COUNT #0000.ASYM #0000H.FLAGCUR #0000.CAPT #0000H.Idc_ref #0.If cleared then stop Clear Fault .OFFSET *.Magnetic Stall Desired Current .ADC Unit setting p3-8 LDP #0E0h SPLK #0003h.FLAGUP #0000H.BCOUNT #0000H.Check if the Magnetic Stall is #0E1h PBDATDIR #010h FAULT_CLEAR #02820h.PBDATDIR #0 COMP #0E8h #03FDh.#0300h .SPEED_REF #00112.Idc_errorK #0300H.STALL #0000H.Check if the Pre Driver Signal .AR2 AR2.B2COUNT #0000H.Stall Function Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 27 .Appendix A Sensorless BLDC Drive Control Assembly Code LACC SACL LACC SACL LACC SACL SPLK SPLK SPLK LACC LACC LACC IFRA IFRA IFRB IFRB IFRC IFRC #0200H.Minimum Duty Cycle FAULT_CLEAR LDP LACC AND BZ SPLK LDP LACC LDP SPLK SACL SPLK SPLK MAGSTALL LDP #0 .V3 #0000H.FLAG #0001H.COMP #0000.CMPR3 .IMRB #7.V1 #0000H.CMPR2 #0FFFH.IMRC IVRA IVRB IVRC .PWM Register for the Magnetic .IMRA #0.Speed Reference .V2 #0000H.ADC 14&5 CLRC LDP SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK SPLK MAR LAR INTM #0 #020H.ADCTRL1 .

If yes then END .Time to update the Duty Cycle? . SPLK #03DFh.Output Current Path: Phase B .Zero already crossed? LDP #0 LACC FLAG .Appendix A Sensorless BLDC Drive Control Assembly Code LACC BZ STALL MAGSTALL .Set next commutation sequence LACC COMP .ACTR CMPR3 #0FFFH.If yes the Call Sequence function .If so then set the ACTR Register LDP #0E8h .Else: Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 28 .ASYM .FLAGCUR SEQUENCE LOOP #0 #4.CAPT .ACTR SACL CMPR2 SPLK #0FFFFH.Trace of the current 60º sector .CMPR2 #0FFFH.Then wait for the next updated Duty Cycle .Non Fed Phase: Phase A RISING1 FALLING3 RISING2 FALLING1 RISING3 *.Commutation glitches filter LDP #0 LACC ASYM ADD #1 SACL ASYM SUB #10 BLEZ END SPLK #10.#0307H * #1 * #0 CAPT #CAPT_DETER .Did BemfA sign already changed? BNZ END .AR3` AR3.CMPR1 LDP SPLK LOOP LDP LACC BZ SPLK CALL B SEQUENCE MAR LAR LACC ADD SACL LDP LACC ADD BACC CAPT_DETER B B B B B FALLING2 LACC LDP SPLK SACL SPLK SPLK COMP #0E8h #0D3FH.Revolution Time Counter #0 FLAGCUR LOOP #0.to commutate the next phase pair.CMPR1 .Terminated .with the new duty cycle? .CMPR3 SPLK #0FFFFH.Which CMPR register should be updated .Input Current Path: Phase C .

Bemf Sign Has Changed LACC BCOUNT .ACC=3*(BemfB + Neutral) SUB NEUTRAL .Bemf zero detection LACC V2.CMPR3 .ACTR CMPR1 #0FFFH.CMPR2 #0FFFH.Bemf zero crossing detection LDP #0 LACC V1.Commutation glitches filter LDP #0 LACC ASYM ADD #1 SACL ASYM SUB #10 BLEZ END SPLK #10.1 ADD V2 .Non Fed Phase Phase A Phase C Phase B .FLAG .ACC=3*(BemfA + Neutral) SUB NEUTRAL .Did bemfB sign already changed? .ACC=3*BemfA SUB OFFSET .Output Current Path .Load Shift Time.CMPR1 .Input Current Path .FLAG .ASYM .Output Current Path .Sign Changed? SPLK #1.Load Shift Time SACL B2COUNT B END FALLING3 LACC LDP SPLK SACL SPLK SPLK COMP #0E8h #03FDH.BemfA Sign has changed LACC BCOUNT .ASYM .Appendix A Sensorless BLDC Drive Control Assembly Code .Commutation glitches filter LDP #0 LACC ASYM ADD #1 SACL ASYM SUB #10 BLEZ END SPLK #10.1 ADD V1 .Zero crossed? LDP #0 LACC FLAG BNZ END .Non Fed Phase Phase C Phase A phase B .Sign Change? SPLK #1.ACTR CMPR3 #0FFFH.Else .ACC=3*BemfA corrected BLZ END .ACC=3*BemfB BGEZ END .Input Current Path .Zero crossed? Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 29 . SACL B2COUNT B END RISING3 LACC LDP SPLK SACL SPLK SPLK COMP #0E8h #0DF3H.If yes then END .CMPR2 #0FFFH.

ACC=3*BemfB corrected BLZ END .Did BemfA sign already changed? .Sign Changed? SPLK #1.Bemf sign has changed LACC BCOUNT .Appendix A Sensorless BLDC Drive Control Assembly Code LDP LACC BNZ #0 FLAG END .Commutation glitches filter LDP #0 LACC ASYM ADD #1 SACL ASYM SUB #10 BLEZ END Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 30 .ACC=3*(BemfB + Neutral) SUB NEUTRAL .Non fed phase Phase A .ACTR CMPR1 #0FFFH.Zero crossed? LDP #0 LACC FLAG BNZ END .FLAG .Sign Changed? SPLK #1.Else: .Bemf zero detection LACC V2.Output Current Path: Phase C .Input Current Path: Phase B .ACC=3*BemfA BGEZ END .Bemf zero detection LACC V1.CMPR1 .Load Shift Time SACL B2COUNT B END RISING1 LACC LDP SPLK SACL SPLK SPLK COMP #0E8h #0F3DH.Commutation glitches filter LDP #0 LACC ASYM ADD #1 SACL ASYM SUB #10 BLEZ END SPLK #10.Output Current Path .CMPR3 .ASYM .If yes then END .ACTR CMPR2 #0FFFH.Else: .1 ADD V1 . Did BemfB sign changed already? .CMPR2 #0FFFH.Input Current Path .ACC=3*BemfB SUB OFFSET .BemfA Sign has Changed LACC BCOUNT .Non fed phase Phase A Phase B Phase C .ACC=3*(BemfA + Neutral) SUB NEUTRAL .Load Shift Time SACL B2COUNT B END RISING2 LACC LDP SPLK SACL SPLK SPLK COMP #0E8h #03DFH.If yes then END .CMPR3 #0FFFH.1 ADD V2 .FLAG .

Load Shift Time SACL B2COUNT B END FALLING1 LACC LDP SPLK SACL SPLK SPLK COMP #0E8h #0FD3H.Else: .Bemf zero detection LDP #0 LACC V3.ACC=3*(BemfC + Neutral) SUB NEUTRAL .ACC=3*(BemfC + Neutral) SUB NEUTRAL .Non fed phase Phase B Phase A Phase C .ACC=3*Bemf3 corrected BLZ END .ACC=3*BemfC BGEZ END .Input Current Path .SPEED_COUNT .ACTR CMPR2 #0FFFH.If yes then END .CMPR1 . Did BemfC sign already changed? .FLAGUP LACC FLAG BNZ END .ACC=3*BemfC SUB OFFSET .Speed error Pointer Init .Speed and speed error calc Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 31 .Sign Changed? SPLK #1.1 ADD V3 .ASYM .Load Shift Time SACL B2COUNT END RET SPEED_REG MAR LAR LDP SPLK *.FLAG .Zero crossed? LDP #0 LACC FLAG BNZ END .AR2 AR2.Sign Changed? SPLK #1.Commutation glitches filter LDP #0 LACC ASYM ADD #1 SACL ASYM SUB #10 BLEZ END SPLK #10.Appendix A Sensorless BLDC Drive Control Assembly Code SPLK #10.BemfC Sign has changed LACC BCOUNT .BemfC Sign has changed LACC BCOUNT .1 ADD V3 .Output Current Path .Zero crossed? LDP #0 SPLK #0.FLAG .Else .If Yes then END .ASYM .#0303h #0 #32.Did BemfC sign already changed? .Speed Error Shifter setting .CMPR3 #0FFFH.Bemf zero detection LDP #0 LACC V3.

Speed error <<5 .Speed error limitation BGEZ POS ABS SPLK #-32.AR1 MAR *+ SST #1.Idc_ref compensation LACC Idc_ref BGEZ RES SPLK #0.16 Idc_ref . *+ SACH *+ SACL * LDP LACC LDP LACC ADD SACL SUB BGZ #0E8H IVRA #0 CUR_COUNT #1 CUR_COUNT #2 CONV SPEED_REF.save ST0 .Acc=1 / (rev. save ST1 .Clear Interrupt Vector . time/ 12) = Speed .Appendix A Sensorless BLDC Drive Control Assembly Code CLRC ZAC OR RPT SUBC AND SETC SUB NEG SXM #0FFFFH #15 BCOUNT #0FFFFH SXM SPEED_REF .Time to start a Conversion? Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 32 .save status registers MAR *.-1024 < Speed error < 1024 * #03FFH OKPOS #03FFH.Acc= Spd ref-Spd Fb= Spd error .Bemf correction computation .SPEED_COUNT .save acc low .Speed LT MPY PAC ADD SACH * SPEED_COUNT * regulation * #Kps Idc_ref.Reset Speed loop timer RES LACC SACH SPLK RET PWMINT .* .save acc high .Idc_ref(k)=Idc_ref(k-1) + K*Speed_error(k) .11 OFFSET #0.SPEED_COUNT POS SACL SUB BLEZ SPLK OKPOS LT MPY PAC SACL .Idc_ref . *+ SST #0. skip one position .

If the first Revolution has not been . make stack pointer active . *LST #1.Clear interrupt vector .high Acc = Idc ADD ADCFIFO2 .If second conv then branch to Vdc .Magnetic stall flag LDP #0 LACC STALL BZ Vdc_or_Idc LACC BNZ SPEEDFLAG Vdc_or_Idc .CUR_COUNT . load ST1 . Performed then . save ST1 .AR1 *+ #1. *+ #0.save acc low . *+ *+ * INTM .If Time then Speed Loop .current error calculation CLRC SXM LACC ADCFIFO1. load ST0 .Branch to Vdc_or_Idc .Restore Acc low .restore status registers MAR *.save acc high . *CLRC RET ADCINT MAR MAR SST SST SACH SACL *.Time to speed loop? LACC SPEED_COUNT SUB #2000 BNZ NO_SPEED_REG CALL SPEED_REG NO_SPEED_REG LACC ADD SACL SPEED_COUNT #1 SPEED_COUNT .Completed then branch to Vdc_or_Idc .If Magnetic Stall is cur. skip one position .Reset CUR_COUNT variable? . save ST0 .10 .Vdc OR Idc? Vdc_or_Idc LDP LACC LDP LACC AND BZ #0E0h SYSIVR #0E0H ADCTRL1 #0002H Vdc .Appendix A Sensorless BLDC Drive Control Assembly Code LDP LACC OR SACL B CONV SUB BLZ SPLK CONTEXT #0E0H ADCTRL1 #02000H ADCTRL1 CONTEXT #2 CONTEXT #0. AR1 LACL *ADDH *LST #0.Restore Acc high .low Acc = V2<<6 Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 33 .

CUR_COUNT COMP #0E8H CMPR1 #0 BCOUNT #1 BCOUNT #0FFFFH SXM RESTO *.BCOUNT #1.Store V2 .Is magnetic stall to the end? .Load first Time Shift .Appendix A Sensorless BLDC Drive Control Assembly Code LDP SACH SACL LACC SACH SETC LACC SUB SACL #0 Idc_errorK V2 V2.5 Idc_ref.current reg output limitation BGZ SUP_LIM SPLK #0.Enable running mode .Release the first revolution indicator flag .Current regulation LT Idc_errorK MPY #Kp PAC ADD COMP.If running mode Branch to SPEEDUP .Else (Magnetic Stall Performing): .AR3 AR3.5 Idc_errorK .0 < Updated Duty cycle < Max duty .SPEEDFLAG RESTO #0112 COMP_OK #0112.COMP .Update speed? SPEEDUP LACC SUB BNZ LACC BNZ MAR LAR SPLK CLRC LACC CAPT #4 RELOAD FLAGUP RELOAD *.AR3 AR3.If yes then .Magnetic Stall Counter Increment .Acc = Kp*Current_error .16 SACH COMP LACC COMP .Output Updated Magnetic Stall Duty Cycle .Time to update speed feedback? .#0307H #0.Store Kp*Current_error + COMP(k-1) .Cancel second conversion start .COMP B COMP_OK SUP_LIM SUB BLZ SPLK COMP_OK LACC BNZ CLRC SPLK LACC LDP SACL LDP LACC ADD SACL SUB SETC BNZ MAR LAR SPLK SPLK SPLK SPLK B STALL SPEEDUP SXM #2.If yes branch to RELOAD .Load updated Duty cycle .Load the revolution time Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 34 .SPEEDFLAG SXM * .Store Idc .STALL #1.Store Current error<<5 .#0307H #0.10 V2 SXM Idc_errorK.Speed feedback already updated? .* #050H.Store V2<<6 .

Zero crossed? LACC FLAG BZ NEU *. AR1 **#0. *#1.Reload Vdc channel RELOAD LDP SPLK #0E0H #1B5Ch.Appendix A Sensorless BLDC Drive Control Assembly Code SPLK RPT SUBC AND SACL SETC SPLK SPLK #012.ASYM . *INTM .Store the new Shift Time .ADC 6&13 .Read Vshunt values LDP #0E0H CLRC SXM LACC ADCFIFO1.Did the Bemf already crossed zero? .* #1.Acc=3*neutral point voltage Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 35 .CAPT OKCAPT SPLK SPLK #0.Acc low = V1<<6 .If Not then Branch to NEU .10 SACH V1 .Is it time to commutate a new phase pair? LACC CAPT .Reset flags for the new Bemf scanning .Divide it by 12 (i.Store V3 .Commutation instant LACC B2COUNT .remainder SACL CAPT . 30º) .Store V1<<6 . load ST0 .Store new shift time counter value SETC SXM BNZ NEU .If yes decrement shift time counter SUB #1 SACL B2COUNT .Speed feedback updated .ADCTRL1 . load ST1 .BCOUNT #15 BCOUNT #0FFFFH BCOUNT SXM #0.e.If yes then upgrade the commutated phases ADD #2 . make stack pointer active .Store the commutated phases remainder SUB #0CH BNZ OKCAPT SPLK #0.restore context RESTO MAR LACL ADDH LST LST CLRC RET Vdc .FLAGUP .Acc high = V3 .FLAG #0.Store V1 .10 ADD ADCFIFO2 LDP #0 SACH V3 SACL V1 LACC V1.Neutral calculation NEU LACC ADD ADD V1 V2 V3 .

*LST #1.ADCTRL1 . load ST0 . make stack pointer active .restore context MAR *.Reload Idc channel LDP #0E0H SPLK #1b6ah.Store 3*neutral point voltage . load ST1 Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 36 .Loaded ADC lines: Idc and V2 .output PWM SPLK #1. *CLRC RET INTM .FLAGCUR . AR1 LACL *ADDH *LST #0.Set flag to let the PWM unit to be updated .Appendix A Sensorless BLDC Drive Control Assembly Code SACL NEUTRAL .

Appendix B Linker File Appendix B Linker File /*-------------------------------------------------------------------------------------------*/ /* LINKER COMMAND FILE .vectors : { } > VECS PAGE 0 . length = 05Fh : origin = 0060h .MEMORY SPECIFICATION for C240 */ /* Last update 24 Sep 96 */ /*------------------------------------------------------------------------------------------*/ MEMORY { PAGE 0 : VECS PROG MMRS B2 B0 B1 : origin = 0h .bss : { } > B2 PAGE 1 .mmrs : { } > MMRS PAGE 1 . length = 0800h : origin = 0h .blk0 : { } > B0 PAGE 1 . length = 040h : origin = 40h .page ? */ */ */ */ Implementation of a Sensorless Speed Controlled Brushless DC drive using TMS320F240 37 .blk1 : { } > B1 PAGE 1 } /* INTERRUPT VECTOR TABLE /* CODE /* Memory Mapped Registers /* Block B0 .text : { } > PROG PAGE 0 .page 0 */ /* Block B1 . length = 0200h /* PROGRAM */ /* Ext mem */ /* MMRS /* DARAM /* DARAM /* DARAM */ */ */ */ PAGE 1 : } /*---------------------------------------------------------------------------------*/ /* SECTIONS ALLOCATION */ /*--------------------------------------------------------------------------------*/ SECTIONS { . length = 020h : origin = 0100h . length = 0200h : origin = 0300h .page 4 */ /* Block B2 .

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