Introduction to CMOS
Logic Circuits
Digital circuit Design : An Overview
Digital IC technologies and logic circuit families
Logic families
Bipolar
– Uses bipolar junction transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls large currents between emitter and collector
– Base currents limit integration density
MOS
 Uses nMOS and pMOS Metal Oxide Semiconductor Field Effect Transistors
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current between
source and drain
– Low power allows very high integration
Transistor Evolution
Transistor –Bardeen et.al. (Bell Labs) in 1947 Bipolar transistor – Shockley in 1949 First bipolar digital logic gate – Harris in 1956 First monolithic IC – Jack Kilby in 1958 First commercial IC logic gates – Fairchild 1960 TTL – 1962 into the 1990’s ECL – 1974 into the 1980’s
MOS Technology Evolution
• MOSFET transistor  Lilienfeld (Canada) in 1925 and
Heil (England) in 1935
• CMOS – 1960’s, but plagued with manufacturing problems (used in watches due to their power limitations)
• PMOS in 1960’s (calculators)
• NMOS in 1970’s (4004, 8080) – for speed
• CMOS in 1980’s – preferred MOSFET technology because of power benefits
• BiCMOS, GalliumArsenide, SiliconGermanium
• SOI, CopperLow K, strained silicon, Highk gate oxide
Bipolar
• TTL (Transistortransistor logic) had been used for many
years .
• ECL (Emitter –Coupled Logic) : basic element is the differential BJT pair.
• BiCMOS : combines the high speed of BJT’s with low
power dissipation of CMOS .
• GaAs : for very high speed due to the high carrier mobility . Has not demonstrated its potential commercially .
CMOS
• Replaced NMOS (much lower power dissipation)
• Small size, ease of fabrication
• Channel length has decreased significantly (as short as 0.06 µm or shorter)
• Low power dissipation than bipolar logic circuits ( can
pack more) .
• High input impedance of MOS transistors can be used to storage charge temporarily (not in bipolar)
• High levels of integration for both logic (chapter 10) and
memory circuits.
• Dynamic logic to further reduce power dissipation and to increase speed performance .
Features to be Considered
• Interface circuits for different families
• Logic flexibility
• Speed
• Complex functions
• Noise immunity
• Temperature
• Power dissipation
• Co$t
Design Abstraction Levels
Ntype and Ptype
MOS Structure
NMOS
L – Distance between the source
and the drain (Channel length)
W – Width of the channel
n+  Silicon doped with higher concentration
p  Silicon substrate doped with
p+  Silicon doped with higher concentration
Introduction to CMOS Logic Circuits
• CMOS stands for Complementary Metal Oxide Semiconductor
– Complementary: there are Ntype and Ptype transistors. Ntype transistors use electrons as the current carriers. Ptype transistors use holes as the current carriers.
• Electrons are free carriers in the conduction band with energy of Ec or just above the conduction band edge. Free electrons are generated by doping the silicon with an Ntype impurity such as phosphorous or arsenic.
• A hole is a current carrier due to the absence of an electron in a covalent bond state, i.e. a missing electron which would otherwise be part of a silicontosilicon bond. Holes are free carriers in the valence band with energy of Ev or just below the valence band edge. Holes are generated by doping the silicon with a Ptype impurity such as boron.
– Metal: the gate of the transistor was made of aluminum metal in the early days, but is made of polysilicon today (for the past 25 years or more).
– Oxide: silicon dioxide is the material between the gate and the channel
– Semiconductor: the semiconductor material is silicon, a type IV element in the periodic chart. Each silicon atom bonds to four other silicon atoms in a tetrahedral
crystal structure.
CMOS NMOS and PMOS Transistors
^{N} ^{c}^{h}^{a}^{n}^{n}^{e}^{l} ^{d}^{e}^{v}^{i}^{c}^{e}
P channel device
• N channel device: built directly in the P substrate with Ndoped source and drain junctions and normally Ndoped gate conductor
– Requires positive voltage applied to gate and drain (with respect to source) for electrons to flow from source to drain (thought of as positive drain current)
• P channel device: built in an Nwell (a deep Ntype junction diffused into the
P substrate) with Pdoped source and drain junctions and N or Pdoped gate
– Requires negative voltage applied to gate and drain (with respect to source) for electrons to flow from drain to source (thought of as negative drain current)
NFET and PFET Devices as Switches
N channel device
source
gate
substrate
drain
NFET device schematic
P channel device
gate
source
substrate
drain
PFET device schematic
• NMOS Device:
– positive voltage (“1” or high) on gate relative to source turns device ON and allows positive current to flow from
drain to source (switch closed)
– zero volts on gate (“0” or low) turns device OFF (open circuit)
– Source (vs drain) is the most negative terminal
• PMOS Device:
– Negative voltage (“0” or low) on gate
relative to source turns device ON and allows (negative) current to flow from drain to source (closes switch)
– Zero volts on gate relative to source
(“1” or high) turns device OFF (closes
switch)
– source (vs drain) is the most positive terminal
3D view of an NMOS
SiO _{2} gate oxide
(good insulator,
_{o}_{x} = 3.9)
Symbols
Vgs = Vg – Vs
Vgd = Vg – Vd
Vds = Vd – Vs = Vgs  Vgd
Operation
Three regions of operation •Cutoff •Linear •Saturation
CutOff Mode
No channel formed
= 0
Operation
Linear Mode
V gs > V t
b
V gd = V gs
V ds = 0
V gs > V gd > V t
0 < V ds < V gs V t
Operation
Saturation Mode
• The voltage drop at the induced channel (from the pinchoff point to the source remains fixed at Vgs – Vt
pMOS Transistor
• Similar, but doping and voltages reversed
– Body tied to high voltage (V _{D}_{D} ) – Gate low: transistor ON – Gate high: transistor OFF
– Bubble indicates inverted behavior
Power Supply Voltage
• GND = 0 V
• In 1980’s, V _{D}_{D} = 5V
• V _{D}_{D} has decreased in modern processes
– High V _{D}_{D} would damage modern tiny transistors – Lower V _{D}_{D} saves power
• V _{D}_{D} = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
Transistors as Switches
• We can view MOS transistors as electrically controlled
switches
• Voltage at gate controls path from source to drain
d
nMOS 
g 

s 

d 

pMOS 
g 

s
g = 0
d
s
g = 1
d
ON
s
d
OFF
s
MOS Transistors
Voltagecontrolled resistance
PMOS
NMOS
MOSFET as Switches

MOSFET: MetalOxideSemiconductor FieldEffect Transistor 

nFET: an nchannel MOSFET that uses negatively charged electrons for electrical current flow 

pFET: a pchannel MOSFET that uses positive charges for current flow 

In many ways, MOSFETs behave like the idealized switches introduced in the previous section 

The voltage applied to the gate determines the 
current flow between the source and drain terminals
(a) nFET symbol
(b) pFET symbol
Figure 1 Symbols used
for nFETs and pFETs
MOSFET as Switches
Early generations of silicon MOS logic circuits used both positive and negative supply voltages as Figure 2 showing
In modern designs require only a single positive voltage V _{D}_{D} and the ground connection, e.g. V _{D}_{D} = 5 V and 3.3 V or lower
The relationship between logic variables x and it’s voltages V _{x}
0
DD
(1)
(2)
Figure 2 Dual power supply voltages
(a) Power supply connection (b) Logic definitions
Figure 3 Single voltage power supply
Switching Characteristics of MOSFET
In general,
Low voltages correspond to logic 0 values
High voltages correspond to logic 1 values
»
The transition region between the highest logic 0 voltage and the lowest logic 1 voltage is undefined
nFET
y 
x A which is valid iff A
1

pFET 

y 
x A which is valid iff A
0

(3)
(4)
(a) Open
(b) Closed
Figure 4 nFET switching characteristics
_{(}_{a}_{)} _{O}_{p}_{e}_{n}
(b) Closed
Figure 5 pFET switching characteristics
nMOS FET Threshold Voltages
An nFET is characterized by a threshold voltage V _{T}_{n} that is positive, typical is around V _{T}_{n} = 0.5 V to 0.7 V
V
Tn
If , then the transistor acts like an open (off) circuit and there is no current flow between
the drain and source
, then the nFET drain and source are
connected and the equivalent switch is closed (on)
V
GSn
V
Tn
If
V
GSn
Thus, to define the voltage V _{A} that is associated with the binary variable A
V
A
V
GSn
(5)
(a) Gatesource voltage
(b) Logic translation
Figure 6 Threshold voltage of an nFET
pMOS FET Threshold Voltages
An pFET is characterized by a threshold voltage V _{T}_{p} that is negative, typical is around V _{T}_{p} = –0.5 V to –0.8 V
» If
V SGp
V Tp
, then the transistor acts like an open (off)
switch and there is no current flow between the drain
and source
» If
V SGp
V Tp
, then the pFET drain and source are
connected and the equivalent switch is closed (on)
Thus, to the applied voltage V _{A} we first sum voltage to write
V V
V
DD
V
A
SGp
DD
V
V
SGp
(6)
(7)
(9)
V DD
V
Tp
(8)
Note that the transition between a logic 0 and a logic 1 is at (8) !
(a) Sourcegate voltage
(b) Logic translation
Figure 7 pFET threshold voltage
nFET Pass Characteristics
An ideal electrical switch can pass any voltage applied to it
As Figure 8 (b), the output voltage V _{y} is reduced to a value
V
1
V
DD
Tn
(10)
since
V
GSn
V
Tn
Which is less than the input voltage VDD, called threshold voltage loss
Thus, we say that the nFET can only pass a weak logic 1; in other word, the nFET is said to pass a strong logic 0 can pass a voltage in the range [0, V _{1} ]
»
(a) Logic 0 transfer
(b) Logic 1 transfer
Figure 8 nFET pass characteristics
Static CMOS Circuit
At every point in time (except during the switching transients) each gate output is connected to either V _{D}_{D} or V _{s}_{s} via a lowresistive path.
The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).
This is in contrast to the
relies on temporary storage of signal values on the
dynamic
circuit class, which
capacitance of high impedance circuit nodes.
Static CMOS
In1
In2
In3
In 1
In 2
In 3
V DD
PUN
PDN
V SS
PMOS Only
F = G
NMOS Only
PUN and PDN are Dual Networks
Simple CMOS Circuits: The Inverter Gate
Inverter
Schematic
Vdd


PMOS 

source 


PMOS 



PMOS drain 



Vout 



NMOS drain NMOS 






NMOS source 
Gnd
Inverter Symbol
• The simplest complementary MOS (CMOS) circuit is the inverter:
– NMOS & PMOS gates are connected together as the
input
– NMOS & PMOS drains are connected together as the output
– NMOS & PMOS sources are connected to Gnd and Vdd, respectively.
– NMOS substrate is normally connected to Gnd for all
NMOS devices in the circuit
– PMOS well is normally connected to Vdd (most positive voltage in circuit) for all PMOS devices
• Operation:
– If Vin is down (0 volts), NMOS is OFF and PMOS is
ON pulling Vout to Vdd (high = 1)
– If Vin is up (at Vdd), NMOS is ON hard and PMOS is OFF pulling Vout low to Gnd (“0”)
– With Vin at 0 or Vdd, no dc current flows in inverter
CMOS Inverter
CMOS Inverter
A 
Y 
0 

1 
0 
A
Y
A=1
V DD
OFF
Y=0
ON
GND
CMOS Inverter
V DD
ON
Y=1
OFF
GND
Series connected MOSFETS
Parallel Connected MOSFETS
Series and Parallel
nMOS: 1 = ON
pMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON
a
g1 


g2 

b 

(a) 

a 

g1 


g2 

b 

(b) 

a 

g1 g2 

b 

(c) 

a 

g1 g2 

b 

(d) 
a a a 
a 

0 
b b 0 1 1 0 b 
1 

0 
1 
b 

OFF OFF OFF 
ON 

a a a 
a 

0 
b b 0 1 1 0 b 
1 
b 
0 
1 

ON OFF OFF 
OFF 

a a a 
a 
0
b
0
OFF
0
a
0
0 

1 
1 

0 
1 

1 

b 
b 
b 

ON 
ON 
ON 

a 
a 
a 

0 

1 
1 

0 
1 

1 
b 
b 
b 
b 
ON 
ON 
ON 
OFF 
Pullup / Pulldown Model
• Typical CMOS gate can be viewed as
consisting of two parts
– pullup network and pulldown network
A
B
C
A
B
C
^{V} DD
Pullup / Pulldown Model
• High level inputs to the PDN cause switches to close
• If there is a closed switch path thru
PDN, then output is low
• Low level inputs to the PUN cause switches to close
• If there is a closed switch path thru
PUN, then output is high
CMOS NAND Gate
A 
B 
Y 
0 
0 

0 
1 

1 
0 

1 
1 
A
B
Y
CMOS NAND Gate
A 
B 
Y 
0 
0 
1 
0 
1 

1 
0 

1 
1 
OFF
OFF
Y=1
CMOS NAND Gate
A 
B 
Y 
0 
0 
1 
0 
1 
1 
1 
0 

1 
1 
OFF
Y=1
CMOS NAND Gate
A 
B 
Y 
0 
0 
1 
0 
1 
1 
1 
0 
1 
1 
1 
OFF
Y=1
OFF
CMOS NAND Gate
A 
B 
Y 
0 
0 
1 
0 
1 
1 
1 
0 
1 
1 
1 
0 
OFF
Y=0
CMOS NOR Gate
A 
B 
Y 
0 
0 
1 
0 
1 
0 
1 
0 
0 
1 
1 
0 
A
B
Y
3input NAND Gate
• Y pulls low if ALL inputs are 1
• Y pulls high if ANY input is 0
3input NAND Gate
• Y pulls low if ALL inputs are 1
• Y pulls high if ANY input is 0
A
B
C
Y
Logic Identities
Logic Analysis Inverter
Logic Analysis –NAND Gate
Logic Analysis –NOR Gate
Pullup / Pulldown Model
GND
Pullup / Pulldown Model
What happens when the Boolean expression is false?
Since there is no path thru PDN, the output could float.
In order to make the output high, the PUN must have a path which connects V _{D}_{D} to the output.
Observe: take the expression for PDN and use DeMorgans Law to write
it in terms of complemented input variables. Complemented variables are true when the input level is low. Thus, this gives exactly the form of the PUN
In this case:
not A or
( not B and not C)
B
C
Vdd
A
Example Gate: COMPLEX CMOS GATE
OUT = D + A• (B+C)
Example Gate: COMPLEX CMOS GATE
A
D
V DD
OUT = D + A• (B+C)
A
D
V DD
OUT = D + A• (B+C)
Examples of pulldown networks
Examples of pullup networks
A
B
C
V DD
PMOSs
Out
NMOSs
GND
Stick Diagram, Interconnected
83
^{V}
DD
GND
^{V}
DD
GND
Line of diffusion layout – abutting sourcedrain connections
Note crossover eliminated by A B C ordering
• Example:
x y + x z + x v
• 5 operations:
• 1 AND, 2 OR
• # txs =
?
=
x (y + z + v)
3 operations:
3 AND, 2 OR
# txs =
?
Construct a CMOS logic gate to
implement the function:
F = a • (b + c)
14 transistors (cascaded gates)
Construct a CMOS logic gate to
implement the function:
F = a • (b + c)
Complex gates in CMOS logic
• A complex logic gate is one that implements a function that can provide the basic NOT, AND and OR operation
but integrates them into a single circuit.
• CMOS is ideally suited for creating gates that have logic equations by exhibiting the following,
• 1) ANDORINVERT
• 2) ORANDINVERT
• An AOI logic equation is equivalent to a complemented SOP from, while an AOI equation is equivalent to a complemented POS structure.
• In CMOS, output always produces NOT operation acting on input variable
AOI form

 OAI form
AOI Logic Function (OR) Design of XOR gate using CMOS logic.
• ANDORINVERT logic function(AOI)
implements operation in the order
AND,OR,NOT. For example ,
• Let us consider the function Y = AB+CD i.e., Y = NOT((A AND B)OR (C AND D))
The AOI logic gate
implementation for Y
CMOS implementation for Y
• Step 1: Draw A.B (AND) function first
by connecting 2 nMOS transistors in
series.
Step 2: Draw C.D implementation, by using 2
nMOS transistors in series.
Step 3:
Y = A.B+C.D , In this function A.B and C.D are added, for addition , we have to draw parallel connection. So, A.B series connected in parallel with C.D as shown in figure.
Step 4: Draw pMOS connection,
I. In nMOS A,B connected in series. So, in pMOS side, A.B should be connected in parallel.
II. In nMOS C,D connected in series. So, in pMOS side,
C.D should be connected inparallel. III. A.B and C.D networks are connected in parallel in nMOS side. So, in pMOS side, A.B and C.D networks should be connected in series.
IV. In pMOS multiplication should be drawn in parallel, then
addition should be drawn in series as shown in figure.
Step 5: Take output at the point in between nMOS
and pMOS networks.
CMOS implementation for Y
Example: x = ab+cd
OAI Logic Function (OR) Design of XNOR
gate using CMOS logic.
• ORANDINVERT logic function(AOI)
implements operation in the order
OR,AND,NOT. For example ,
• Let us consider the function Y = (A+B).(C+D) i.e., Y = NOT((A OR B)AND (C OR D))
CMOS implementation for Y
OAI22 Logic Graph
Structured Logic Design (1/4)
CMOS logic gates are intrinsically inverting
» Output always produces a NOT operation acting on the input variables
Figure 2.42 Origin of the inverting characteristic of CMOS gates
Structured Logic Design (2/4)
(a) Seriesconnected nFETs
(b) Parallelconnected nFETs
Figure 2.43 nFET logic formation
Figure 2.44 nFET AOI circuit
Figure 2.45 nFET OAI circuit
Structured Logic Design (3/4)
(a) Parallelconnected pFETs
^{(}^{b}^{)} ^{S}^{e}^{r}^{i}^{e}^{s}^{}^{c}^{o}^{n}^{n}^{e}^{c}^{t}^{e}^{d} ^{p}^{F}^{E}^{T}^{s}
Figure 2.46 pFET logic formation
(a) pFET AOI circuit
(b) pFET OAI circuit
Figure 2.47 pFET arrays for AOI and OAI gates
Structured Logic Design (4/4)
(a) AOI circuit
(b) OAI circuit
Figure 2.48 Complete CMOS AOI and OAI circuits
Bubble Pushing
(a)
Parallelconnected pFETs
(b)
Seriesconnected pFETs
Figure 2.51 Assertlow models for pFETs
(a) NAND  OR
(b) NOR  AND
Figure 2.52 Bubble pushing using DeMorgan rules
XOR and XNOR gates
XOR and XNOR Gates
An important example of using an AOI circuit is constructing ExclusiveOR (XOR) and ExclusiveNOR circuits
Figure 2.56 XOR
(2.71)
(2.72)
(2.73)
(2.74)
(a) ExclusiveOR
(b) ExclusiveNOR
Figure 2.57 AOI XOR and XNOR gates
(a) AOI22
(b) AOI321
(c) AOI221
Figure 2.58 General naming convention
logic cascade in cmos
HalfAdder
Truth Table
x y 
C S 

0 0 
0 
0 

0 1 
0 1 

1 0 
0 1 

1 1 
1 0 
Logic Equations
C = x • y
S = x
y
Schematic
Full Adder
• Adding two singlebit binary values, X, Y with a carry input bit Cin produces a sum bit S and a carry out Cout bit.
Full Adder Truth Table
_{I}_{n}_{p}_{u}_{t}_{s}
Outputs
X 
Y 
Cin 
S 
Cout 
0 
0 
0 
0 
0 
0 
0 
1 
1 
0 
0 
1 
0 
1 
0 
0 
1 
1 
0 
1 
1 
0 
0 
1 
0 
1 
0 
1 
0 
1 
1 
1 
0 
0 
1 
1 
1 
1 
1 
1 
S(X,Y, Cin) =
Cout(x, y, Cin) =
(1,2,4,7)
(3,5,6,7)
Sum S
X
Cin
0
00
01
0
2 6
1
4
1
1
1
3
7
1
5
1
Cin
Y
Cin
Y
Cout = XY + X(Cin) + Y(Cin)
Addition of Binary Numbers
Full Adder. The full adder is the fundamental building block of
most arithmetic circuits:
^{C} out
^{C} in
s i
The sum and carry outputs are described as:
c
i
s
i
abc
i
i
i
abc
i
i
i
abc
i
i
i
abc
i
i
i
abc
i
i
i
a bc
i
i
i
ab c
i
i
i
abc
i
i
i
ab
i
i
ac
i
i
i
bc
i
Full Adder Circuit Using ANDOR
Y
Cin
S
Sum S
X
Y
X
Cin
Y
Cin
Cout
Cont
Addition of Binary Numbers
Propagate
Generate
Propagate
Generate
PGK
For a full adder, define what happens to carries
» Generate: C _{o}_{u}_{t} = 1 independent of C
G = A • B
» Propagate: C _{o}_{u}_{t} = C
P = A
» Kill: C _{o}_{u}_{t} = 0 independent of C
K = ~A • ~B
FullAdder Implementation
Full Adder operations is defined by equations:
abc
i
i
i
p
g
i
i
abc
i
i
i
g
p
i
abc
i
i
i
abc
i
i
i
i
i
s
i
a i
b i
abc
i
i
i
abc
i
i
i
ab
i
i
c
i
pc
i
CarryPropagate:
and CarryGenerate
Onebit adder could be
implemented as shown
s i
c in
HighSpeed Addition
c
i
g
i
p c
i
i
^{a} i
^{b} i
i
b
^{s} i
g
i
i
^{c} out
Onebit adder could be implemented more efficiently because MUX is faster
p
i
Multiplexers
2:1 multiplexer chooses between two inputs
S 
D1 
D0 
Y 

0 
X 
0 
D0 

0 
X 
1 
D1 

1 
0 
X 

1 
1 
X 
S
Multiplexers
2:1 multiplexer chooses between two inputs
S 
D1 
D0 
Y 

0 
X 
0 
0 
D0 
0 
X 
1 
1 
D1 
1 
0 
X 
0 

1 
1 
X 
1 
S
GateLevel Mux Design
Y
How many transistors are needed?
GateLevel Mux Design
Y
How many transistors are needed? 20
D1
S
D0
D1
S
D0
Y
Y
Inverting Mux
Inverting multiplexer
» Use compound AOI22
» Or pair of tristate inverters
» Essentially the same thing
Noninverting multiplexer adds an inverter
Y
D0
D1
S
Tristate Inverter
Tristate inverter produces restored output
» Violates conduction complement rule
» Because we want a Z output
Y
Tristate Inverter
Tristate inverter produces restored output
» Violates conduction complement rule
» Because we want a Z output
Y
A
EN = 0 
EN = 1 
Y = 'Z' 
Y = A 
Y D0
D1
S
Inverting Mux
Inverting multiplexer
» Use compound AOI22
» Or pair of tristate inverters
» Essentially the same thing
Noninverting multiplexer adds an inverter
D0
Y
Y
D0
D1
S
Complimentary Static CMOS Full Adder
A
V DD
28 Transistors
V DD
S
A Better Structure: The Mirror Adder
"0"Propagate
"1"Propagate
S
24 transistors
and 2 inverter Total 24+4 =28 Transistors
Mirror Adder
Stick Diagram
139
OAI/AOI
duality
Review: Construction of PDN
• NMOS devices in series implement a NAND function
• NMOS devices in parallel implement a NOR function
A
A + B
• Scale both W and L
• – no effective change in W/L
• – increases gate capacitance
• Series Transistors
• – increases effective L
• Parallel Transistors
• increases effective W
Analysis of CMOS gates
Represent “on” transistors as resistors
• Transistors in series → resistances in series
• Effective resistance = 2R
• Effective width = ½ W
Analysis of CMOS gates, cont
• Represent “on” transistors as resistors
0
• Transistors in parallel → resistances in parallel
• Effective resistance = ½ R
• Effective width = 2W
CMOS gate design
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