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Introduction to CMOS Logic Circuits
Introduction to CMOS Logic Circuits

Introduction to CMOS

Logic Circuits

Introduction to CMOS Logic Circuits

Digital circuit Design : An Overview

Digital circuit Design : An Overview Digital IC technologies and logic circuit families
Digital circuit Design : An Overview Digital IC technologies and logic circuit families

Digital IC technologies and logic circuit families

Logic families

Logic families Bipolar – Uses bipolar junction transistors – npn or pnp silicon structure – Small
Logic families Bipolar – Uses bipolar junction transistors – npn or pnp silicon structure – Small

Bipolar

Uses bipolar junction transistors

npn or pnp silicon structure

Small current into very thin base layer controls large currents between emitter and collector

Base currents limit integration density

MOS

- Uses nMOS and pMOS Metal Oxide Semiconductor Field Effect Transistors

nMOS and pMOS MOSFETS

Voltage applied to insulated gate controls current between

source and drain

Low power allows very high integration

Transistor Evolution

Transistor Evolution  Transistor – Bardeen et.al. (Bell Labs) in 1947  Bipolar transistor – Shockley

Transistor Bardeen et.al. (Bell Labs) in 1947 Bipolar transistor Shockley in 1949 First bipolar digital logic gate Harris in 1956 First monolithic IC Jack Kilby in 1958 First commercial IC logic gates Fairchild 1960 TTL 1962 into the 1990’s ECL 1974 into the 1980’s

MOS Technology Evolution

MOS Technology Evolution • MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935
MOS Technology Evolution • MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935

MOSFET transistor - Lilienfeld (Canada) in 1925 and

Heil (England) in 1935

CMOS – 1960’s, but plagued with manufacturing problems (used in watches due to their power limitations)

• PMOS in 1960’s (calculators)

• NMOS in 1970’s (4004, 8080) – for speed

• CMOS in 1980’s – preferred MOSFET technology because of power benefits

BiCMOS, Gallium-Arsenide, Silicon-Germanium

SOI, Copper-Low K, strained silicon, High-k gate oxide

Bipolar

Bipolar • TTL (Transistor-transistor logic) had been used for many years . • ECL (Emitter –

TTL (Transistor-transistor logic) had been used for many

years .

ECL (Emitter Coupled Logic) : basic element is the differential BJT pair.

BiCMOS : combines the high speed of BJT’s with low

power dissipation of CMOS .

GaAs : for very high speed due to the high carrier mobility . Has not demonstrated its potential commercially .

CMOS

CMOS • Replaced NMOS (much lower power dissipation) • Small size, ease of fabrication • Channel
CMOS • Replaced NMOS (much lower power dissipation) • Small size, ease of fabrication • Channel

Replaced NMOS (much lower power dissipation)

Small size, ease of fabrication

Channel length has decreased significantly (as short as 0.06 µm or shorter)

Low power dissipation than bipolar logic circuits ( can

pack more) .

High input impedance of MOS transistors can be used to storage charge temporarily (not in bipolar)

High levels of integration for both logic (chapter 10) and

memory circuits.

Dynamic logic to further reduce power dissipation and to increase speed performance .

Features to be Considered

Features to be Considered • Interface circuits for different families • Logic flexibility • Speed •

Interface circuits for different families

Logic flexibility

Speed

Complex functions

Noise immunity

Temperature

Power dissipation

Co$t

Design Abstraction Levels

Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT DEVICE G D S n+ n+
Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT DEVICE G D S n+ n+
SYSTEM MODULE + GATE CIRCUIT DEVICE G D S n+ n+
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
D
S
n+
n+

N-type and P-type

N-type and P-type
N-type and P-type
N-type and P-type

MOS Structure

MOS Structure NMOS Channel L – Distance between the source and the drain (Channel length) W

NMOS

Channel
Channel

L Distance between the source

and the drain (Channel length)

W Width of the channel

n+ - Silicon doped with higher concentration

p - Silicon substrate doped with

p+ - Silicon doped with higher concentration

Introduction to CMOS Logic Circuits

Introduction to CMOS Logic Circuits • CMOS stands for Complementary Metal Oxide Semiconductor – Complementary :

CMOS stands for Complementary Metal Oxide Semiconductor

Complementary: there are N-type and P-type transistors. N-type transistors use electrons as the current carriers. P-type transistors use holes as the current carriers.

Electrons are free carriers in the conduction band with energy of Ec or just above the conduction band edge. Free electrons are generated by doping the silicon with an N-type impurity such as phosphorous or arsenic.

A hole is a current carrier due to the absence of an electron in a covalent bond state, i.e. a missing electron which would otherwise be part of a silicon-to-silicon bond. Holes are free carriers in the valence band with energy of Ev or just below the valence band edge. Holes are generated by doping the silicon with a P-type impurity such as boron.

Metal: the gate of the transistor was made of aluminum metal in the early days, but is made of polysilicon today (for the past 25 years or more).

Oxide: silicon dioxide is the material between the gate and the channel

Semiconductor: the semiconductor material is silicon, a type IV element in the periodic chart. Each silicon atom bonds to four other silicon atoms in a tetrahedral

crystal structure.

CMOS NMOS and PMOS Transistors

CMOS NMOS and PMOS Transistors oxide gate N + N N+ source P substrate drain N
oxide gate N + N N+ source P substrate drain
oxide
gate
N +
N N+
source
P substrate
drain

N channel device

oxide gate P+ P+ source N well drain
oxide
gate
P+
P+
source
N well
drain

P channel device

N channel device: built directly in the P substrate with N-doped source and drain junctions and normally N-doped gate conductor

Requires positive voltage applied to gate and drain (with respect to source) for electrons to flow from source to drain (thought of as positive drain current)

P channel device: built in an N-well (a deep N-type junction diffused into the

P substrate) with P-doped source and drain junctions and N or P-doped gate

Requires negative voltage applied to gate and drain (with respect to source) for electrons to flow from drain to source (thought of as negative drain current)

N-FET and P-FET Devices as Switches

N-FET and P-FET Devices as Switches oxide gate N + N N+ P substrate drain source
oxide gate N + N N+ P substrate drain source
oxide
gate
N +
N
N+
P substrate
drain
source

N channel device

source

gate

N+ P substrate drain source N channel device source gate substrate drain N-FET device schematic oxide
N+ P substrate drain source N channel device source gate substrate drain N-FET device schematic oxide
N+ P substrate drain source N channel device source gate substrate drain N-FET device schematic oxide
N+ P substrate drain source N channel device source gate substrate drain N-FET device schematic oxide
N+ P substrate drain source N channel device source gate substrate drain N-FET device schematic oxide

substrate

drain

N-FET device schematic

oxide gate P+ P+ source N well drain
oxide
gate
P+
P+
source
N well
drain

P channel device

gate

gate P+ P+ source N well drain P channel device gate source substrate drain P-FET device
gate P+ P+ source N well drain P channel device gate source substrate drain P-FET device
gate P+ P+ source N well drain P channel device gate source substrate drain P-FET device
gate P+ P+ source N well drain P channel device gate source substrate drain P-FET device
gate P+ P+ source N well drain P channel device gate source substrate drain P-FET device

source

substrate

drain

P-FET device schematic

NMOS Device:

– positive voltage (“1” or high) on gate relative to source turns device ON and allows positive current to flow from

drain to source (switch closed)

– zero volts on gate (“0” or low) turns device OFF (open circuit)

Source (vs drain) is the most negative terminal

PMOS Device:

– Negative voltage (“0” or low) on gate

relative to source turns device ON and allows (negative) current to flow from drain to source (closes switch)

Zero volts on gate relative to source

(“1” or high) turns device OFF (closes

switch)

source (vs drain) is the most positive terminal

3-D view of an NMOS

3-D view of an NMOS polysilicon gate W t ox L n+ n+ p-type body SiO
3-D view of an NMOS polysilicon gate W t ox L n+ n+ p-type body SiO
polysilicon gate W t ox L n+ n+ p-type body
polysilicon
gate
W
t
ox
L
n+
n+
p-type body

SiO 2 gate oxide

view of an NMOS polysilicon gate W t ox L n+ n+ p-type body SiO 2

(good insulator,

ox = 3.9)

Symbols

Symbols NMOS V g + + V gs V gd - - V s V d
NMOS V g + + V gs V gd - - V s V d
NMOS
V
g
+
+
V
gs
V
gd
-
-
V s
V d
-
+
V
ds

Vgs = Vg Vs

Vgd = Vg Vd

Vds = Vd Vs = Vgs - Vgd

Operation

Operation Three regions of operation • Cutoff • Linear • Saturation Cut-Off Mode No channel formed

Three regions of operation Cutoff Linear Saturation

Cut-Off Mode

No channel formed

V gs = 0 V gd g + + - - s d n+ n+
V gs = 0
V
gd
g
+
+
-
-
s
d
n+
n+
p-type body
b

= 0

Operation

Operation Linear Mode V gs > V t g + + - - s d n+

Linear Mode

V gs > V t

g + + - - s d n+ n+ p-type body
g
+
+
-
-
s
d
n+
n+
p-type body

b

V gd = V gs

t g + + - - s d n+ n+ p-type body b V gd =

V ds = 0

- - s d n+ n+ p-type body b V gd = V gs V ds
- - s d n+ n+ p-type body b V gd = V gs V ds
- - s d n+ n+ p-type body b V gd = V gs V ds
V gs > V t g + + - - I ds s d n+
V gs > V t
g
+
+
-
-
I
ds
s
d
n+
n+
p-type body
b
V t g + + - - I ds s d n+ n+ p-type body b

V gs > V gd > V t

0 < V ds < V gs -V t

Operation

Operation Saturation Mode V gs > V t V gd < V t g + +

Saturation Mode

Operation Saturation Mode V gs > V t V gd < V t g + +
V gs > V t V gd < V t g + + - -
V gs > V t
V gd < V t
g
+
+
-
-
I
s
d
ds
n+
n+
V ds > V gs -V t
p-type body
b

The voltage drop at the induced channel (from the pinch-off point to the source remains fixed at Vgs Vt

pMOS Transistor

pMOS Transistor • Similar, but doping and voltages reversed – Body tied to high voltage (V

Similar, but doping and voltages reversed

Body tied to high voltage (V DD ) Gate low: transistor ON Gate high: transistor OFF

Bubble indicates inverted behavior

Source Gate Drain Polysilicon SiO 2 p+ p+ n bulk Si
Source
Gate
Drain
Polysilicon
SiO 2
p+
p+
n
bulk Si

Power Supply Voltage

Power Supply Voltage • GND = 0 V • In 1980 ’s, V D D =

GND = 0 V

In 1980’s, V DD = 5V

V DD has decreased in modern processes

High V DD would damage modern tiny transistors Lower V DD saves power

V DD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

Transistors as Switches

Transistors as Switches • We can view MOS transistors as electrically controlled switches • Voltage at

We can view MOS transistors as electrically controlled

switches

Voltage at gate controls path from source to drain

d

nMOS

g

nMOS g
 

s

d

pMOS

g

pMOS g

s

g = 0

d

OFF s d ON
OFF
s
d
ON

s

g = 1

d

ONpath from source to drain d nMOS g   s d pMOS g s g =

s

d

OFFcontrols path from source to drain d nMOS g   s d pMOS g s g

s

MOS Transistors

MOS Transistors Voltage-controlled resistance PMOS NMOS
MOS Transistors Voltage-controlled resistance PMOS NMOS

Voltage-controlled resistance

PMOS

MOS Transistors Voltage-controlled resistance PMOS NMOS

NMOS

MOS Transistors Voltage-controlled resistance PMOS NMOS

MOSFET as Switches

MOSFET as Switches  MOSFET: M etal- O xide- S emiconductor F ield- E ffect T

MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor

nFET: an n-channel MOSFET that uses negatively charged electrons for electrical current flow

pFET: a p-channel MOSFET that uses positive charges for current flow

In many ways, MOSFETs behave like the idealized switches introduced in the previous section

The voltage applied to the gate determines the

current flow between the source and drain terminals

the current flow between the source and drain terminals (a) nFET symbol (b) pFET symbol Figure

(a) nFET symbol

flow between the source and drain terminals (a) nFET symbol (b) pFET symbol Figure 1 Symbols

(b) pFET symbol

Figure 1 Symbols used

for nFETs and pFETs

MOSFET as Switches

MOSFET as Switches  Early generations of silicon MOS logic circuits used both positive and negative

Early generations of silicon MOS logic circuits used both positive and negative supply voltages as Figure 2 showing

In modern designs require only a single positive voltage V DD and the ground connection, e.g. V DD = 5 V and 3.3 V or lower

The relationship between logic variables x and it’s voltages V x

0

V x
V
x
V
V

DD

x x x 1 0 means means that that V V x
x
x
x
1 0 means means that that V V
x
V V 0 DD
V
V 0
DD

(1)

(2)

x x x 1 0 means means that that V V x V V 0 DD

Figure 2 Dual power supply voltages

V x V V 0 DD (1) (2) Figure 2 Dual power supply voltages (a) Power
V x V V 0 DD (1) (2) Figure 2 Dual power supply voltages (a) Power

(a) Power supply connection (b) Logic definitions

Figure 3 Single voltage power supply

Switching Characteristics of MOSFET

Switching Characteristics of MOSFET  In general, Low voltages correspond to logic 0 values  High

In general,

Low voltages correspond to logic 0 values

High voltages correspond to logic 1 values

»

The transition region between the highest logic 0 voltage and the lowest logic 1 voltage is undefined

nFET

y

x A which is valid iff A 1
x A which is valid iff A 1

x A which is valid iff A

1
1

pFET

y

x A which is valid iff A 0
x A which is valid iff A 0

x A which is valid iff A

0
0

(3)

(4)

 pFET y x A which is valid iff A 0 (3) (4) (a) Open (b)

(a) Open

pFET y x A which is valid iff A 0 (3) (4) (a) Open (b) Closed

(b) Closed

Figure 4 nFET switching characteristics

(a) Open (b) Closed Figure 4 nFET switching characteristics ( a ) O p e n

(a) Open

Closed Figure 4 nFET switching characteristics ( a ) O p e n (b) Closed Figure

(b) Closed

Figure 5 pFET switching characteristics

nMOS FET Threshold Voltages

nMOS FET Threshold Voltages  An nFET is characterized by a threshold voltage V T n

An nFET is characterized by a threshold voltage V Tn that is positive, typical is around V Tn = 0.5 V to 0.7 V

is positive, typical is around V T n = 0.5 V to 0.7 V V Tn

V

Tn

If , then the transistor acts like an open (off) circuit and there is no current flow between

the drain and source

, then the nFET drain and source are

connected and the equivalent switch is closed (on)

V

GSn

and the equivalent switch is closed ( on ) V  GSn V Tn  If

V

Tn

If

V

GSn

Thus, to define the voltage V A that is associated with the binary variable A

V

A

V A that is associated with the binary variable A V A V GSn (5) (a)

V

GSn

(5)

is associated with the binary variable A V A V GSn (5) (a) Gate-source voltage (b)

(a) Gate-source voltage

the binary variable A V A V GSn (5) (a) Gate-source voltage (b) Logic translation Figure

(b) Logic translation

Figure 6 Threshold voltage of an nFET

pMOS FET Threshold Voltages

pMOS FET Threshold Voltages  An pFET is characterized by a threshold voltage V T p

An pFET is characterized by a threshold voltage V Tp that is negative, typical is around V Tp = 0.5 V to 0.8 V

» If

V SGp

around V T p = – 0.5 V to – 0.8 V » If V SGp

V Tp

, then the transistor acts like an open (off)

switch and there is no current flow between the drain

and source

» If

V SGp

no current flow between the drain and source » If V SGp V Tp , then

V Tp

, then the pFET drain and source are

connected and the equivalent switch is closed (on)

Thus, to the applied voltage V A we first sum voltage to write

the applied voltage V A we first sum voltage to write V V V DD V

V V

applied voltage V A we first sum voltage to write V V V DD V A

V

DD

V

A

SGp

DD

A
A
V A we first sum voltage to write V V V DD V A SGp DD

V

A we first sum voltage to write V V V DD V A SGp DD A

V

SGp

(6)

(7)

(9)sum voltage to write V V V DD V A SGp DD A V V SGp

voltage to write V V V DD V A SGp DD A V V SGp (6)

V DD

V

Tp

(8)

Note that the transition between a logic 0 and a logic 1 is at (8) !

the transition between a logic 0 and a logic 1 is at (8) ! (a) Source-gate

(a) Source-gate voltage

between a logic 0 and a logic 1 is at (8) ! (a) Source-gate voltage (b)

(b) Logic translation

Figure 7 pFET threshold voltage

nFET Pass Characteristics

nFET Pass Characteristics  An ideal electrical switch can pass any voltage applied to it 

An ideal electrical switch can pass any voltage applied to it

As Figure 8 (b), the output voltage V y is reduced to a value

V

1

8 (b), the output voltage V y is reduced to a value V 1 V DD

V

DD

V
V

Tn

(10)

since

V

GSn

V y is reduced to a value V 1 V DD V Tn (10) since V

V

Tn

Which is less than the input voltage VDD, called threshold voltage loss

Thus, we say that the nFET can only pass a weak logic 1; in other word, the nFET is said to pass a strong logic 0 can pass a voltage in the range [0, V 1 ]

»

0  can pass a voltage in the range [0, V 1 ] » (a) Logic

(a) Logic 0 transfer

pass a voltage in the range [0, V 1 ] » (a) Logic 0 transfer (b)

(b) Logic 1 transfer

Figure 8 nFET pass characteristics

Static CMOS Circuit

Static CMOS Circuit At every point in time (except during the switching transients) each gate output

At every point in time (except during the switching transients) each gate output is connected to either V DD or V ss via a low-resistive path.

The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).

This is in contrast to the

relies on temporary storage of signal values on the

dynamic

circuit class, which

capacitance of high impedance circuit nodes.

Static CMOS

Static CMOS In1 In2 In3 In 1 In 2 In 3 V DD PUN PDN V

In1

In2

In3

In 1

In 2

In 3

V DD

Static CMOS In1 In2 In3 In 1 In 2 In 3 V DD PUN PDN V
PUN PDN

PUN

PUN PDN
PUN PDN

PDN

PUN PDN
PUN PDN
PUN PDN
PUN PDN
PUN PDN
PUN PDN
PUN PDN
PUN PDN
PUN PDN
PUN PDN
Static CMOS In1 In2 In3 In 1 In 2 In 3 V DD PUN PDN V
Static CMOS In1 In2 In3 In 1 In 2 In 3 V DD PUN PDN V
Static CMOS In1 In2 In3 In 1 In 2 In 3 V DD PUN PDN V
Static CMOS In1 In2 In3 In 1 In 2 In 3 V DD PUN PDN V
Static CMOS In1 In2 In3 In 1 In 2 In 3 V DD PUN PDN V

V SS

Static CMOS In1 In2 In3 In 1 In 2 In 3 V DD PUN PDN V

PMOS Only

F = G

NMOS Only

PUN and PDN are Dual Networks

Simple CMOS Circuits: The Inverter Gate

Simple CMOS Circuits: The Inverter Gate Inverter Schematic Vin Vdd   PMOS     source P-MOS

Inverter

Schematic

Vin
Vin

Vdd

  PMOS
 
  PMOS

PMOS

   

source

P-MOS

P-MOS

 
 
   

PMOS drain

  Vout
 
  Vout

Vout

  Vout
 
 
  NMOS drain N-MOS

NMOS drain

N-MOS

 
 
   
   
   
 
  NMOS source

NMOS source

            NMOS source Gnd Inverter Symbol • The simplest complementary MOS

Gnd

            NMOS source Gnd Inverter Symbol • The simplest complementary MOS

Inverter Symbol

The simplest complementary MOS (CMOS) circuit is the inverter:

NMOS & PMOS gates are connected together as the

input

NMOS & PMOS drains are connected together as the output

NMOS & PMOS sources are connected to Gnd and Vdd, respectively.

NMOS substrate is normally connected to Gnd for all

NMOS devices in the circuit

PMOS well is normally connected to Vdd (most positive voltage in circuit) for all PMOS devices

Operation:

If Vin is down (0 volts), NMOS is OFF and PMOS is

ON pulling Vout to Vdd (high = 1)

If Vin is up (at Vdd), NMOS is ON hard and PMOS is OFF pulling Vout low to Gnd (“0”)

With Vin at 0 or Vdd, no dc current flows in inverter

CMOS Inverter

CMOS Inverter A Y 0 1 A A Y V DD Y GND
A Y 0 1 A A Y
A
Y
0
1
A
A
Y
V DD Y GND
V
DD
Y
GND

CMOS Inverter

CMOS Inverter A Y 0   1 0 A Y A= 1 V DD OFF Y=

A

Y

0

 

1

0

A

CMOS Inverter A Y 0   1 0 A Y A= 1 V DD OFF Y=

Y

A=1

V DD

CMOS Inverter A Y 0   1 0 A Y A= 1 V DD OFF Y=
CMOS Inverter A Y 0   1 0 A Y A= 1 V DD OFF Y=

OFF

Y=0

ON

GND

CMOS Inverter

CMOS Inverter A Y 0 1 1 0 A=0 A Y V DD ON Y= 1
A Y 0 1 1 0 A=0 A Y
A
Y
0
1
1
0
A=0
A
Y

V DD

CMOS Inverter A Y 0 1 1 0 A=0 A Y V DD ON Y= 1
CMOS Inverter A Y 0 1 1 0 A=0 A Y V DD ON Y= 1

ON

Y=1

OFF

GND

Series connected MOSFETS

Series connected MOSFETS
Series connected MOSFETS

Parallel Connected MOSFETS

Parallel Connected MOSFETS
Parallel Connected MOSFETS

Series and Parallel

Series and Parallel  nMOS: 1 = ON  pMOS: 0 = ON  Series :

nMOS: 1 = ON

pMOS: 0 = ON

Series: both must be ON

Parallel: either can be ON

a

 

g1

  g1  
 

g2

 

b

(a)

 

a

 

g1

  g1  
 

g2

 

b

(b)

 

a

 

g1

g1 g2

g2

 

b

(c)

 

a

 

g1

g1 g2

g2

 

b

(d)

 

a

a

a

a

0

b

b

0 1

1 0

b

1

0

1

b

OFF

OFF

OFF

ON

 

a

a

a

a

0

b

b

0 1

1 0

b

1

b

0

1

ON

OFF

OFF

OFF

a

a

a

a

0

b 0 1 ON OFF OFF OFF a a a a 0 b 0 OFF 0

b

0

OFF

0

a

01 ON OFF OFF OFF a a a a 0 b 0 OFF 0 a 0

0

0 1 1 0 1 1

1

1

0 1 1 0 1 1

0

1

0 1 1 0 1 1

1

b

b

b

ON

ON

ON

a

a

a

0

0 1 1 0 1 1

1

1

0 1 1 0 1 1

0

1

0 1 1 0 1 1

1

b

b

b

b

ON

ON

ON

OFF

Pull-up / Pull-down Model

Pull-up / Pull-down Model • Typical CMOS gate can be viewed as consisting of two parts

Typical CMOS gate can be viewed as

consisting of two parts

pull-up network and pull-down network

A

B

C

A

B

C

V DD

Pull-up output Pull- down GND
Pull-up
output
Pull-
down
GND

Pull-up / Pull-down Model

Pull-up / Pull-down Model • High level inputs to the PDN cause switches to close •

High level inputs to the PDN cause switches to close

If there is a closed switch path thru

PDN, then output is low

Low level inputs to the PUN cause switches to close

If there is a closed switch path thru

PUN, then output is high

CMOS NAND Gate

CMOS NAND Gate A B Y 0 0   0 1   1 0   1

A

B

Y

0

0

 

0

1

 

1

0

 

1

1

 
CMOS NAND Gate A B Y 0 0   0 1   1 0   1
CMOS NAND Gate A B Y 0 0   0 1   1 0   1

A

B

CMOS NAND Gate A B Y 0 0   0 1   1 0   1

Y

CMOS NAND Gate

CMOS NAND Gate A B Y 0 0 1 0 1   1 0   1

A

B

Y

0

0

1

0

1

 

1

0

 

1

1

 
Gate A B Y 0 0 1 0 1   1 0   1 1  
Gate A B Y 0 0 1 0 1   1 0   1 1  
ON ON A=0 B=0
ON
ON
A=0
B=0

OFF

OFF

Y=1

CMOS NAND Gate

CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0   1

A

B

Y

0

0

1

0

1

1

1

0

 

1

1

 
Gate A B Y 0 0 1 0 1 1 1 0   1 1  
Gate A B Y 0 0 1 0 1 1 1 0   1 1  
ON OFF A=0 B=1 ON
ON
OFF
A=0
B=1
ON

OFF

Y=1

CMOS NAND Gate

CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1

A

B

Y

0

0

1

0

1

1

1

0

1

1

1

 
NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 1
NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 1
ON A=1 ON B=0
ON
A=1
ON
B=0

OFF

Y=1

OFF

CMOS NAND Gate

CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1

A

B

Y

0

0

1

0

1

1

1

0

1

1

1

0

CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1
CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1
OFF A=1 ON B=1 ON
OFF
A=1
ON
B=1
ON

OFF

Y=0

CMOS NOR Gate

CMOS NOR Gate A B Y 0 0 1 0 1 0 1 0 0 1

A

B

Y

0

0

1

0

1

0

1

0

0

1

1

0

CMOS NOR Gate A B Y 0 0 1 0 1 0 1 0 0 1
CMOS NOR Gate A B Y 0 0 1 0 1 0 1 0 0 1

A

B

CMOS NOR Gate A B Y 0 0 1 0 1 0 1 0 0 1

Y

3-input NAND Gate

3-input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high

Y pulls low if ALL inputs are 1

Y pulls high if ANY input is 0

3-input NAND Gate

3-input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high

Y pulls low if ALL inputs are 1

Y pulls high if ANY input is 0

A

B

C

3-input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high

Y

Logic Identities

Logic Identities
Logic Identities

Logic Analysis -Inverter

Logic Analysis -Inverter
Logic Analysis -Inverter

Logic Analysis NAND Gate

Logic Analysis – NAND Gate
Logic Analysis – NAND Gate

Logic Analysis NOR Gate

Logic Analysis – NOR Gate
Logic Analysis – NOR Gate

Pull-up / Pull-down Model

Pull-up / Pull-down Model A Since hign level signals on the inputs cause the PDN to
A Since hign level signals on the inputs cause the PDN to A and (
A
Since hign level signals on
the inputs cause the PDN to
A and ( B or C)
B
C
close switches, we get a
Boolean expression for the
input which creates a closed
path thru PDN
If a closed path exists in PDN, then the output is pulled low.
Thus the logic function realized is the complement (inverted)
version of the Boolean expression.
output
A
not (A and ( B or C))
Pull-
B
down
C

GND

Pull-up / Pull-down Model

Pull-up / Pull-down Model What happens when the Boolean expression is false? Since there is no

What happens when the Boolean expression is false?

Since there is no path thru PDN, the output could float.

In order to make the output high, the PUN must have a path which connects V DD to the output.

Observe: take the expression for PDN and use DeMorgans Law to write

it in terms of complemented input variables. Complemented variables are true when the input level is low. Thus, this gives exactly the form of the PUN

In this case:

not A or

( not B and not C)

B

C

Vdd

the input level is low. Thus, this gives exactly the form of the PUN In this

A

Example Gate: COMPLEX CMOS GATE

Example Gate: COMPLEX CMOS GATE OUT = D + A • (B+C)

OUT = D + A(B+C)

Example Gate: COMPLEX CMOS GATE

Example Gate: COMPLEX CMOS GATE A D V DD B C D A B C OUT

A

D

V DD

B C D A B C
B
C
D
A
B C

OUT = D + A(B+C)

A D V DD B C D A B C OUT = D + A

A

D

V DD

B C D A B C
B
C
D
A
B C

OUT = D + A(B+C)

A D V DD B C D A B C OUT = D + A •

Examples of pull-down networks

Examples of pull-down networks
Examples of pull-down networks

Examples of pull-up networks

Examples of pull-up networks
Examples of pull-up networks
A B C V DD PMOSs Out NMOSs GND

A

B

C

A B C V DD PMOSs Out NMOSs GND

V DD

PMOSs

Out

NMOSs

GND

B A C E D Vcc F Gnd
B
A
C
E
D
Vcc
F
Gnd
Vcc C E D A B F A C B D E Gnd B A
Vcc C E D A B F A C B D E Gnd
Vcc
C
E
D
A
B
F
A
C
B
D
E
Gnd
B A C E D Vcc F Gnd
B
A
C
E
D
Vcc
F
Gnd

Stick Diagram, Interconnected

Stick Diagram, Interconnected 83
Stick Diagram, Interconnected 83
Stick Diagram, Interconnected 83
Stick Diagram, Interconnected 83

83

Two Versions of C • (A + B)
Two Versions of C • (A + B)
Two Versions of C • (A + B) V DD GND A C B X A

V

DD

GND

A C B X
A
C
B
X
A B C X
A
B
C
X

V

DD

GND

Line of diffusion layout abutting source-drain connections

Note crossover eliminated by A B C ordering

• Example: x y + x z + x v • 5 operations: • 1

Example:

x y + x z + x v

5 operations:

1 AND, 2 OR

# txs =

?

=

x (y + z + v)

3 operations:

3 AND, 2 OR

# txs =

?

Construct a CMOS logic gate to

implement the function:

Construct a CMOS logic gate to implement the function: F = a • (b + c)
Construct a CMOS logic gate to implement the function: F = a • (b + c)

F = a • (b + c)

Construct a CMOS logic gate to implement the function: F = a • (b + c)

14 transistors (cascaded gates)

Construct a CMOS logic gate to

implement the function:

Construct a CMOS logic gate to implement the function: F = a • (b + c)
Construct a CMOS logic gate to implement the function: F = a • (b + c)

F = a • (b + c)

Construct a CMOS logic gate to implement the function: F = a • (b + c)
Construct a CMOS logic gate to implement the function: F = a • (b + c)
Construct a CMOS logic gate to implement the function: F = a • (b + c)

Complex gates in CMOS logic

Complex gates in CMOS logic • A complex logic gate is one that implements a function

A complex logic gate is one that implements a function that can provide the basic NOT, AND and OR operation

but integrates them into a single circuit.

CMOS is ideally suited for creating gates that have logic equations by exhibiting the following,

1) AND-OR-INVERT

2) OR-AND-INVERT

An AOI logic equation is equivalent to a complemented SOP from, while an AOI equation is equivalent to a complemented POS structure.

In CMOS, output always produces NOT operation acting on input variable

AOI form

-

- OAI form

AOI Logic Function (OR) Design of XOR gate using CMOS logic.

Logic Function (OR) Design of XOR gate using CMOS logic. • AND-OR-INVERT logic function(AOI) implements operation

AND-OR-INVERT logic function(AOI)

implements operation in the order

AND,OR,NOT. For example ,

Let us consider the function Y = AB+CD i.e., Y = NOT((A AND B)OR (C AND D))

The AOI logic gate

implementation for Y

The AOI logic gate implementation for Y
The AOI logic gate implementation for Y

CMOS implementation for Y

CMOS implementation for Y • Step 1: Draw A.B (AND) function first by connecting 2 nMOS

Step 1: Draw A.B (AND) function first

by connecting 2 nMOS transistors in

series.

CMOS implementation for Y • Step 1: Draw A.B (AND) function first by connecting 2 nMOS

Step 2: Draw C.D implementation, by using 2

nMOS transistors in series.

Step 2: Draw C.D implementation, by using 2 nMOS transistors in series.
Step 2: Draw C.D implementation, by using 2 nMOS transistors in series.

Step 3:

Step 3: Y = A.B+C.D , In this function A.B and C.D are added, for addition

Y = A.B+C.D , In this function A.B and C.D are added, for addition , we have to draw parallel connection. So, A.B series connected in parallel with C.D as shown in figure.

for addition , we have to draw parallel connection. So, A.B series connected in parallel with

Step 4: Draw pMOS connection,

Step 4: Draw pMOS connection, I. In nMOS A,B connected in series. So, in pMOS side,

I. In nMOS A,B connected in series. So, in pMOS side, A.B should be connected in parallel.

II. In nMOS C,D connected in series. So, in pMOS side,

C.D should be connected inparallel. III. A.B and C.D networks are connected in parallel in nMOS side. So, in pMOS side, A.B and C.D networks should be connected in series.

IV. In pMOS multiplication should be drawn in parallel, then

addition should be drawn in series as shown in figure.

IV. In pMOS multiplication should be drawn in parallel, then addition should be drawn in series

Step 5: Take output at the point in between nMOS

and pMOS networks.

Step 5: Take output at the point in between nMOS and pMOS networks.
Step 5: Take output at the point in between nMOS and pMOS networks.
CMOS implementation for Y
CMOS implementation for Y

CMOS implementation for Y

Example: x = ab+cd

Example: x = ab+cd
Example: x = ab+cd

OAI Logic Function (OR) Design of XNOR

gate using CMOS logic.

OAI Logic Function (OR) Design of XNOR gate using CMOS logic. • OR-AND-INVERT logic function(AOI) implements

OR-AND-INVERT logic function(AOI)

implements operation in the order

OR,AND,NOT. For example ,

Let us consider the function Y = (A+B).(C+D) i.e., Y = NOT((A OR B)AND (C OR D))

CMOS implementation for Y
CMOS implementation for Y

CMOS implementation for Y

OAI22 Logic Graph

OAI22 Logic Graph A C B D X = (A+B)•(C+D) C D A B A B
A C B D X = (A+B)•(C+D) C D A B A B C D
A
C
B
D
X = (A+B)•(C+D)
C
D
A
B
A
B
C
D

Structured Logic Design (1/4)

Structured Logic Design (1/4)  CMOS logic gates are intrinsically inverting » Output always produces a

CMOS logic gates are intrinsically inverting

» Output always produces a NOT operation acting on the input variables

produces a NOT operation acting on the input variables Figure 2.42 Origin of the inverting characteristic

Figure 2.42 Origin of the inverting characteristic of CMOS gates

Structured Logic Design (2/4)

Structured Logic Design (2/4) (a) Series-connected nFETs (b) Parallel-connected nFETs Figure 2.43 nFET logic formation
Structured Logic Design (2/4) (a) Series-connected nFETs (b) Parallel-connected nFETs Figure 2.43 nFET logic formation
Structured Logic Design (2/4) (a) Series-connected nFETs (b) Parallel-connected nFETs Figure 2.43 nFET logic formation

(a) Series-connected nFETs

Structured Logic Design (2/4) (a) Series-connected nFETs (b) Parallel-connected nFETs Figure 2.43 nFET logic formation
Structured Logic Design (2/4) (a) Series-connected nFETs (b) Parallel-connected nFETs Figure 2.43 nFET logic formation

(b) Parallel-connected nFETs

Figure 2.43 nFET logic formation

(b) Parallel-connected nFETs Figure 2.43 nFET logic formation Figure 2.44 nFET AOI circuit Figure 2.45 nFET
(b) Parallel-connected nFETs Figure 2.43 nFET logic formation Figure 2.44 nFET AOI circuit Figure 2.45 nFET

Figure 2.44 nFET AOI circuit

(b) Parallel-connected nFETs Figure 2.43 nFET logic formation Figure 2.44 nFET AOI circuit Figure 2.45 nFET
(b) Parallel-connected nFETs Figure 2.43 nFET logic formation Figure 2.44 nFET AOI circuit Figure 2.45 nFET

Figure 2.45 nFET OAI circuit

Structured Logic Design (3/4)

Structured Logic Design (3/4) (a) Parallel-connected pFETs ( b ) S e r i e s
Structured Logic Design (3/4) (a) Parallel-connected pFETs ( b ) S e r i e s
Structured Logic Design (3/4) (a) Parallel-connected pFETs ( b ) S e r i e s

(a) Parallel-connected pFETs

Structured Logic Design (3/4) (a) Parallel-connected pFETs ( b ) S e r i e s
Structured Logic Design (3/4) (a) Parallel-connected pFETs ( b ) S e r i e s

(b) Series-connected pFETs

Figure 2.46 pFET logic formation

c t e d p F E T s Figure 2.46 pFET logic formation (a) pFET

(a) pFET AOI circuit

T s Figure 2.46 pFET logic formation (a) pFET AOI circuit (b) pFET OAI circuit Figure

(b) pFET OAI circuit

Figure 2.47 pFET arrays for AOI and OAI gates

Structured Logic Design (4/4)

Structured Logic Design (4/4) (a) AOI circuit (b) OAI circuit Figure 2.48 Complete CMOS AOI and
Structured Logic Design (4/4) (a) AOI circuit (b) OAI circuit Figure 2.48 Complete CMOS AOI and

(a) AOI circuit

Structured Logic Design (4/4) (a) AOI circuit (b) OAI circuit Figure 2.48 Complete CMOS AOI and

(b) OAI circuit

Figure 2.48 Complete CMOS AOI and OAI circuits

Bubble Pushing

Bubble Pushing (a) Parallel-connected pFETs (b) Series-connected pFETs Figure 2.51 Assert-low models for pFETs (a) NAND
Bubble Pushing (a) Parallel-connected pFETs (b) Series-connected pFETs Figure 2.51 Assert-low models for pFETs (a) NAND
Bubble Pushing (a) Parallel-connected pFETs (b) Series-connected pFETs Figure 2.51 Assert-low models for pFETs (a) NAND

(a)

Parallel-connected pFETs

Bubble Pushing (a) Parallel-connected pFETs (b) Series-connected pFETs Figure 2.51 Assert-low models for pFETs (a) NAND
Bubble Pushing (a) Parallel-connected pFETs (b) Series-connected pFETs Figure 2.51 Assert-low models for pFETs (a) NAND

(b)

Series-connected pFETs

Figure 2.51 Assert-low models for pFETs

pFETs Figure 2.51 Assert-low models for pFETs (a) NAND - OR (b) NOR - AND Figure
pFETs Figure 2.51 Assert-low models for pFETs (a) NAND - OR (b) NOR - AND Figure
pFETs Figure 2.51 Assert-low models for pFETs (a) NAND - OR (b) NOR - AND Figure

(a) NAND - OR

pFETs Figure 2.51 Assert-low models for pFETs (a) NAND - OR (b) NOR - AND Figure
pFETs Figure 2.51 Assert-low models for pFETs (a) NAND - OR (b) NOR - AND Figure

(b) NOR - AND

pFETs Figure 2.51 Assert-low models for pFETs (a) NAND - OR (b) NOR - AND Figure

Figure 2.52 Bubble pushing using DeMorgan rules

XOR and XNOR gates

XOR and XNOR gates
XOR and XNOR gates
XOR and XNOR gates

XOR and XNOR Gates

XOR and XNOR Gates  An important example of using an AOI circuit is constructing Exclusive-OR

An important example of using an AOI circuit is constructing Exclusive-OR (XOR) and Exclusive-NOR circuits

a b a a a b b b
a
b
a
a a
b b
b
a b
a
b
(a b) a b a b
(a
b)
a
b
a
b
a b a b a b
a
b
a
b
a
b
a a a b b b a b (a b) a b a b a b
a a a b b b a b (a b) a b a b a b

Figure 2.56 XOR

(2.71)

(2.72)

(2.73)

(2.74)

a b a b a b Figure 2.56 XOR (2.71) (2.72) (2.73) (2.74) (a) Exclusive-OR (b)

(a) Exclusive-OR

(b) Exclusive-NOR

Figure 2.57 AOI XOR and XNOR gates

(b) Exclusive-NOR Figure 2.57 AOI XOR and XNOR gates (a) AOI22 (b) AOI321 (c) AOI221 Figure

(a) AOI22

(b) Exclusive-NOR Figure 2.57 AOI XOR and XNOR gates (a) AOI22 (b) AOI321 (c) AOI221 Figure

(b) AOI321

(b) Exclusive-NOR Figure 2.57 AOI XOR and XNOR gates (a) AOI22 (b) AOI321 (c) AOI221 Figure

(c) AOI221

Figure 2.58 General naming convention

A B C D E Vcc F Gnd
A B C D E Vcc F Gnd
A
B
C
D
E
Vcc
F
Gnd

logic cascade in cmos

logic cascade in cmos
logic cascade in cmos

Half-Adder

Half-Adder Truth Table x y C S 0 0 0 0 0 1 0 1 1

Truth Table

x y

C S

0

0

0

0

0 1

0 1

1 0

0 1

1 1

1 0

Logic Equations

C = x • y

S = x

x y C S 0 0 0 0 0 1 0 1 1 0 0 1

y

Schematic

x y C S 0 0 0 0 0 1 0 1 1 0 0 1

Full Adder

Full Adder • Adding two single-bit binary values, X, Y with a carry input bit C-in

Adding two single-bit binary values, X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit.

Full Adder Truth Table

Inputs

Outputs

X

Y

C-in

S

C-out

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

0 1 1 1 0 0 1 1 1 1 1 1 S(X,Y, C-in) = C-out(x,

S(X,Y, C-in) =

C-out(x, y, C-in) =

(1,2,4,7)

1 1 1 S(X,Y, C-in) = C-out(x, y, C-in) = (1,2,4,7) (3,5,6,7) Sum S X XY

(3,5,6,7)

Sum S

X

XY
XY

C-in

0

11 10
11
10

00

01

0

2 6

1

4

1

1

1

3

7

1

5

1

Sum S X XY C-in 0 11 10 00 01 0 2 6 1 4 1
Sum S X XY C-in 0 11 10 00 01 0 2 6 1 4 1

C-in

Y

S = X’Y’(C-in) + XY’(C-in)’ + XY’(C-in)’ + XY(C-in) S = X Y (C-in) Carry
S = X’Y’(C-in) + XY’(C-in)’ + XY’(C-in)’ + XY(C-in)
S =
X
Y
(C-in)
Carry C-out
X
XY
C-in
00
01
11
10
0
2 6
4
0
1
1
3 7
5
1
1
1
1
Carry C-out X XY C-in 00 01 11 10 0 2 6 4 0 1 1

C-in

Y

C-out = XY + X(C-in) + Y(C-in)

Addition of Binary Numbers

Addition of Binary Numbers Full Adder. The full adder is the fundamental building block of most

Full Adder. The full adder is the fundamental building block of

most arithmetic circuits:

a i b i Full Adder
a i
b i
Full
Adder

C out

C in

s i

The sum and carry outputs are described as:

c

i

1
1

s

i

s i The sum and carry outputs are described as: c i 1 s i abc

abc

i

i

i

sum and carry outputs are described as: c i 1 s i abc i i i

abc

i

i

i

outputs are described as: c i 1 s i abc i i i abc i i

abc

i

i

i

are described as: c i 1 s i abc i i i abc i i i

abc

i

i

i

as: c i 1 s i abc i i i abc i i i abc i

abc

i

i

i

as: c i 1 s i abc i i i abc i i i abc i

a bc

i

i

i

as: c i 1 s i abc i i i abc i i i abc i

ab c

i

i

i

as: c i 1 s i abc i i i abc i i i abc i

abc

i

i

i

as: c i 1 s i abc i i i abc i i i abc i

ab

i

i

as: c i 1 s i abc i i i abc i i i abc i

ac

i

i

as: c i 1 s i abc i i i abc i i i abc i

i

bc

i

Full Adder Circuit Using AND-OR

Full Adder Circuit Using AND-OR X X X’ Y C-in Y Y’ C-in C-in’ X Y
X X X’
X
X
X’

Y

C-in

Y Y’ C-in C-in’
Y
Y’
C-in
C-in’
X Y Full C-out C-in Adder
X
Y
Full
C-out
C-in
Adder

S

X’ X’Y’C-in Y’ C-in X’ X’YC-in’ Y C-in’ X Y C-in’ XY’C-in’ X Y XYC-in
X’
X’Y’C-in
Y’
C-in
X’
X’YC-in’
Y
C-in’
X
Y
C-in’
XY’C-in’
X
Y
XYC-in
C-in’

Sum S

X

Y

X

XY XC-in YC-in
XY
XC-in
YC-in

C-in

Y

C-in

C-out

Cont

Cont
Cont

Addition of Binary Numbers

Addition of Binary Numbers Inputs Outputs c a b s c i i i i i+1
Inputs Outputs c a b s c i i i i i+1 0 0 0
Inputs
Outputs
c
a
b
s
c
i
i
i
i
i+1
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1

Propagate

Generate

Propagate

Generate

PGK

PGK  For a full adder, define what happens to carries » Generate: C o u

For a full adder, define what happens to carries

» Generate: C out = 1 independent of C

G = A B

» Propagate: C out = C

P = A

B
B

» Kill: C out = 0 independent of C

K = ~A ~B

Full-Adder Implementation

Full-Adder Implementation Full Adder operations is defined by equations: abc i i i p g i

Full Adder operations is defined by equations:

Full Adder operations is defined by equations: abc i i i p g i i abc
Full Adder operations is defined by equations: abc i i i p g i i abc

abc

i

i

i

Full Adder operations is defined by equations: abc i i i p g i i abc
Full Adder operations is defined by equations: abc i i i p g i i abc
Full Adder operations is defined by equations: abc i i i p g i i abc
Full Adder operations is defined by equations: abc i i i p g i i abc

p

g

i

i

abc

i

i

i

is defined by equations: abc i i i p g i i abc i i i
is defined by equations: abc i i i p g i i abc i i i

g

a b c i i i
a
b
c
i
i
i
by equations: abc i i i p g i i abc i i i g a

p

i

c i
c
i

abc

i

i

i

abc

i

i

i

i

abc i i i g a b c i i i p i c i abc

i

s

i

a i

g a b c i i i p i c i abc i i i abc

b i

b c i i i p i c i abc i i i abc i i

abc

i

i

i

abc

i

i

i

ab

i

i

c

i

1
1

pc

i

i i i i s i a i b i abc i i i abc i
a b i i a b i i
a
b
i
i
a
b
i
i

Carry-Propagate:

c out
c
out
i c i 1 pc i a b i i a b i i Carry-Propagate: c

and Carry-Generate

One-bit adder could be

implemented as shown

s i

c in

High-Speed Addition

High-Speed Addition c i 1 g i p c i i a i b i a

c

i

1
1
High-Speed Addition c i 1 g i p c i i a i b i a

g

i

High-Speed Addition c i 1 g i p c i i a i b i a

p c

i

i

a i

b i

a
a

i

High-Speed Addition c i 1 g i p c i i a i b i a

b

0 s p c i i i s 1 c in
0
s
p
c
i
i
i
s
1
c
in
p c i i a i b i a i b 0 s p c i

s i

g

i

i

i b i a i b 0 s p c i i i s 1 c

c out

a i b 0 s p c i i i s 1 c in s i

One-bit adder could be implemented more efficiently because MUX is faster

p

i

a b i i
a
b
i
i

Multiplexers

Multiplexers  2:1 multiplexer chooses between two inputs S D1 D0 Y   0 X 0

2:1 multiplexer chooses between two inputs

S

D1

D0

Y

 

0

X

0

 

D0

0

X

1

 

D1

1

0

X

 

1

1

X

   

S

0 Y 1
0
Y
1

Multiplexers

Multiplexers  2:1 multiplexer chooses between two inputs S D1 D0 Y   0 X 0

2:1 multiplexer chooses between two inputs

S

D1

D0

Y

 

0

X

0

0

D0

0

X

1

1

D1

1

0

X

0

1

1

X

1

 

S

0 Y 1
0
Y
1

Gate-Level Mux Design

Gate-Level Mux Design   Y SD SD (too many transistors) 1 0 How many transistors

Y

SD SD (too many transistors) 1 0
SD
SD (too many transistors)
1
0

How many transistors are needed?

Gate-Level Mux Design

Gate-Level Mux Design   Y SD SD (too many transistors) 1 0 How many transistors

Y

SD SD (too many transistors) 1 0
SD
SD (too many transistors)
1
0

How many transistors are needed? 20

D1

S

D0

D1

S

D0

  Y SD SD (too many transistors) 1 0 How many transistors are needed? 20

Y

4 2 4 2 4 2 2
4
2
4
2
4
2
2

Y

Inverting Mux

Inverting Mux  Inverting multiplexer » Use compound AOI22 » Or pair of tristate inverters »

Inverting multiplexer

» Use compound AOI22

» Or pair of tristate inverters

» Essentially the same thing

Noninverting multiplexer adds an inverter

D0 S S D1 S S
D0
S
S
D1
S
S

Y

D0

D1

S

0 Y 1
0
Y
1

Tristate Inverter

Tristate Inverter  Tristate inverter produces restored output » Violates conduction complement rule » Because we

Tristate inverter produces restored output

» Violates conduction complement rule

» Because we want a Z output

A EN EN
A
EN
EN

Y

Tristate Inverter

Tristate Inverter  Tristate inverter produces restored output » Violates conduction complement rule » Because we

Tristate inverter produces restored output

» Violates conduction complement rule

» Because we want a Z output

A EN EN
A
EN
EN

Y

A

complement rule » Because we want a Z output A EN EN Y A A Y
A Y Y
A
Y
Y
complement rule » Because we want a Z output A EN EN Y A A Y

EN = 0

EN = 1

Y = 'Z'

Y = A

D0 D1 S S S S Y D0 D1 S 0 Y 1
D0 D1 S S S S
D0
D1
S
S
S
S

Y D0

D1

S

0 Y 1
0
Y
1

Inverting Mux

Inverting Mux  Inverting multiplexer » Use compound AOI22 » Or pair of tristate inverters »

Inverting multiplexer

» Use compound AOI22

» Or pair of tristate inverters

» Essentially the same thing

Noninverting multiplexer adds an inverter

S S D1 S S
S
S
D1
S
S

D0

Y

D0 D1 S S S S
D0
D1
S
S
S
S

Y

D0

D1

S

0 Y 1
0
Y
1

Complimentary Static CMOS Full Adder

Complimentary Static CMOS Full Adder A V DD V DD C A B i A B

A

V DD

V DD C A B i A B A B B C i A X
V
DD
C
A
B
i
A
B
A
B
B
C
i
A
X
C
i
C
A
i
C
i
B
B
V
DD
A
B
C
A
i
C
o
B

28 Transistors

V DD

DD C A B i A B A B B C i A X C i

S

A Better Structure: The Mirror Adder

A Better Structure: The Mirror Adder "0"-Propagate "1"-Propagate V DD A V DD V DD A

"0"-Propagate

"1"-Propagate

V DD A V DD V DD A B A B B B C i
V DD
A
V DD
V DD
A
B
A
B
B
B
C i
Kill
A
C i
C o
C i
A
C i
Generate
A
B
A
A
B
B
C i
B

S

24 transistors

and 2 inverter Total 24+4 =28 Transistors

Mirror Adder

Mirror Adder Stick Diagram V DD A B B A A B C i C i

Stick Diagram

V DD A B B A A B C i C i C o C
V DD
A
B
B
A
A
B
C i
C i
C o
C i
C o
S
GND

139

OAI/AOI

duality

OAI/AOI duality A B OUT C A Vdd B C C B A Out B A
A B OUT C
A
B
OUT
C
A Vdd B C C B A Out B A C Gnd
A
Vdd
B
C
C
B
A
Out
B
A
C
Gnd
OAI/AOI duality A B OUT C A Vdd B C C B A Out B A
OUT
OUT

Review: Construction of PDN

Review: Construction of PDN • NMOS devices in series implement a NAND function A • B

NMOS devices in series implement a NAND function

PDN • NMOS devices in series implement a NAND function A • B A B •
A • B A B
A • B
A
B

NMOS devices in parallel implement a NOR function

A

B
B
in series implement a NAND function A • B A B • NMOS devices in parallel

A + B

• Scale both W and L • – no effective change in W/L • –

Scale both W and L

no effective change in W/L

increases gate capacitance

• Scale both W and L • – no effective change in W/L • – increases

• Series Transistors

• Series Transistors • – increases effective L

increases effective L

• Series Transistors • – increases effective L
• Series Transistors • – increases effective L

• Parallel Transistors

• Parallel Transistors • increases effective W

increases effective W

• Parallel Transistors • increases effective W

Analysis of CMOS gates

Analysis of CMOS gates  Represent “on” transistors as resistors 1 W 1 W R 1

Represent “on” transistors as resistors

1 W
1
W
1 W R 1 W
1
W
R
1
W
R R
R
R

• Transistors in series → resistances in series

Effective resistance = 2R

Effective width = ½ W

Analysis of CMOS gates, cont

Analysis of CMOS gates, cont • Represent “on” transistors as resistors 0 W W W R

• Represent “on” transistors as resistors

0

W
W
W W R 0 0
W
W
R
0
0
R R
R
R

• Transistors in parallel → resistances in parallel

Effective resistance = ½ R

Effective width = 2W

CMOS gate design

CMOS gate design  Designing a CMOS gate:  Find pulldown NMOS network from logic function