Anna University

1. What is mean by “Epitaxy”? 2. What is isolation? 3. What are the steps involved in manufacturing of IC? 4. What is the special feature of Twin-Tub process? 5. What are the various process used in SOI process? 6. Draw the Isotropic etching process diagram. 7. What is siliside? 8. What is AOI? 9. Define fabrication process. 10. What do you mean by Isolation?

1. Explain the silicon semiconductor technology with various processes that are involved in the sae. (16) 2. Differentiate the p-well CMOS process from n-well CMOS process. Explain the n-well CMOS process to fabricate the n-switches. 3. Write brief notes on (i) Twin-Tube process (ii) Silicon – On Insulator (SIO) process. 4. How do you enhance the CMOS process & explain about an interconnect and a circuit element to do so. 5. Explain the following terms with neat diagram (i) Latch up (ii) Latch up Prevention. (16) (8) (8) (16) (8) (8)

6. List out the layout design rule & draw the physical layout for one basic gate & two universal gates.(16)

1. Draw the graph of n-MOS depletion mode. 2. Draw the diagram for the accumulation mode. 3. Draw the Dc transfer characteristics curve. 4. Define noise margin. 5. Define Rise Time. 6. Draw the symbol for tristate inverter.


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Explain the n MOS and p MOS enhancement transistor with its physical structure. 5. Fall Time. What are the uses of UCF file? 6. Write short notes on (I) Noise Margin. How do you declare the bus in the HDL? 2. 4. Give the relation of RT with FT. Define bit and byte. 8. Differentiate the various modes to develop the project and explain them with an example. Define FSM. Write the HDL coding for Modulo 2 Adder. Design and develop a project in HDL to compare x5x4x3x2x1x0 with y5y4y3y2y1y0. 6. Define the Power disipatiion PART-B 1. Define Mealy network.A ( 2 marks) (16) (8) (8) (16) (16) (10) (6) 1.A (2 marks) (16) (16) (16) 1. 3. 9. Develop the project using HDL to realize the function of a ripple carry adder & draw its RTL. 2. Design and develop a HDL project in structural model to realize the priority encoder. UNIT – IV CMOS CHIP DESIGN PART . 10.Vidyarthiplus. Derive and explain the (I) Threshold voltage equation. What is component in HDL? PART-B 1. Explain that how the MOS transistor is to be analysed by the small scale models.com 7. 3. 5. 5.com Page 2 . What are all the factors can be extracted from the Vth equation? 10. 2. 4. What do you mean by Data flow model? 8. Define vector in verilog. Give the duty cycle equation form the negative logic systems. (16) (16) 3.0. (II) Rise Time. Explain the complimentary CMOS inverter DC characteristics. 9. (II) MOS DC equation. Design a full adder by cascading two half adders and develop a project to realize it in model simulator 6. (16) 4. Explain the process flow that is followed to develop a project by any HDL with example. Differentiate the nMOS from pMOS. UNIT – III SPECIFICATION USING VERILOG HDL PART . 7. Which MOS can pass logic 1 and logic 0 strongly? www.Vidyarthiplus.www.

What are all the uses of programmable interconnect? Explain it with the neat diagram.www. Statistical Fault Analysis. & explain the 22V10 standard logic structure with the architecture. 12. (ii) Explain the Application Specific Integrated circuits Design Flow with architecture. Fault Models. 4. What is AOI logic function? 3. 6. x = (lmnop)’ + q’(r’s + rs’) (8) (8) (10) (6) 3. Differentiate the PALs from PLAs. 8. (ii) Explain the design of an inverted 2x1 MUX. Draw the basic PLA. List out the all types of ASICs and explain about any three types of the same with neat diagram. 5. Define PLD. (ii) Transmission gate. What does programmable interconnect mean? Explain the Actal interconnect with example.(16) 4. 2. What are all the types of programming PALs? 6. Briefly explain the following terms (i) Design of switches with MOSFETs.Vidyarthiplus.Vidyarthiplus. What is manual routing? PART-B 1. What are the methods for programming the PALs? 5. Muxs using TG. (i) Draw and explain the typical architecture of PAL. Differentiate the PLA from the PAL. 7. 11. ATPG. UNIT – V CMOS TESTING PART .A ( 2 marks) (16) (16) (16) (16) (8) (8) (16) (8) (8) (8) (8) (16) www. List out all the methods of design strategies for test and explain any three methods.com 2. Explain the reprogrammable gate array with the architecture and logic blocks. 10. 7. y = (a +b)’ + c + de b. Draw the physical layout for the following Boolean expression a. Explain the following terms i.com Page 3 . List out the types of ASICs. Explain the methods used to programme the PALs with neat diagram. Give an example circuit for OAI221 gate. 10. (i) Design and Draw the logic circuit using CMOS and tristate switch for the logical relation x1’ x2’ + x1x2. 9. 8. 9. ii.

8. 9.com Page 4 .com 1. (II) ATPG. What is fault sampling? 6. *****ALL THE BEST****** (8) (8) (16) (16) (8) (8) www. Statistical Fault Analysis. 10. With the help of IEEE1149 BSA and TAPA explain the system level test technique. Write short notes on “need for CMOS testing”. What is parallel simulation? 5.www. Define ATPG. Define SFA. 3. List out all the methods of design strategies for test and explain any three methods. Explain the following terms (I) Fault Models. What are all the major classifications of Testing? 3. Explain the same. (i) How do you find IDDQ ?.Vidyarthiplus. Draw the SC mode. Give the expression of IDDQ. 4. 4. What is meant by Ad-hoc testing? 7. Differentiate the System level g from the Chip level testing. 2. PART-B 1. 5. (ii) Draw and explain the Data path test scheme for chip level test methods.Vidyarthiplus. What is schooling process? 2.

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