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Code: 9A05406

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B. Tech III Year II Semester (R09) Regular & Supplementary Examinations, April/May 2013 COMPUTER ORGANIZATION (Common to EIE & E.Con.E) Time: 3 hours Max. Marks: 70 Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) 2 (a) (b) 3 (a) (b) 4 (a) (b) 5 6 (a) (b) 7 (a) (b) 8 (a) (b) Discuss in brief about the functions of various functional units in a computer system. Define MFLOPS and explain its importance. Explain the purpose of various registers in a computer. Discuss about the sequence of steps that occurs when an interrupt occurs. What is microinstruction? Give the typical horizontal and vertical microinstruction formats and compare them. Discuss about the design considerations of microinstruction sequencing technique. Design an array multiplier that multiplies two 4-bit numbers. Use AND gates and binary numbers. Represent (278.2875)10 in single and double precision format. Explain the performance considerations of various memories with necessary parameters. Explain the types of commands that an interface may receive when it is addressed by the CPU. Briefly list out the functioning of peripheral devices in an input-output organization. Explain about array processors. Give a short note on parallel processing. Explain centralized shared memory architecture. Explain the write operations to be performed on cache memory. *****

Code: 9A05406

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B. Tech III Year II Semester (R09) Regular & Supplementary Examinations, April/May 2013 COMPUTER ORGANIZATION (Common to EIE & E.Con.E) Time: 3 hours Max. Marks: 70 Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) Explain four stage instruction pipelining and superscalar execution. How it affects the performance of computer? What is the basic performance equation in computer? Explain how to increase the performance of computer by varying the parameters. Explain in brief about logical and shift instructions. List various states of an instruction cycle and with a neat sketch explain the execution of an instruction. What is the necessity of branching? Explain the control sequence required for branch instruction. Give the horizontal and vertical micro instructions format and compare them. Write short notes on array multiplier. Explain the operation of restoring division with flow chart. Describe the basic concepts of semiconductor RAM memories. Give short notes on cache memories. Discuss with necessary diagrams the programmed I/O method for controlling I/O operations. List differences between pipeline processing and vector processing. What is a cross bar switch? Explain. Explain inter processor communication and synchronization. *****

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Code: 9A05406

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B. Tech III Year II Semester (R09) Regular & Supplementary Examinations, April/May 2013 COMPUTER ORGANIZATION (Common to EIE & E.Con.E) Time: 3 hours Max. Marks: 70 Answer any FIVE questions All questions carry equal marks ***** 1 (a) Obtain an expression for even parity generator and checker and realize the expression with logic gates. (b) What is bias? What normalization is used in IEEE 754 standard? (a) Design a single bus line with three state buffers. (b) There exists three 4-bit registers (A, B and C) and 4-bit data lines (say D). Design a circuit to transfer data from any register to any other register including data lines and vice versa. (a) Describe how microinstructions are arranged in control memory and how they are interpreted. (b) Compare hardwired control unit and microprogrammed control unit. (a) Derive an algorithm in flow chart form for the non restoring method of fixed point binary division. (b) List four alternative methods of rounding the result of a floating point operation. (a) What is the difference between a RAM and ROM? (b) Describe working of any three auxiliary memory devices. (a) Explain about data transfer modes. (b) List the salient features about standard serial communication protocols. (a) What is pipeline? Explain space-time diagram for pipeline. (b) Explain pipeline for floating point addition and subtraction. (a) Explain the characteristics of multiprocessors. (b) Give a short note on cache coherence. *****

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Code: 9A05406

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B. Tech III Year II Semester (R09) Regular & Supplementary Examinations, April/May 2013 COMPUTER ORGANIZATION (Common to EIE & E.Con.E) Time: 3 hours Max. Marks: 70 Answer any FIVE questions All questions carry equal marks ***** 1 (a) Explain the basic performance equation. (b) Explain the process of error detection using parity bit with an example. (a) Differentiate between RISC and non-RISC systems. (b) Design a circuit for parallel load operation into one of the four 4-bit registers from a bus. Mention clearly control/selection bits and selection logic. Assume JK flip flops. (a) Formulate a mapping procedure that provides eight consecutive micro instructions for each routine. The operation code has six bits and the control memory has 2048 words. (b) Draw and explain the block diagram of hardwired control unit. (a) Explain the IEEE 754 single precision and double precision format of representing floating point numbers. (b) What is the benefit of using biased representation for the exponent portion of a floating point number? Explain the need for memory Hierarchy and discuss the reasons for not having a large enough main memory for storing the total information in a computer system. (a) Explain PCI bus in detail. (b) Bring out the features of RS 232. (a) Draw and explain space-time diagram for pipeline. (b) Elucidate arithmetic pipelining with necessary example. (a) Explain the interprocessor communication. (b) Write in detail about interprocessor arbitration. *****

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