You are on page 1of 4

Code: 9A05704

1
ADVANCED COMPUTER ARCHITECTURE
(Computer Science and Systems Engineering)

B.Tech III Year II Semester (R09) Regular & Supplementary Examinations, April/May 2013

Time: 3 hours Answer any FIVE questions All questions carry equal marks
***** 1 (a) (b) (a) (b) (a) (b) (a) (b) (a) (b) (a) (b) 7 (a) (b) 8 (a) (b)

Max Marks: 70

Explain briefly the operational model of SIMD computers. Explain in detail the levels of parallelism in program execution on modern computers. Explain in detail about the importance characteristics of parallel algorithms. Explain the memory Hierarchy in detail with a neat diagram. Explain synchronous and asynchronous bus timing protocols in detail. Write a short note on floating point operations. Explain different levels of hierarchy of bus system in detail. Explain in detail about the three generations of multicomputer. Explain in detail about the six types of vector instructions. What is compound vector function? Derive an expression for compound vector function. What is the need of scalable coherence interface? Explain different SCI interconnect models. Explain briefly the design goals of Tera multiprocessor systems. Write a short note on: Operand forwarding. Register renaming. Explain in detail about the semiconductor technology. Explain Cray XT super computer with a schematic diagram.

2

3

4

5

6

*****

Code: 9A05704

2
ADVANCED COMPUTER ARCHITECTURE
(Computer Science and Systems Engineering)

B.Tech III Year II Semester (R09) Regular & Supplementary Examinations, April/May 2013

Time: 3 hours Answer any FIVE questions All questions carry equal marks
***** 1 (a) (b) (a) (b) 3 (a) (b) (a) (b) (a) (b) 6 (a) (b) 7 (a) (b) (a) (b)

Max Marks: 70

Explain briefly the elements of modern computer with a neat diagram. Explain different factors affected by the performance of an interconnection networks. Define the basic metrics affecting the scalability of a computer system for a given application. Write a short note on CISC and RISC architectures. What is the need for Cache memory? Explain different cache addressing modes in detail. What is linear pipeline processor? Explain different models of linear pipelines. Explain the blocking and nonblocking network in detail. Explain briefly the major design choices made so far in building multicomputer. Draw the schematic logic diagram of the crossbar network between 8 processors and 256 memory banks in the Cray Y-MP816 and explain. Explain in detail about the implementation model of SIMD computers. Write a short notes on: Shared virtual memory. Page swapping. What are the limitations in exploiting instruction level parallelism? Write short notes on Thread level parallelism. What is Moore’s law? Explain the logic behind the Moore’s law in detail. Write a short note on sun ultra space T2 processor in detail.

2

4

5

8

*****

Code: 9A05704

3
ADVANCED COMPUTER ARCHITECTURE
(Computer Science and Systems Engineering)

B.Tech III Year II Semester (R09) Regular & Supplementary Examinations, April/May 2013

Time: 3 hours Answer any FIVE questions All questions carry equal marks
***** 1 (a) (b) (a) (b) (a) (b) Explain in detail about parallel random access machines. Differentiate between control flows versus data flow. Explain in detail about the application models of parallel computers. Write a short note on hit ratios and effective access time.

Max Marks: 70

2

3

Explain briefly the different performance issues for cache design. Explain how we can improve throughput of a pipelined processor with internal data forwarding among multiple functional units. Draw and explain the schematic design of a row of cross point switches in a single crossbar network. Write a short note on store-and-forwarding routing. In development of future general purpose super computers what are the major challengers. Explain. Draw and explain the architecture of connection machine CM-5. Explain briefly about the parameters to analyze the performance of a multithreaded environment. Explain the advantages and disadvantages of Tera multiprocessor system. Explain briefly about the TOMASULO’S algorithm. Explain the classification of multithread based on specific strategy adopted for switching between threads and hardware support. Explain in detail about the display technology. Differentiate structural parallelism versus instruction level parallelism.

4

(a) (b)

5

(a) (b)

6

(a) (b)

7

(a) (b)

8

(a) (b)

*****

Code: 9A05704

4
ADVANCED COMPUTER ARCHITECTURE
(Computer Science and Systems Engineering)

B.Tech III Year II Semester (R09) Regular & Supplementary Examinations, April/May 2013

Time: 3 hours Answer any FIVE questions All questions carry equal marks
***** 1 (a) (b) 2 (a) (b) (a) (b)

Max Marks: 70

Explain Flynn’s classification of various computer architecture based on notations of instruction and data streams. Write a short note on shared-memory multiprocessors. Define efficiency, utilization and quality parameters for evaluating parallel computations. Compare and explain between CISC and RISC. Compare the relative merits of the four cache memory organizations. What is memory swapping? Explain different memory allocation schemes and discuss the performance issues. Explain in detail about cache coherence problem and brief possible solution for it. What is virtual channel? How it avoids the deadlock? Explain. Explain briefly about the three vector access memory scheme. Draw and explain the architecture of connection machine CM-2. What is shared virtual memory? Why it is become necessity in building a scalable system? Explain. Describe the KSR-1 Architecture in detail. Explain briefly about the basic design issues of instruction level parallelism. Draw and explain a state transition diagram of 2-bit branch predictor. Write a short note on: Semiconductor memories. Storage technology.

3

4

(a) (b) (a) (b) (a) (b)

5

6

7

(a) (b)

8 (a) (b)

*****