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# Lecture 7. D.C.-D.C.

conversion (2): boost converter
In this lecture:
5.1. 5.2. 5.3. 5.4. operation Input/output characteristic Edge jitter Design Example

The boost converter is very useful for stepping d.c. voltages up: that is, for producing output voltages higher than the input voltage. As before, assume that the components are all ideal, and the JFET switches with a period of T. The duty cycle is D=ton/T.

Mode 1 – JFET switch closed
Assume the capacitor is initially charged. When the switch is closed, it shorts point A to ground: VA=0, the diode does not conduct and we get two loops.
iL + Vin L A

L vL

A

iC

5.1. Operation
+ Vin -

vC

C

vout

JFET Switch

C

+ vout -

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In loop 1, the Vin energises the inductor: the current in the inductor climbs linearly, with a slope depending on the value of L:
di Vin ≈ L L dt di V ⇒ L ≈ in constant L dt

Remember! • For sufficiently high C and R the vout falloff is very small. • The decay is approximately linear for a short time (compared to the RC time-constant).

Mode 2 – JFET Switch Open
L A iL iC C iR Rload vout>Vin

Meanwhile in loop 2 the charged capacitor slowly discharges into the load, maintaining a (very slowlydecaying) voltage across the load.
iout = −iC , vout = vC vout dv = −C out R dt dvout − vout − vout = ≈ dt RC RC ⇒
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+ Vin -

vL<0

With the switch open, the node A floats back up to a positive voltage and the diode conducts current.

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EE301 GB06 Page 5 therefore EE301 GB06 Page 6 vout T 1 = = Vin T − t on 1 − D So vOUT is greater than Vin. then power is delivered steadily over the whole period: E in = Vin i L T Energy out. producing a positive iL with a negative voltage vL: • a very large voltage. Edge jitter Edge jitter is the uncertainty in the output voltage level due to noise or uncertainty in the timing of the clock signal to the switch.3. when the switch is off. consider the energy in and out. E out = vout i L (T − t on ) Taking E out = E in gives vout i L (T − t on ) = Vin i LT If T is kept sufficiently short then the current ripple is acceptably small. a switching failure could cause disaster! The inductor voltage can be very large. Since the inductor current is fairly steady. and changes rapidly between positive and negative. In particular. What is the edge jitter‘s effect on output voltage? EE301 GB06 Page 7 EE301 GB06 Page 8 . Notes The battery can not be left too long energising the inductor.75. that is. • The large voltage also re-charges C. Example Consider a boost converter with • Switching frequency = 100 kHz • Edge jitter = ±100 ns • Vin = 10 V. v out = v C = Vin − v L = Vin + v L > Vin Since VL<0 is constant and negative. This is called jitter.The inductor de-energises: • it acts as a source. 5. In this way we can boost the output voltage compared to the input voltage. the rise and fall times of a square clock signal are often inexact: the edges of the square wave may occur slightly earlier or later than they ideally should. Input/output characteristic To find out the relationship between vout and Vin. Vin-vL. This can lead to unwanted electromagnetic emissions. input voltage source. the resulting current in the inductor decreases gradually between t=ton and t=T: 5. D = 0. Every signal has some uncertainty or noise.C. For this reason. is thus dropped across R. Energy reaches the load and capacitor only when the diode conducts. Energy in. larger than Vin.2. All energy into the circuit comes from the D. Even a small jitter in a switching converter can lead to large errors in output voltage.

02=8mA.) = 10⎜ ⎟ = 38.1 ⎞ v out (max.Solution Right away. Examine the range of values vout may take.1µs: ⎛ 10 ⎞ v out (nominal) = 10⎜ ⎟ = 40V ⎝ 2 . Design Example Design a Boost Converter such that a 5V input is scaled to 15V.1V ⎝ 2 .) = 10⎜ ⎟ = 42.5 + 0. Edge jitter (or timing jitter) is a particular problem when the scaling ratio is large. tOFF = 2. Vin = 10V. given that both T and toff may differ by up to 0. Switching period: T = 1 / f = 15µs We need an output voltage of 15V from an input of 5V. The output load power is 6W. the maximum permissible ripple (2%) is 0. 2.5µs ± 100 ns (=0. Input current ripple and the inductor The average input current can be determined by the output load power Pout = v out i out ⇒ i out = 6 / 15 = 0.4x0.7 kHz and you main assume that timing jitter is not significant.5 − 0 . we find T = 10 µs. So 100ns edge jitter represents only 1% of T.1 ⎠ EE301 GB06 Page 9 EE301 GB06 Page 10 5.4A.1 ⎞ v out (min.1 µs) v out = Vin T 1 = Vin t OFF 1− D • A large scaling ratio corresponds to a small toff. • So the buck and boost converters are most reliable when the duty ratio D is small. thus the switch-off time toff is given by v out = Vin T t OFF v L = Vi = L giving diL ∆I ≈L L dt t on V ⇒ t OFF = i T = 1 T = 5µs 3 Vo T − t off 10 t = = 66% And D = on = T T 15 EE301 GB06 Page 11 L= t on Vi ∆i L Recall the maximum permissible current ripple is ∆i L max = 8 mA .4. with no more than a 50mV ripple on the output and an input current ripple of no more than 2%. Duty ratio With an average output current of 0.5 ⎠ ⎛ 10 + 0. leading to a bigger output voltage uncertainty. so we require EE301 GB06 Page 12 . a jitter of ±∆t then is then proportionally bigger.1 ⎠ ⎛ 10 − 0.1V ⎝ 2.4 A Solution 1. recall that while the switch is closed (mode 1). Thus a 1% error in the timing signal results in a 4V (=10%) swing in the output voltage – quite a large output error. The switching frequency is 66. To find a value of L that permits this.

25 mH 8 × 10 −3 In mode 1 (0<t<ton). the bigger the required inductor. Output voltage ripple and the capacitor (15 − 5) × 10 −6 > × 5 = 6. and guarantees a smaller ripple current. converter that is capable of voltages smaller or bigger than the input voltage.C. In this way. The capacitor discharges slightly.C. Assuming the current falls linearly allows us to write So a larger inductor can store more energy during ton. iC ≈ C ∆vC ∆v = C out ∆t t ON Rearranging gives C = iC t ON ∆v out We require C such that ∆v out (max) = 50 mV . the smaller the demanded ripple. demanding an even bigger inductor. maintaining the output voltage (approximately). then a 2% ripple tolerance would represent an even smaller ∆IL.. the charged capacitor supplies energy to the load. gives us the following circuit: 10 mH D = 66% toff = 5µs C L = 100µF = 10mH + Vin - A toff =5µs 100 µF Rload vout In the next lecture we will see a D.4 ) = 80 µF ∆vout max 50 × 10 −3 EE301 GB06 Page 13 EE301 GB06 Page 14 We have now defined all the components we need. comfortably above their minima. If the load current were smaller. END OF LECTURE EE301 GB06 Page 15 . so just picking values that satisfy these constraints. in other words C > iC t ON 10 × 10 −6 = (0. and its voltage falls by a small amount.L> ton Vi ∆iL max 3.D.