Direct Memory Access (DMA) What is DMA?

A facility o transfer data from memory to memory o / memory to peripheral o memory and peripherals can be internal / external o no intervention of CPU o DMA controller takes care of memory transfer • DMA has 6 channels for memory transfer o Each channel connects to a source location and destination location o Total 6 source and destination locations can be connected o Single transfer at a time o High priority channel is serviced before a low priority channel o For same priority it is serviced in a circular way 2,3,4,5,0,1 o Transfer in terms of blocks of data o Block contains frames o For internal memories 4 clock cycles o 2 read + 2 write DMA Operation Configuration • Prior to transfer sub bank addressed registers have to be configured o Which channel? o Source and destination address o Priorities and enabling of channels with DMPREC register 16 bit o Size of the block DMA Sub bank Addressed Registers Name Address Sub Addr Description DMSRC0 56h/57h 00h DMA channel 0 source address register DMDST0 56h/57h 01h DMA channel 0 destination address register DMCTR0 56h/57h 02h DMA channel 0 element count register DMSFC0 56h/57h 03h DMA channel 0 sync select and frame count register DMMCR0 56h/57h 04h DMA channel 0 transfer mode control register DMSRC1 ……….. DMSRCP 56h/57h 1Eh DMA source program page address (common channel) • 5 registers for each channel • Total 30 registers for 6 channels • +other control registers • Total 62 registers Register Sub addressing • Technique used for configuring the DMA registers • Intervention of CPU required • Code for configuration is loaded into access registers DMSDI or DMSDN • Sub address to be configured is loaded into DMSA • DMSDI is auto-incremented • DMSDI for entire sets of registers • DMSDN for a single register access •

SUBBANK DMSDI ACCESS REGISTERS DMSDN

Sub-addressed Registers

DMSA SUBBANK ADDRESS REGISTER Example Program 1: Write code to show how the DMA channel 2 source address register can be initialized with the value 1111h. Following program is simulated in CCS: ; Program name ex9p6.s .def _c_int00 dmsa .set 55h ; address of subbank address register dmsdn .set 57h ; address of subbank access register dmsrc2 .set 0ah ; subaddress .text _c_int00: stm dmsrc2, dmsa ; DMSA= address of DMSRC2= 0Ah stm #1111h, dmsdn ; write 1111h to DMSRC2 .end After execution: Peripheral register DMSA=000A DMPREC =0000h Example Program 2: Write TMS320C54xx code to show how the DMA channel 5 context registers can be initialized. Choose arbitrary values to be written to the registers. Solution: Since a set of registers are to be configured DMSDI is used. DMSA .set 55h ; address of subank address register DMSDI .set 56h ; address of subbank access register DMSRC5 .set 19h ; subaddress of DMSRC5 DMDST5 .set 1Ah DMCTR5 .set 1Bh DMSFC5 .set 1Ch DMMCR5 .set 1Dh STM DMSRC5, DMSA ; DMSA= first sub address STM #2000h, DMSDI ; write 2000h to DMSRC5 STM #3000h, DMSDI ; write 3000h to DMDST5 STM #0010h, DMSDI ; write 0010h to DMCTR5 STM #0002h, DMSDI ; write 2h to DMSFC5 STM #0000h, DMSDI ; write 0h to DMMCR5 Example 3: Write a TMS320C54xx code to transfer a block of data from the program memory to the data memory. Following are the specifications:

Source address: 26000h in program space (extended memory page 2) Destination address: 07000h in data space Transfer size: 1000h single (16-bit) words Channel use: DMA channel #0 Solution: DMA registers should be defined with appropriate directives STM DMSRCP, DMSA ; set source program page STM #2h, DMSDN STM DMSRC0, DMSA ; channel 0 to be used STM #6000h, DMSDI ; source program address is set to 6000h ; DMSA points to DMDST0 after transfer STM #7000h, DMSDI ; set destination address to 7000h ; after transfer DMSA points to DMCTR0 STM #(1000h-1), DMSDI ; set for 1000h transfers ; DMSA points to DMSFC0 STM #00000h, DMSDI ; Configure DMSFC0 ; DMSA points to DMMCR0 STM #00105h, DMSDI ; configure DMMCR0 ; DMSA points to DMSRC0 STM #00101h, DMPREC ; configure DMPREC