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Architecture of 8085 Microprocessor
Architecture reveals the internal logic of a microprocessor. The 8085 architecture comprises of the following blocks: 1. ALU logic 2. Register logic 3. Timing and Execution logic 4. Interrupt logic 5. Serial I/O logic 1. ALU Logic: The Arithmetic and Logic Unit performs arithmetic and logic operations. It comprises of the accumulator, temporary registers, flag register and arithmetic and logic circuits Accumulator: • It is an 8-bit register • Stores one of the operands during arithmetic and logic operations • Stores result of the operation Temporary Register: • It is used to hold another operand during arithmetic and logic operations. • It is not accessible to the programmer Flag Register: • It is an 8-bit register • It makes use of only five bits, each one is called a flag • They reflect the result of an arithmetic or logic operation S Z X
C X – don’t care
Sign(S) flag: set/reset after the execution of an arithmetic or logic operation 1 (set) – if bit d7 of result is 1 (negative number) 0 (reset) – if bit d7 of result is 0 (positive number) Zero(Z) flag: set/reset after the execution of an arithmetic or logic operation 1 – result is zero 0 – result is non – zero Auxiliary Carry(AC) flag: set/reset after the execution of an arithmetic or logic operation 1 – if carry is generated by bit d3 0 – if there is no carry out of bit d3 It is used internally for BCD operations and is not available to the programmer Parity(P) flag: set/reset after the execution of an arithmetic or logic operation 1 – Even number of 1s in the result
It is always pointing to the memory address from where the next byte is to be fetched Stack Pointer (SP): This is a pointer register. D. Its always pointing to the top of the stack. and L Some of them are used in combination to form 16-bit register pairs. E. OR. DE and HL 2. H. General Purpose registers: These are the ones that are accessible to the programmer. PC and SP are 16-bit registers. subtraction. They are broadly classified as – 1. Special function registers 1. General purpose registers 2. The following combinations are possible – BC.By Ashish Dixit Asst. B. EXOR & NOT 2. C.S. Timing and Execution logic: Instruction Register The instruction Register holds the instruction fetched from memory The Instruction Decoder decodes the instruction in the Instruction Register and passed relevant information to the timing and control unit Timing and Control Unit synchronizes microprocessor operations with the clock generates the control signals necessary communication between microprocessor peripherals all and for and Instruction Decoder Timing and Control Unit 2 .E) 0 – Odd number of 1s in the result Carry(C) flag: set/reset after the execution of an arithmetic or logic operation 1 – if an arithmetic operation results in carry/borrow 0 – if no carry/borrow The ALU of 8085 provides Arithmetic operations – Addition. Program Counter (PC): This is used for sequencing the execution of instructions. Register Logic: This logic provides a set of registers and the circuits for accessing these registers. They are 8-bit registers – A. Special Function registers: Specific functions are assigned to the registers in this group. incrementing and decrementing operations Logical operations – AND.prof.(C.
and INTR One signal called Interrupt acknowledge (INTA) is an output signal. RST 7. This is to acknowledge the acceptance to service the interrupt.E) Interrupt Logic: This logic supports 5 interrupts with the following features: • Priority • Masking and Non-masking • Vectoring and Non-vectoring The five interrupt signals are: TRAP. RST 5.5.5. 3 .prof. RST 6.5.(C.By Ashish Dixit Asst.S. Serial I/O Logic: This logic supports serial communication with the help of 2 signals: SID (input) and SOD (output).
(C.5 TRAP RST 7.5 SID SOD Interrupt Control 8-bit internal data bus Accumulator Temp. Reg.By Ashish Dixit Asst.S.prof.5 INTR RST 6. IR MUX W Z C E L B D H Flags Instruction Decoder & m/c cycle encoding Stack Pointer Program Counter Inc/Dec Address Latch ALU X0 X1 CLK GEN Timing and Control Control Status DMA Reset Address Buffer Data/adr Buffer A15 – A8 Address Bus Clk out RD READY WR ALE S0 S1 IO/M HOLD HLDA RESET OUT AD0 – AD7 Address/Data Bus RESET IN 4 .E) INTA RST 5.
5 RST 6.By Ashish Dixit Asst.S.E) 8085 Pin Details: VCC Interrupt Signals Address Bus DMA Signals Serial I/O Signals Timing and Synchronization Signals VSS 8085 µp Address/Data Bus Control & Status Signals TRAP RST 7.prof.5 INTR INTA A8 – A15 AD0 – AD7 HOLD HLDA READY RESETIN RESETOUT CRYSTAL CLOCKOUT 8085 µp RD WR IO/ M ALE S0 S1 SID SOD The 8085 microprocessor: • Is a 40 pin LSI chip • Is 8 – bit general purpose microprocessor with addressing capacity of 64K • Operates with 3MHz single phase clock The 8085 signal are grouped as follows: 5 .5 RST 5.(C.
used to differentiate between I/O and memory operation.By Ashish Dixit Asst. This signal indicates that the data on the data bus is to be written into the selected memory or I/O location. S0 – These signals along with IO/ M are used to identify various operations of microprocessor. (b) Status Signals: * IO/ M . 7. 2.prof. 6 . 3. Address bus Address/data bus Control and status signals Interrupt signals DMA signals Timing and synchronization signals Serial I/O signals Power supply (1) Address signals: A15 – A8 These signals form the higher order address lines (2) Address/Data signals: AD7 – AD0 This is a time multiplexed address and data bus used for carrying both • lower order address signals • Data signal at different time intervals Address bus is unidirectional and data bus is bidirectional (3) Control and Status signals: (a) Control Signals: * RD . 6. 4. HOLD – This signal indicates a peripheral such as DMA controller is requesting for the use of address and data bus. * WR . It is used to demultiplex the multiplexed lower order address and data bus. * ALE – This signal is generated during the first clock period of every machine cycle. 8. (4) Interrupt Signals: An interrupt is a request to the microprocessor to suspend the execution of the main program temporarily and execute another program called Interrupt Service Routine (ISR) corresponding to a device which has requested microprocessor through any of the e5 interrupt lines.(C.E) 1. INTA is acknowledgement to a maskable interrupt.This is an active low signal.This is also an active low signal. 5.S. This signal indicates that selected I/O or memory device is to be read and that the data is available on the data lines. 1 – I/O operation 0 – Memory operation * S1. (5) DMA Signals: DMA (Direct Memory Access) is the process of transferring data from the I/O device to memory without the interference of the microprocessor. We must keep in mind that for initiating the DMA process microprocessor is needed.
By Ashish Dixit Asst. 7 . * READY – This input signal is used to delay the microprocessor read/write cycles until an I/O device is ready to send/accept data. * RESET OUT – This signal indicates that the microprocessor is reset and can be used to reset other devices.(C. (7) Serial I/O signals: * SID – serial input data: The data on this line is loaded into accumulator bit – 7 whenever a RIM instruction is executed. * SOD – Serial output data: This line is set or reset as specified by the SIM instruction. * X1 and X2 – The crystal is connected across these pins. buses are tristated and microprocessor is reset. These two signals are used to establish serial communication between the microprocessor and external serial I/O devices. The frequency is internally divide by 2.prof. the program counter is set to 0.+5V Power supply VSS – ground reference Microprocessor Communication and Bus Timings: We have to examine the process of communication between the microprocessor and memory to understand the functions of various signals. to operate a system at 3MHz.when the signal on this pin goes low. It can be better understood through timing diagram as shown below.S. The first step in the communication process is reading from memory or fetching an instruction. the crystal must have a frequency of 6MKz. * CLKOUT – This signal can be used as system clock for other devices. We need to understand timings of various signals in relation to the system clock. This process is called fetch cycle. (8) Power supply signals: VCC . (6) Timing and synchronization signals: * RESETIN . Thus.E) HLDA – This output signal acknowledges the HOLD request.
The status signal IO/M goes low.E) Data Bus 4F Internal Data Bus Memory 2000 B ALU Instruction Decoder C E L 2005 4F 2005 D H Stack Pointer Program Counter Contr ol Logic RD Address Bus 4F Consider the example of fetching the machine code of instruction MOV C. indicating this is a memory-related operation. The RD signal causes 4F to be placed on the multiplexed bus and when RD goes high. the instruction byte (4F) is placed on the bus AD7 – AD0 and transferred to the microprocessor. The instruction decoder decodes the machine code and the contents of the accumulator are copied into register C. 8 . and ALE signal goes high.(C. it causes the bus to go into high impedance Step4: The byte is placed in the instruction decoder of the microprocessor and the task is carried out according to the instruction. the lower order address 05H is placed on the bus AD7AD0. Step2: The control unit sends the control signal RD to enable the memory chip The control signal RD is sent out during the clock period T2.S.By Ashish Dixit Asst. This signal is active for two clock periods. thus enabling the memory chip. In Timing diagram. This task is performed during periodT4. When the memory is enabled. during the T-state T1 the higher order memory address 20H is placed on the address lines A15-A8. Step3: The byte from the memory location is placed on the data bus.prof. A (0100 1111 = 4F) stored at the address 2005 Step1: Program Counter places the 16-bit memory address on the address bus.
the latch is transparent and output changes according to input. When ALE goes low.By Ashish Dixit Asst.(C. When ALE is high. If the bus AD7 – AD0 is used to identify the memory location 2005H. demultiplexing AD7 – AD0 becomes apparent. The following figure shows a schematic that uses a latch and ALE signal to demultiplex the bus. the data byte 05H is latched until next ALE. 9 . It clearly shows that. the output of the latch is 05H. During T1. lower order address (05H) is lost after the first clock period.prof. ALE goes high during T1. the address will change to 204FH after the first clock period.S.E) Demultiplexing the Bus AD7 – AD0: If we observe the timing diagram above. The ALE signal is connected to the enable pin of the latch and the output control signal of latch is grounded. The bus AD7 – AD0 is connected as the input to the latch 74LS373. This address needs to be latched and used for identifying the memory address. And the output of latch represents the lower order address bus A7 – A0.
Now. fetching.prof.S.E) Some definitions: After carefully observing timing diagram of instruction fetch shown above. 8085 has instructions which consume one to six machine cycles. I/O. or acknowledging an external request. we can make following observations: 1) The machine code 4FH is one-byte instruction that copies the contents of the accumulator into register C 2) The 8085 microprocessor requires one external operation – fetching the machine code from memory location 2005h 3) The entire operation. 2) Machine Cycle – it is defined as the time required to complete one operation of accessing memory. This cycle may consists of three to six T-states 10 .By Ashish Dixit Asst. decoding and executing requires four clock periods. we can define following terms: 1) Instruction cycle – it is the time required to complete the execution of an instruction.(C.
prof. In high impedance state. the device functions the same way as ordinary logic devices.(C. practically no current is drawn from the system. 11 .By Ashish Dixit Asst. When this line is activated.S. the logic device goes into high impedance state – as if it were disconnected from the system.E) 3) T – state – It is defined as one subdivision of the operation performed in one clock period. The term TRI – STATE is a trade mark of National Semiconductor and is used to represent three logic states. Tristate Devices: Tri-state logic devices have three stages: logic 1. Ordinarily. current is required to drive a device in logic 0 or logic 1 states. These subdivisions are internal states synchronized with the system clock and each T – state is precisely equal to one clock period. When this third line is disabled. logic 0 and high impedance. A tri-state device has has a third line called enable.