An integrated low power buck converter with a

comparator controlled low-side switch

Reinhard Enne and Horst Zimmermann
Institute of Electrodynamics, Microwave and Circuit Engineering
Vienna University of Technology, Gusshausstr. 25/354, 1040 Vienna, Austria
Email: and

Abstract—Here the design of an integrated buck-converter leg is
presented in which the free-wheeling diode is replaced by a
comparator controlled N-MOSFET. This allows eliminating the
efficiency reducing voltage drop at the diode while the
discontinuous conducting mode (DCM) is still applicable. For this
issue, besides the control block also a fast comparator with a
special offset reduction circuit is presented. A layout for a
converter bridge was done and simulated which is optimized for
the best efficiency at a statistically often used point of operation
(3.3V output, 27.5% duty ratio, 1MHz, 170mA).
Keywords: CMOS buck converter; low offset comparator;
synchronous rectification; discontinuous conduction mode;
In the last years low-drop-out (LDO) regulators have been
replaced more and more by buck converters even at low power.
The reason for that is the higher efficiency and lower heat
production of these switched-mode converters although it
induces the demand for additional external inductors and
diodes [1]. For lower output voltages and higher input voltages
the forward voltage of the free-wheeling diode causes more
and more losses, so that the efficiency decreases. Replacing the
diode by a further MOSFET which is driven inversely to the
upper one, makes that the voltage drop in the free-wheeling
path is ohmic with the effect of a higher efficiency. This
control method is called synchronous rectification. The
drawback is that this forces the continuous conduction mode
(CCM) at every load point, and the more efficient
discontinuous conduction mode (DCM) at light load is
excluded. In the following a comparator based controlled
bridge leg is presented which has its free-wheeling path via a
MOSFET and is switching automatically between DCM and
CCM. In the following, the main parts of the converter are
described in more detail.
Figure 1 illustrates the internal structure of the presented
converter. At the input side the pulse generator generates the
control pulses for the zero voltage comparator (ZVC), the level
shifter and the low side control circuit from a PWM modulated
rectangular signal. It generates a pulse ‘MH on’ when
a rising edge is detected and a pulse ‘MH off’ for the falling
edge, as a blocking signal for the lower MOSFET to prevent a
shoot-through. Furthermore it restricts the minimal pulse width
to prevent undefined states of the converter, which may
Figure 1. Internal structure of the converter leg
destroy it. The level shifter [2] transforms the voltage level of
the control signals so that the high gate voltage p-channel
MOSFET MH can be controlled. For the control and driving of
the low side NMOS switch (ML) the function blocks ZVS
comp, ML control and the driver are responsible. While the
zero voltage comparator measures the current direction through
the lower transistor by the use of it’s on resistance, ML control
prevents the positive feedback loop which may cause an
uncontrolled switching of ML in DCM.
All function blocks in the dotted box in Fig. 1 are realized
on chip in a 0.35µm high-voltage CMOS technology and
isolated from the substrate by an N-well. The filter inductor
and capacitor as well as the load are assumed to be external.
The zero voltage comparator measures the drain-to-source
voltage of the low side power N-MOSFET to detect its current
direction for control: When current is flowing out from the
drain of ML it should be low-ohmic and when current is
flowing from the load into the drain ML should get a switch-
off signal. To detect also small reverse currents the offset
voltage of the comparator has to be as small as possible, while
a small time delay is important for correct operation of the
bridge leg.
As it can be seen in Fig. 2 the basic circuit is this of a
differential amplifier with the differential input stage formed
by the transistors M1, M2, M8, M9, M10 and two single ended
amplification stages formed by M3, M7 and M4, M6. To
protect the gate of M10 against high input voltages, R1 and
M11 are inserted. So the gate-to-source voltage of M10 is
bordered nearly to the threshold voltage of M11 in the positive
direction and to the flow voltage of the parasitic drain-to-bulk
978-1-4244-6610-8/10/$26.00 ©2010 IEEE 84
Figure 2. Zero voltage comparator with auto zero extension (gray)
diode in the negative direction. From this initial set-up a trade-
off between energy loss, offset voltage and speed would have
to be done:
 Low loss of protection circuit: R1 should by high-
 Small offset voltage requires a good matching of
the input differential stage: M9, M10, M1, M2
should have large gate areas
 High speed: the time constant R1*C
should be small
For example, in the given technology a 3-sigma threshold-
matching would require transistors with a gate area of about
500µm². In combination with R1=28kΩ this would lead to an
inacceptable time constant of M10’s gate node of 670ns which
is more than the half assumed PWM period. In the following,
therefore, a method for low offset voltage and small transistor
areas for high-speed operation is introduced.
A. Auto Zero Extension
An insertion of the two switches SW1, SW2, the transistor
M12, and the capacitor C1 makes this circuit auto zero capable
(gray parts in Fig. 2). Additionally the differential input stage
has to be built asymmetric in such a way that M1 has a smaller
width than M2. This results in an offset voltage which makes
the comparator switching at an input voltage less than 0. A
drain current of M12 pulls this offset in the positive direction.
When the switches SW1 and SW2 are in the position as in Fig.
2, the circuit is in comparator mode. An auto zero cycle is
performed, when the switches are in the other position: Then
SW1 connects the gate of M10 with GND, so that the input
voltage of the differential amplifier stage is zero. SW2
connects the drain node of M3 with the gate node of the
calibration transistor M12, in order to form a negative feedback
through the differential input stage and the preamplifier (M3,
M7). This ensures that all MOSFETs of the input stage and the
preamplifier are in active mode, when the input voltage is zero.
Also the gate node of M4 is slightly above the threshold
voltage. The capacitor C1 is used to keep this bias point when
the comparator is switched back to the comparator mode till the
next auto-zero cycle is performed. A direct connection of C1
and the gate of M12 would induce an oscillatory action into the
circuit when it is in auto zero state, what would result in long
settling times. The insertion of R2 damps this behavior.
B. Monte Carlo Simulaton of Offset Voltage
For the evaluation of this auto zero concept Monte Carlo
simulations were done for a circuit with a symmetrical input
stage without calibration and one with the described method.
The dimensions of the significant parts are listed in Tab. I,
while R1 is 285kΩ in both circuits. As test signal a saw tooth
voltage from -200mV to 144mV and a period of 2.5µs was
used, while the offset voltage was seen as the input voltage
when the output voltage is 1.65V. To simulate the output load
two logic gates were connected to both comparators. With this
setup a typical current demand of 25µA for each comparator
resulted at 3.3V supply voltage. The output transition time was
2.7ns (10%-90%).
The statistical analysis was done with 500 runs whereby
matching and process variation was simulated. Fig. 3 shows the
distribution graphs of the offset voltage. As it can be seen the
expectancy value of the offset voltage at the symmetrical
circuit of -4.191mV is improved through the auto zero
extension by the factor 12 to roughly 340µV. Of course this
mean value could also be improved by a slightly smaller width
of M1 than M2. More important is the reduction of the offset
voltage variance which is improved by the factor 2.8 without
any drawback in speed.
Figure 3. Offset voltage distribution of the symmetric and auto-zero
extended circuit
MOSFET dimensions width(um)/length(um)
Symmetrical circuit Auto zero circuit
M1 , M2 2.4/0.45 , 2.4/0.45 1.8/0.45 , 2.4/0.45
M9 , M10 1/0.35 , 1/0.35 1/0.35 , 1/0.35
M12 - 2/5
Fig.4 shows the simulated transient response of the
converter when it is in DCM. The test setup is the same like for
the efficiency simulations (Fig. 6). When the bridge output
voltage, which is equivalent to the drain-to-source voltage of
the low-side valve is below zero, which means that current is
flowing out of the drain, the zero voltage comparator detects
this, the lower MOSFET (ML) is switched on and the output
current is carried by ML. At the time point 23.48µs the output
current is crossing zero and makes ML to be switched off.
Caused by ML’s Miller capacitance, its drain potential is
dropping while the switch-off transition is happening. By the
ZVC this is incorrectly detected as a further switch-on case.
Moreover, when the current through the lower valve stalls, its
drain voltage begins to oscillate caused by the resonant circuit,
which is formed by the filter reactor and the parasitic
capacitance of the bridge output node. At some conditions the
output voltage swings back below zero, so that a further
incorrect switch-on command is generated.
Besides the fact that a direct control of the low side
MOSFET by the comparator could cause instability, every
additional switching cycle wastes energy and has to be
suspended. This is done by a flip flop in the ML control block,
whose internal structure is shown in Fig. 5. The flip flop is
cleared when the upper power MOSFET is switched off, and
set when the first zero-crossing of the current from positive to
negative is detected. Then it forces ML to be switched off and
blocks all further signals from the ZVC. When the high side
MOSFET is on, the low side is also blocked.
For dimensioning the power section of the converter the
significant part of the loss is assumed to be in the gate driver of
the power MOSFETs and in their on-resistance. The power loss
in the gate drivers is given by (1), where e
, e
are the
amounts of energy which are used to switch on the power
MOSFETs, related to their widths w
, w
while f means the
switching frequency. Equation (2) estimates the ohmic loss in
the power stage in CCM, while r
and r
represent the
on-resistances related to the widths, I means the mean output
current and δ is the duty ratio.
= ¡ · (c
· w
· w
) (1)
= I
· j
· o +
· (1 -o)[ (2)
In minimizing the sum of these two loss terms the optimal
transistor widths for a certain output current and duty ratio are
given by (3) and (4), while the maximum efficiency is
estimated by (5), whereby U
means the output voltage.
= I · _
= I · _
= _1 +2 ·
· |¸o · r
· c
¸(1 -o) · r
· c
Figure 4. Transient response of the DC/DC converter in discontinuous
conduction mode
Figure 5. Structure of the ML control block

Tab. II shows the used values for which the proposed
converter is optimized. The combination of the duty ratio of
0.275 and 3.3V output voltage assumes an input voltage of
about 12V and which is an often used conversion ratio in
automotive applications, where most electronic control units
work at 3.3V.
For efficiency simulations the setup illustrated in Fig. 6 was
used. It is mainly built up by the signal generator, the converter
chip, the filter and the load resistor. The bond wires are
represented by the inductors in the range from 2nH to 6nH. For
internal chip parasitics simplified values from the post layout
extraction were used. All simulations were done at 12V input
and 3.3V load voltage while the control signals were varied.
For efficiency calculations the averaged power dissipated in the
load was put in relation with the averaged electrical powers
supplied by the 3.3V and 12V net.
Two types of simulations were done, whose resulting
efficiency graphs are illustrated in Fig. 8 as load current
dependent efficiency map.
Point of operation MOSFET sizes



0.275 3.3 1 170
a. Chosen size

Figure 6. Circuit for efficiency simulation
The first one is the characterization for the PWM mode at
1MHz at continuous conduction mode and discontinuous
conduction mode. Here the duty cycle was varied between 0.05
and 0.35, and the converter switched automatically between
DCM and CCM at about 60mA load. While the CCM part of
the graph has a smooth trend the DCM part has some local
maxima in efficiency. This is because of the oscillation of the
converter output (see Fig. 4): at some certain duty ratios the
output voltage has its maximum when the high-side MOSFET
is switched on, so its switch-on transition produces lower
losses. Such effects can be used for further efficiency
improvements [4]. In PWM mode the efficiency remains above
90% from 70mA load current up to 400mA. The maximum of
93% is at 176mA which roughly fits to the chosen value of
170mA. Because of the fact that the MOSFETs do not switch
infinitely fast, the loss through the metal resistance and the
power consumption of the internal control, the proposed value
from Tab II cannot be reached.
The second characterization was done for pulse repetition
modulation (PRM) of 285ns pulses with repetition rates from
100kHz to 1.2MHz. While for I>170mA the efficiency is
nearly the same like for PWM in CCM, it remains above 90%
towards low output currents. So PRM makes a matching of the
driver power consumption to the load with the drawback that
the non-constant switching frequency can be a disadvantage in
some applications.
This paper discusses the design of a diode-less buck
converter with a comparator-controlled low-side power
MOSFET, which switches automatically from CCM to DCM at
light loads, in such a way that electrical power cannot flow
back from the load. Because of its control structure the
presented converter is able to be controlled with PRM, which
delivers high efficiency in a larger load range. In a multi-phase
converter structure it may reduce reverse currents [3]. The key
component of the control circuit is a fast low-offset

Figure 7. Efficiency plot considering parasitics from post-layout extraction
comparator (ZVC), which uses the presented simple offset
reduction extension. Monte Carlo simulations have shown that
this small extension reduces the mean value of the offset
voltage by the factor 12 and the offset variance by the factor
2.8 without any drawback in speed. All layouts and simulations
were done with the design kit of a standard 0.35µm HV-CMOS
process. Concerning the power stage layout it is shown that a
simple size optimization rule, which just concentrates on well-
known technology factors, is sufficient to optimize it for a
certain commonly used operation point. The technology factors
can be found via simulations. For the investigated chip layout a
silicon area of 850μm x 1100μm was necessary in which the
ZVC circuit (Fig.2) took 70μm x 35μm.
The authors thank austriamicrosystems AG and especially
H. Gall for supporting the necessary work for this paper.
Financial funding from the Austrian BMVIT via FFG and the
ENIAC joint undertaking in the project E3CAR is

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