Siddaganga Institute of Technology, Tumkur – 572 103

(An Autonomous Institution under Visvesvaraya Technological University, Belgaum)

VI Semester BE Electronics & Communication FEB-2012
Subject USN : : VLSI Design [EC65] All Assignment-2 Section : B

1

The output of an nFET is used to drive the gate of another nFET as shown in fig 2.1. Assume that Vdd = 3.3V and Vtn = 0.60V. Find the output voltage Vout when the input voltages are at the following values a) Va = 3.3V and Vb = 3.3V; b) Va = 0.5V and Vb = 3.0V; c) Va = 2.0V and Vb = 2.5V; d) Va = 3.3V and Vb = 1.8V.

Fig 2.1 2 Design a NAND 3 gate using an 8:1 MUX

3

Design a NOR 3 gate using an 8:1 MUX

4

Consider the 2-input XOR function a) Design an XOR gate using a 4:1 mux b) Modify the circuit of (a) to produce a 2-input XNOR. c) A full adder accepts inputs a, b and c and calculates the sum bit a (xor) b (xor) c Use your MUX- based gates to design a circuit with this output.

3 a) Construct the nFET array using the logic diagram. Fig 2.5 Design a CMOS logic gate for the function F = a. b) Apply bubble pushing to obtain the pFET logic.3 . Then construct the pFET array using rules.2.2 7 An AOAI logic gate is described by the schematic in fig 2. Use the diagram to construct the pFET rules. complex logic CMOS gate is to be designed for F.b + ac + bd Using smallest number of transistors. 6 Consider the logic described by the diagram in fig 2. Fig 2. A single. b) Apply bubble pushing to obtain the pFET logic. a) Construct the nFET array using the logic diagram.

2. 8 by using TG switches 10 Use an AOI22 gate to design a 2:1 MUX.5 for the following input voltage values a) Vin = 2V b) Vin = 4. Then construct the nFET circuit.8 A pFET logic array is shown in fig 2. Inverters are permitted in your design 11 Design a 4:1 MUX using three 2:1 TG multiplexers.7V.7V Fig.5V c) Vin = 3.4 9 Design the 4:1 multiplexor circuit that implements the function in equation of problem no. Fig 2.5 .5V d) Vin = 0. Find the output voltage Vout of the nFET in Fig 2. 12 Suppose that Vdd = 5V and Vtn = 0. Construct the logic diagram using the pFET logic equations.4.

2.6 Design a CMOS circuit for the OAI expression H = ((a + b ) ⋅ (a + c ) ⋅ (b + d )) 14 Use smallest number of transistors in your design Design a CMOS logic circuit that implements F = a + b ⋅ c + abc Using series-parallel logic.FET chain in fig 2.6.55V. The power supply is set to a value of Vdd = 3.13 Consider the two.0V c) Vin = 1. The objective is to minimize the transistor count Construct a CMOS logic gate for the function G = x ⋅ ( y + z ) + y start with the minimum-transistor nFET network.4V d) Vin = 3. 15 16 .3V and the nFET threshold voltage is Vtn = 0. and then apply bubble pushing to find the pFET wiring.1V. Fig. Find the output voltage Vout at the right side of the chain for the following values of Vin a) Vin = 2.9V b) Vin = 3.

Sign up to vote on this title
UsefulNot useful

Master Your Semester with Scribd & The New York Times

Special offer for students: Only $4.99/month.

Master Your Semester with a Special Offer from Scribd & The New York Times

Cancel anytime.