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A.Kamaraj

Asst. Prof/ECE Mepco Schlenk Engineering College, Sivakasi.

P.Nithya Kalyani

Final Year ECE Mepco Schlenk Engineering College, Sivakasi.

M.Muthu Lakshmi

Final Year ECE Mepco Schlenk Engineering College, Sivakasi.

Abstract— Reversible logic is emerging as an important research area in the recent years due to its ability to reduce the power dissipation, which is the main requirement in low power digital design. Energy dissipation is proportional to the number of bits lost during computation. The reversible circuits do not lose information and can generate unique outputs from specified inputs and vice versa. It has application in diverse fields such as low power CMOS design, optical information processing, cryptography, quantum computation and nanotechnology. This paper proposes a reversible design of an 8 -bit arithmetic and logic unit and control unit for a reversible processor. The architectures of the ALU and control unit have been proposed, in which, each block is realized using reversible logic gates. The important blocks of the Arithmetic and Logical Unit are adder/subtractor, multiplier, left and right shifter and the logical operations. Each module has been coded using Verilog then simulated using Modelsim and prototyped in Xilinx-Spartan 3E. Keywords- Reversible Logic, Reversible Gate, ALU, Control Unit, Xilinx. I.

INTRODUCTION

Toffoli gate and 3*3 Peres gate are the most referred. The detailed cost of a reversible gate depends on any particular realization of quantum logic [2]. Generally, the cost is calculated as a total sum of 2*2 quantum primitives used. The cost of Toffoli gate is exactly the same as the cost of Fredkin gate and is 5. The only cheapest quantum realization of a complete (universal) 3*3 reversible gate is Peres gate and its cost is 4.

Figure 1: Feynman Gate

Figure 2: Fredkin Gate

In modern VLSI system, power dissipation is very high due to rapid switching of internal signals. Landauer showed that the circuits designed using irreversible elements dissipate heat due to the loss of information bits [1]. It is proved that the loss of every bit of information results in dissipation of KT*log2 Joule of heat energy where K is the Boltzmann constant and T is the temperature at which the operation is performed. Bennett showed that this heat dissipation due to information loss can be avoided if the circuit is designed using reversible logic gates [1]. A gate is considered to be reversible only if each and every input has a unique output assignment. Hence there is a one to one mapping between the input and output vectors. A reversible logic gate has same number of inputs and outputs. III. II.

BASIC REVERSIBLE GATES

Figure 3: Tofolli Gate

Figure 4: Peres Gate

ARITHMETIC AND LOGIC UNIT

There exist many reversible gates in the literature. Among them 2*2 Feynman gate, 3*3 Fredkin gate, 3*3

The arithmetic and logic unit has 4-bit select inputs to select one from 16 operations as shown in Table.1. Two 8-bit data are given as input to the ALU. The logical

The various sub modules included in the design are adder/subtractor. 8-bit Adder/Subtractor The reversible full adder/subractor is realized using Peres gates and Feynman gates [3]. Figure 5 : Reversible design of full adder/subtractor Figure 6 : Design of 8-bit adder/subtractor B. Figure 8 : Design of right shifter using reversible mux The Figure 9 shows 8-bit right shifter block designed using reversible 2 to 1 multiplexers. The XOR and NOT operations are realized using Feynman gate [6]. The reversible multiplexer is realized using reversible Fredkin gates. OR. right shifter and a logical unit. Logical Unit The logical operations included in this unit are basic logic gates AND. Each partial product is obtained by addition using reversible half-adder and fulladder gates. XOR and XNOR. The Peres gate is used as the half-adder. Shifter The left and right shifter blocks are designed using reversible multiplexers. NOR. NAND. NOT. For Ctrl value zero the circuit performs addition and Subtraction for Ctrl value one. The AND gate is realized using the Fredkin gate [6]. The Figure 8 shows 8-bit right shifter block designed using reversible 2 to 1 multiplexers. . A.operations include all basic logic gates. left shifter. the 8-bit reversible ripple carry adder/subractor is designed by propagating the carry as shown in Figure 6. Figure 9 : Design of left shifter using reversible mux D. multiplier. The HNG gate is used as the full-adder. Table 1 : Operations in the ALU I3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 I2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 I1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 I0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operation Clear A+B A-B A*B A++ A-Left Shift Right Shift Or And Not Xor Nor Nand Xnor Preset Figure 7 : 8-bit Multiplication Partial Products C. The NAND and NOR gates are realized using the New gate [6]. 8-bit Multiplier HNG gates and Peres gates are used in the design of the 8bit reversible multiplier [6]. using which.

If the ENABLE is 1. The lower 4-bits of the instruction carry useful information for both ALU and 16-bit Register File. Figure 10 : Instruction Format SIMULATION RESULTS The important block of the control unit is the instruction decoder. The DEVICE ID assigned to each memory component is shown in Table. 11 show the simulation results of 8-bit adder/subtractor. Table 2 : Device IDs of Memory Components Device Id 000 001 010 011 100 101 110 111 Device Name Accumulator Register ALU Result Registers Data Bus Buffer Register Program Counter Instruction Register Status Register Register File Temporary Register All the blocks are modelled using VERILOG. respectively. 12 respectively. The functional verification of the codes is analysed using ModelSim-Altera 6. If the LOAD is 1. Two select signals ‘load’ and ‘enable’ are used for the decoders. CONTROL UNIT ARCHITECTURE The Figure 7 shows the 10-bit instruction used in this design.9. The first two bits correspond to LOAD and ENABLE. which controls the eight memory components of the processor.0) Starter Edition and synthesised using Xilinx ISE Design Suite 13. The simulation results of the ALU.4a (Quartus II 9. Register File and Memory Components are shown in Figure. right shifter and left shifter blocks of the Arithmetic and Logic Unit. 11. Instruction decoder consists of two 3 to 8 decoders as shown in Figure. 9. the device specified by the DEVICE ID will output its content to the data bus.8. 8-bit multiplier. Figure 12: Reversible 3 to 8 decoder V. Instruction Decoder. Arithmetic And Logical Unit: Figure 8. Figure 13 : Simulation result of 8-bit reversible adder/subtractor Figure 14 : Simulation result of reversible 8-bit multiplier Figure 15 : Simulation result of right shifter Figure 11 : Instruction Decoder Figure 16 : Simulation result of left shifter . 10.IV. The next 3-bits correspond to DEVICE ID of the memory component.2. then the device specified by the DEVICE ID will take the input from the data bus.4. 10. A. The Figure 7 shows the reversible 3 to 8 decoder designed using reversible Fredkin gates [4].

The Instruction Decoder of the Control Unit has been implemented in Xilinx Spartan 3E kit and the synthesis report is obtained as shown in Table 4. The Figure 17 shows the simulation result of Instruction Decoder. REFERENCES 2% [1] [2] [3] B. Majid Haghparast. Depending on this value the required output results are obtained and stored in ‘x’ and ‘y’. 17:pp. One for controlling the LOAD input ‘l’ of each of the 8 memory components and other to control the ENABLE input ‘e’ of each of the components.312 190 Utilization 1% 1% 100% 0% 1% 11% Figure 17: Simulation result of ALU Average Fanout of Non-Clock Nets The ALU design has been implemented in Xilinx Spartan 3E kit and the synthesis report is obtained as shown in Table 3. Further this design may be extended to transistor implementation which would help in easier analysis of power. Shahid Beheshti University. (Sept 2010) Design. . Mr. Table 3: Synthesis report of ALU Device Utilization Summary Logic Utilization Number of Slice Latches Number of 4 input LUTs Number of occupied Slices Number of Slices containing only related logic Number of Slices containing unrelated logic Total Number of 4 input LUTs Number used as logic Number used as a route-thru Number of bonded IOBs Average Fanout of Non-Clock Nets Used 20 252 142 142 0 253 252 1 23 3.81 Available 9. Instruction decoder In the Instruction Decoder. Himanshu Thapliyal.656 8 8 9.312 4. Praveen Kumar B V. This paper provides the circuit level implementation of the reversible processor. Muralidhara K N. (May 2012) A Beginning in the Reversible Logic Synthesis of Sequential Circuits. Ravish Aradhya H V. Islamic Azad University. Muralidhara K N. Bennett. Somayyeh Jafarali Jassbi. Devendra Goyal. RTU. Venugopal U.312 Utilization 1% 2% 3% 100% 0% VI.bit input data that acts as the control signal.India (May 2012) VHDL Implementation of Reversible Logic Gates. RTU. this design can be extended to any number of bits. Department of Electronics and Communication Engineering. RVCE Bangalore. In future. (September 2011) Low Power Reversible Parallel Binary Adder/Subtractor. Here k is the 3-bit selection input to address each memory component. Tehran. Vidhi Sharma.312 9. Ms.(2008) . Raja K B. two 3 to 8 reversible decoders are used. Mark Zwolinski (2005) Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology. Research and Development.B Srinivas. Tehran. Rangaraju H G. IranKeivan Navi and Omid Hashemipour. Optimization and Synthesis of Efficient Reversible Logic Binary Decoder. H.84 190 12% Available 9.The Figure 17 shows the simulation result of ALU. 525-532 (November 1973) Design of Control unit for Low Power ALU Using Reversible Logic. Chinmaye R. CONCLUSION AND FUTURE WORK Reversible circuits are an emerging technology with promising applications because of the low power dissipation. IBM J. Each block of the processor was designed using the basic reversible gates.KOTA. Here ‘a’ and ‘b’ indicates the 8-bit data and ‘i’ is a 4. Table 4: Synthesis report of Instruction Decoder Device Utilization Summary Logic Utilization Number of 4 input LUTs Number of occupied Slices Number of Slices containing only related logic Number of Slices containing unrelated logic Total Number of 4 input LUTs Number of bonded IOBs Used 16 8 8 0 16 21 3. RCEW Jaipur. Iran.312 4. C. [4] [5] [6] [7] Figure 18: Simulation result of Instruction Decoder Logical reversibility of computation. Ravish Aradhya HV. In this paper a novel architecture of a reversible 8-bit processor has been proposed. KOTA. Muralidhara KN.656 142 142 9. M.

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