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Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011

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Analysis of PCFICH Channel Architecture for LTE using Unfolding Technique
S.Syed Ameer Abbas
Assistant Professor, Department of ECE Mepco Schlenk Engineering College Sivakasi, India abbas_mepco@yahoo.com

R.Lakshumi Praba
PG Student, Department of ECE Mepco Schlenk Engineering College Sivakasi, India lakshumipraba@gmail.com

S.J.Thiruvengadam
Professor, Department of ECE Thiagarajar College of Engineering Madurai, India sjtece@tce.edu
Abstract— Realization of transmitter and Receiver architecture for LTE is the major research work being carried out by implementation experts. There are four Control channels available in LTE for both uplink and downlink. The uplink control channel is PUCCH. The downlink control channels are PDCCH,PCFICH and PHICH. The Physical Control Format Indicator Channel(PCFICH) is one among the downlink physical control channel and it carries the number of OFDM symbols used by the PDCCH channel, denoted as Control Format Indicator(CFI).These control channels play a key role in the correct decoding of the payload information. The CFI is the first information received by the User and so is important for the system performance. In this paper, the realization of architecture for the PCFICH are done using FPGA, and the VLSI DSP technique called unfolding is applied for optimization. The simulations are done using Modelsim and are implemented in Xilinx Spartan 3E kit. Keywords- LTE; FPGA; CFI;Unfolding

I.

INTRODUCTION

Long Term Evolution (LTE) is a Fourth generation wireless broadband technology, which is capable of providing high peak data rates (100 Mbps downlink and 50 Mbps uplink),multi antenna support, reduced cost, wide range of bandwidth(from 1.4 MHZ upto 20 MHZ),backward compatibility with existing 2G and 3G networks, increased spectrum efficiency and peak data rates at cell edges[1-3]. All these criteria are satisfied by the efficient usage of the control channels. The LTE physical layer is a highly efficient means of conveying both data and control information between an enhanced base station(e-Node B) and mobile user equipment(UE). The LTE physical layer uses OFDM as the access technology, QAM as the modulation scheme and MIMO concepts. LTE differs from its predecessors by using OFDM along with MIMO antennas. OFDM is selected ,owing to its suitability for MIMO transmission and reception, resistance of its symbol structure to multi path delay spread, no need of equalization etc[4].

The downlink physical channels correspond to a set of resource elements carrying information originating from the higher layers. There are six physical downlink channels available namely, Physical Downlink Shared Channel (PDSCH), Physical Broadcast Channel(PBCH), Physical Multicast Channel (PMCH), Physical Control Format Indicator Channel (PCFICH), Physical Downlink Control Channel (PDCCH), Physical Hybrid ARQ Indicator Channel(PHICH)[1].The first three channels are the data channels. The PDSCH carries the payload and PBCH broadcast the cell specific information. The PMCH is used for broadcasting and multicasting information from multiple cells. The latter three channels are the control channels, where PDCCH is the main control channel carrying the downlink scheduling assignments and the uplink scheduling grants. The PCFICH carries the control Format Indicator(CFI), which provides the number of OFDM symbols used by the PDCCH channel. The PHICH carries the hybrid –ARQ ACK/NACK Indicator(HI). The downlink physical signals are Reference signal and the Synchronization signal. The reference signals are of three types namely Cell Specific reference signals, MBSFN reference signals, UE-specific reference signals. The synchronization signals are primary synchronization signal and secondary synchronization signal and they provide the
One radio frame T f=10ms One slot Tslot=0.5ms 0 1 2 3 .................................... 18 19

One sub frame
Figure 1. Type I (FDD) frame structure.

978-1-61284-653-8/11/$26.00 ©2011 IEEE

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0.0. as shown in TABLE I.1. The exact position of CFI in the resource grid is based on the bandwidth and physical layer cell identity. LTE specification provides capacity enhancing features such as link adaptation.0.1. Section VI.0.1. The gold sequence is generated using the formula x1( n + 31) = ( x1( n + 3) + x1( n)) mod 2 (2) x 2(n + 31) = ( x 2( n + 3) + x 2( n + 2) + x 2( n + 1) + x 2(n)) mod 2 (3) Transmitter Scrambling QPSK Modulation Layer Mapping Block Coding Mapping to RE Pre coding (4) 3) Modulation: The scrambled sequence is then QPSK modulated to create a block of modulated symbols.1.0.0.1.1. assumptions are provided and the architectures for the PCFICH transmitter and receiver are proposed.0. The rest of the paper is organized as follows. a brief discussion of PCFICH channel is done.0. b1.1.1> <1.0.1. symbols used to contain the downlink control information is the same as the actual CFI value.0.0.1.0.1.0.1. c is the gold sequence used. stored in RAM table appear as output.00 ©2011 IEEE 538 .1.2. followed by block diagram and modelling of the transmitter and receiver architecture is done.0.1. Each sub frame consists of 2 slots.0.1. The proposed architectures is optimized using VLSI DSP techniques of folding to increase the speed and to decrease the power consumption. In Section II.1. 978-1-61284-653-8/11/$26.0.0. 2) Scrambling: The 32 bit code words are bit wise XOR ed with a cell specific scrambling sequence.1.1.1.1.1.1.0.0. Each slot consists of seven OFDM symbols [1].0.1. Otherwise span of the downlink control information is CFI+1 symbols. The scrambled bits are stored in a shift register and first two bits are given as control lines for the multiplexer.0.0.0.0. LTE supports both Time Division (TDD) and Frequency Division Duplexing (FDD).0.0> CFI ML Detection Delayer mapping 2 3 4 (Reserved) Receiver Figure 2.1.0.0.1.2) Block Code c ( n ) = ( x1( n) + x 2( n )) mod 2 Channel Demapping from RE Decoding CFI 1 CFI codeword < b0.0.0.0.1. ….1.0.1.1.0. PCFICH Transmitter 1) Block Coding: The original CFI value to be transmitted is first represented in two bit format R1. The cell specific sequence is used for the purpose of inter-cell interference rejection. The scrambling is done using b ~ (q ) (i ) = (b (q ) (i ) + c (q ) (i ))mod 2 (1) II.Proceedings of 2011 International Conference on Signal Processing.3 and 4(Reserved) and are represented using two bits.0> <1.0.0. Each downlink frame lasts for 10 ms and consists of 10 sub frames.0.0. b is the encoded sequence.0. So.0.1. The CFI is the first information received by the User equipment and so the overall performance depends on the correctness of CFI detection.The CFI is first encoded using a (32.1. The CFI can take the values of 1.1. number of OFDM CFI Where q represents the codeword.0.0.1. PHYSICAL CONTROL FORMAT INDICATOR CHANNEL The PCFICH carries the information of number of OFDM symbols used by the PDCCH to carry the scheduling assignments and other control information.1.1. Hybrid Automatic Repeat Request(H.11->3). In order to ensure high robustness. Block Diagram.10-->2.1.0.1. provides the results and discussion.1. Communication.1.0. The information carried by the PCFICH is called as Control Format Indicator (CFI) and is located in the first OFDM symbol of each subframe.0.0. which is a pseudo random sequence generated using a length 31 gold sequence generator. which ranges from 0 to 503[1]. Computing and Networking Technologies (ICSCCN 2011) information of physical layer cell identity.In QPSK modulation pairs of bits are mapped to complex valued modulaed symbols I+jQ and hence TABLE I CFI (32.0.0.0.ARQ) etc.0.1. Section III deals with the unfolding technique.0. Based upon the control.1.1.1. The dmin between the code words is 21.1.0. Section V.1. A.1.1.1.1. When a UE descrambles a received bit stream with a known cell specific scrambling sequence.1> <0. interference from other cells will be descrambled incorrectly and will only appear as uncorrelated noise.0.R0 (01-->1.0.0.0.1.0. contains some concluding remarks.2) block code.1. b31 > <0. The objective of this paper is to propose transmitter and receiver architecture for PCFICH channel and to implement the architectures using FPGA.1. In Section IV. For bandwidths greater than ten resource blocks.1.0.1.1.1.0.0. control channel design and structure plays a lead role in the correct detection and interpretation of the payload information[4]. PCFICH use this type of encoding.1.0. In this paper FDD is adopted.1.1.0.1. the corresponding modulated symbols. The frame structure for FDD used in this realization is shown in Fig.1.1.

short term fading and uncorrelated scrambling sequences. PCFICH Receiver 1) Received Signal: In the receiver side.3 (7) Where the soft outputs are given by Figure 3. hk is 16x1 complex channel frequency response and u k represents the contribution of thermal noise and interference. Computing and Networking Technologies (ICSCCN 2011) t i m Frequency Æ CFI = arg max z (m ) m =1..3 ∑ k =1 K y k − hk °d (m ) ( ) 2 (6) which simplifies to 978-1-61284-653-8/11/$26. The complex valued output at the k -th receive antenna is modelled in eqn.Then this term and three possible values of d (m ) undergoes inner product. d ( ) } K k * k m (9) The received signal y k is element by element multiplied with the conjugate of the complex channel frequency response * vector hk . 4) Mapping To Resource Elements: The control channels’ modulated symbols are mapped to the resource element groups(REG). draw the J edges Ui-->V(i+w)%J with i=0. it is 11. evenly distributed in six resource blocks (LTE minimum bandwidth 1. 2) CFI Estimation: The ML decision rule. Then argument max among the three values is selected as the CFI value. (8) the 32 bits are converted to 16 complex modulated symbols. U1.for single antenna case. which is represented as a 16 bit 16X1 vector. draw the J nodes U0. K y k = hk °d (n ) + u k . and each of these gcd(w1.3 k =1 ∑ Re{ y °h .J)loops in the unfolded DFG .J-1. The inner product is given by x. The outputs are represented by 16 bit numbers. The resultant is a 32 bit 16X1 vector.J) loops contains w1/gcd(w1. which also denotes the received subcarrier vector at the antennas in the receiver side. UJ-1. y = ∑x y i =1 N * i i . Unfolding by the factor J creates a new program that describes J consecutive iterations of the original program. z (m ) = ∑ z( k =1 K m) k for m=1. since the interferers are uncorrelated due to independent large scale propagation.1.(5) k = 1.J) delays and J/gcd(w1. UNFOLDING Unfolding is a VLSI DSP technique that can be applied to a DSP program to create a new program describing more than one iteration of the original program. The hidden concurrencies in the processing can be unraveled by using Unfolding. The noise term u k is modelled as zero mean circularly symmetric complex Gaussian with covariance H 2 E uk uk = σu I . (5) y is 16x1 received subcarrier vector.J) copies of each node that appears in l.as shown in Fig. It has applications in designing high speed and low power VLSI architectures. III.00 ©2011 IEEE 539 . 5) Channel Estimation and Noise addition: To model the channel. Then the noise. 3.. The received signal y k is represented in the figure 2.3.The resultant is a 32 bit 16X1 vector.For each edge U-->V with w delays in the original DFG. by maximizing the log-likelihood function of y k given hk is given in eqn(6) delays for [ ] CFI = min m =1.. which is represented as a 16 bit 16X1 noise vector is added .. after removal of cyclic prefix from the received signal.. the modulated output is element by element multiplied with the channel estimation vector. B. This is done for number of times as the number of antennas used to receive.2.For each node U in the original Data Flow Graph(DFG). 2. Property 2: Unfolding a loop l with w1 delays in the original DFG leads to gcd(w1.bit CFI code words. 3. then FFT is performed and then resource element de mapping is done. ⎢i + w ⎥ ⎢ ⎥ ⎣ j ⎦ complex QPSK symbol vector corresponding to the 32..2. The transmitter architecture is presented in Fig. Property 3: Unfolding of a DFG with iteration bound T ∞ results in a J-unfolded DFG with iteration bound JT ∞ . d (n ) is the 16x1 k Which is simplified as CFI = arg max m =1. Communication. Unfolding Algorithm 1. and PCFICH is mapped only in the first OFDM symbol of each subframe and are transmitted through the channel. then the codeword detected is 01. Properties of Unfolding Property 1: Unfolding preserves the number of delays in a DFG.. where n varies from 1 to 3. 2. the 16 symbols are distributed in four REGs. Mapping to Resource Elements. In order to obtain the largest possible frequency diversity gain.4 MHz support 6 resource blocks).Proceedings of 2011 International Conference on Signal Processing. 2. This is also known as Loop Unrolling and has been used in compiler theory. If CFI is maximum value when m=1.The real part of the resultant value is taken. A. 2. when m=2. …. B. it is 10 and when m=3.

1 0 Layer mapping Z1 Z2. which also maintains the number of delay elements.(eg:1<2 implies 1 edge with 0D and 1 edge with 1D). So.Z3 Z4. 29 30 31 31 31 Channel estimation hk 31 30 ………. R1 R0 Property 4: Unfolding preserves the precedence constraints of a DSP program.Z7 00-1ant 01-2ant 10-4ant M U X Figure 6. 14 15 .. at 5 unit time we are getting all the outputs. The 16D branch is converted into 4 branches each with 4D and so we get 2 outputs at 4 time units and the other 2 outputs are produced at 5 unit time.4 6 1. the real part is extracted and argument maximum is taken among the three outputs.5. The data flow graph for CFI estimation is shown partially in Figure....4 are converted to 6 nodes in Figure. Thus we get output with 9 unit delay by applying J=2 unfolding. 2 .. 2 14 15 −1 2 − j1 2 15 14 ……. Communication. 1 0 0 1 1 1 −1 2 + j1 2 − j1 2 + j1 2 0 1 . The unfolding by a factor of J=2 is applied for Figure.3.Proceedings of 2011 International Conference on Signal Processing. .The transmitter architecture consists of Block Coding.By using unfolding algorithm.. The first two bits are same as the original bits and the third bit is the XOR value of the first two bits. 3 nodes in Figure. These 32 bits form the CFI codeword. 1 0 + 31 30 …….CFI Estimation . CFI Estimation using unfolding J=2 . A.. For scrambling process. The input is the 2 bit CFI value R1. 1 0 16 QPSK sym. the branch with 16 delays is converted into two branches with 8 delays each in Figure.The 2 bit value is converted to 32 bit value by block coding. Thus we get output with 9 unit delay by applying J=2 unfolding. R0.00 ©2011 IEEE 540 . IV. unfolding by a factor of 4 (J=4) is also done using 12 nodes.6. 978-1-61284-653-8/11/$26.4. Transmitter Architecture The transmitter architecture is presented in Figure. Scrambling and Modulation and layer mapping. Unfolding by higher factors increase the speed of the process.Similarly. d(m)(2k) Yk(2k) Cyclic Prefix Number of OFDM symbols per sub frame Frame Structure CFI(bits) Gold Sequence(bits) dmin between CFI code words (bits) Modulated Symbol(bits) Channel channel frequency response vector(hk) Conjugate of channel frequency response vector(hk*) Noise vector(uk) Normal 14 (7 in each slot) Type I(FDD) 2 32 21 16 Rayleigh fading 16 bit 16X1 vector 16 bit 16X1 vector 16 bit 16X1 vector 8D h*k(2k) 0D 1D d(m)(2k+1) Yk(2k+1) 8D h*k(2k+1) 1D 0D Figure 5.Unfolding an edge with w delays where w<J produces J-w edges with no delays and w edges with 1 delay. yk 31 30 ……. by application of unfolding algorithm (eg: U0ÆV0 with floor((0+16)/2)=8delays ).5.In Figure... ….Z5.. Computing and Networking Technologies (ICSCCN 2011) Yk(n) d(m)(n) 16D h*k(n) 1D 1D Figure 4.From the output. PROPOSED ARCHITECTURE FOR PCFICH TRANSMITTER AND RECEIVER TABLE II Assumptions Parameter Channel Bandwidth (MHz) Number of Physical Resource Blocks Sampling Frequency(Msps) Number of occupied subcarriers Assumption 1.5.PCFICH Transmitter Architecture upto Layermapping ..Z6. The 3 bit pattern is repeated until the required 32 bits are obtained. 3 and the resultant DFG is shown in Figure. Unfolding also helps in obtaining low power architectures.92 73 X1 X2 0 1 2 0 1 2 3 0 1 2 3 ….

z6.Proceedings of 2011 International Conference on Signal Processing.For all the elements the multiplication is done and the results are accumulated.11 shows the simulation result for applying J=2 unfolding and the outputs are available at 400 ps itself. The inner product is done using the formula in section II. 1 0 d 31 1 1 −1 −1 (m)* 30 2 + j1 2 − j1 2 + j1 2 − j1 2 ………. Receiver Architecture The received signal is demapped from the 16 positions of first OFDM symbol. assuming that the channel response is known are presented in this section. The 16 complex modulated symbols are then layer mapped to one. 978-1-61284-653-8/11/$26.Z2. The d(m)* is multiplied with (yko hk*) product .Z1 is the output if one antenna is selected.Z3 are outputs if 2 antennas are selected and Z4. The received signal is yk and is multiplied with the conjugate of the complex channel frequency response vector hk*. d(0). 1 0 0 1 . The modulated symbol is multiplied with the complex channel frequency response vector hk. Figure. d(2). yk hk 0 1 . namely 01.Z6. RESULTS AND DISCUSSION The simulation results and the device utilization summary. which is also represented as a 16 bit value.. one 32-bit adder. V.Table III gives the FPGA resource utilization summary for the transmitter architecture and the Table IV gives the FPGA resource utilization summary for the receiver architecture. The shifted 2 bits are given as control lines for the multiplexer. It is known that. . which on scrambling produces 32 bit output. which is a 16x16-bit multiplier.The The input to the receiver is the 16x1vector.. Re| 2 2 14 15 CFI 1 CFI 2 0 1 . Then these 2 sequences are XOR ed to get the gold sequence. Then noise which is represented using 16 bits is added.Then among the three results. Figure. The modulated symbols are represented using 16 bits.Figure. The resultant scrambled sequence is stored in a shift register. .8 provides the simulation output for transmitter.Z5. the codeword which has the maximum argument value is detected as the CFI. Communication. ….. The block coding produces 32 bit output.. 9.14 are 16X16 multipliers.z3 z1 DeLayer Mapping R1 R0 {} {} ctrl 0 1 2 0 1 2 3 0 1 2 3 0 1 ….z7 z2. Computing and Networking Technologies (ICSCCN 2011) gold sequence generation is needed. there are only three possibilities of signal transmitted.The X1 sequence is a predefined sequence. The real part of the accumulated value alone is taken. which is represented as 16 bit value. The adders used are one 16-bit carry out adder and z4.of error bits and find minimum error output o/p 1 o/p 2 o/p 3 31 Figure 7. Thus the resultant signal yk is a 32 bit value. Of them.So.. The gold sequence is produced by using the 2 sequences X1 and X2.d(1).PCFICH Receiver Architecture . Based on the control.00 ©2011 IEEE 541 . the demodulated signal will be one among the three. The receiver architecture is presented in Figure. CFI 3 30 01 CFI 10 11 Count no. The resultant is a 32 bit value. where CFI value is available. B.. which is also a 32 bit value.20 adder/subtractors are used.7. It takes three clock pulses to get the output From the synthesis report. the output appears.2 or 3). The shift register is set to shift 2 bits per clock cycle for QPSK modulation.element by element. which is “1000000000000000000000000000000”.. the number of multipliers used is one. The simulation results for the unfolding by factor of J=2 and J=4 are presented here. Then scrambling is done by XOR of the block coded sequence and the gold sequence.7. This process is done for the three values viz. 14 15 * . 16 symb. . which is a 32 bit value. 2 MAC . The 32nd bit of both the sequences are calculated using the formula in section II.Z7 if 4 antennas are selected. The 4 possible complex modulated QPSK symbols are shown in figure. From the synthesis report. The simulation for the CFI estimation is shown in the Figure.two bit CFI input is given. In fig. 18 multipliers are used. and the result is a 64 bit value. two or four layers based on the information from higher layer..z5. The inputs to the multiplexer are stored in RAM table.. since it varies according to the applications...10 or 11(CFI-1.10 shows the simulation result for applying J=2 unfolding and the outputs are available at 800 ps compared to the 1600 ps for the original PCFICH receiver output. The 31 bits of X2 sequence is assumed. 30 31 31 31 29 30 31 47 46 ……. Then this resultant term undergoes inner product with the three possible values of d(m).1is 32X16 and 3 are 48X16 multipliers.

260ns 168372 kilobytes VI.User Equipment radio access capabilities (Release 8)”.Physical Channels and Modlation(Release 8)”. Simulation for PCFICH receiver The transmitter and receiver architectures for the PCFICH channel are proposed in this paper. A. Thiruvengadam. the CFI is estimated by maximum likelihood method.Proceedings of 2011 International Conference on Signal Processing. The architectures can be further enhanced by using unfolding to reduce power consumption and retiming to reduce number of registers. Computing and Networking Technologies (ICSCCN 2011) TABLE III FPGA RESOURCE UTILIZATION SUMMARY FOR PCFICH TRANSMITTER FOR THE XILINX SPARTAN 3E . The simulations are done and the device utilization are studied.Parhi “VLSI Digital Signal Processing Systems-Design and Implementation”.212. Communication. Louay M.Kuchibhotla.April 2008. 3GPP TS36.00 ©2011 IEEE 542 . Nev.”Evolved Universal Terrestrial Radio Access(EUTRA).” in proceedings of IEEE wireless communication and Networking Conference(WCNC’08).211. R.2010. 10 pages. R. The synthesis are done using Xilinx 8. REFERENCES [1] [2] 3GPP TS36. Simulation for unfolding J=2 [3] [4] [5] [6] Figure 11.Frequency Delay(Min..2010. The simulations are done using Modelsim.3S500EFT256-4 DEVICE Number of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of MULT18X18SIOs Max.Love. Keshab K. and the speed is improved.Las Vegas. A.period) Total memory usage 494 /4656 (10% ) 322 / 9312 ( 3%) 883 / 9312 (9% ) 11 / 20 ( 55% ) 33. S.” EURASIP Journal onWireless Communications and Networking. In the receiver side. Simulation for PCFICH transmitter 582 / 4656 (12%) 616 /9312 ( 6% ) 714 / 9312 (7% ) 59.830MHz 16. The signal to be transmitted is produced.Multiplexing and Channel Coding(Release 8)”. The proposed architecture was optimized using Unfolding technique. Simulation for unfolding J=4 978-1-61284-653-8/11/$26. J. Figure 10. CONCLUSION Figure 9.Article ID 914934.Ghosh et al.”Downlink control channel design for 3GPP LTE. 3GPP TS36. passed through channel and noise is added.047MHz 30.vol. period) Total memory usage Figure 8.714ns 143284 kilobytes TABLE IV FPGA RESOURCE UTILIZATION SUMMARY FOR PCFICH RECEIVER FOR THE XILINX SPARTAN 3E .”Evolved Universal Terrestrial Radio Access(EUTRA).”Evolved Universal Terrestrial Radio Access(EUTRA). USA .813-818.pp.Nov.1i and implementation is done in Spartan 3E kit. Jalloul.3S500EFT256-4 DEVICE Number of slices Number of Slice Flip Flops Number of 4 input LUTs Max. Performance Analyis of the 3GPP-LTE Physical Control Channels.306. Frequency Delay(min.