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1554

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 7, JULY 1998

Modeling and Simulation of Stress-Induced Leakage Current in Ultrathin SiO Films
Bruno Ricc` o, Gianfranco Gozzi, and Massimo Lanzoni
Abstract— This paper presents a new model for stress-induced leakage current (SILC) in ultrathin SiO2 films, that is able to explain and accurately represent the experimental data obtained with MOS capacitors fabricated with different technologies and oxide thickness in the 3–7 nm range. Index Terms— MOS capacitors, reliability, SILC, thin oxides, tunnel injection.

I. INTRODUCTION INCE its discovery [1], stress-induced leakage current (SILC), namely the excess low field conductivity produced by a high field stress, has become a major phenomenon of concern for the reliability of MOS SiO films with thickness approximately below 10 nm, particularly interesting for nonvolatile memories exploiting tunneling programming. At microscopic level, however, the physics of SILC is still to be fully understood, although general consensus exists about the fact that it is due to trap-assisted conduction, very likely involving tunneling. The situation is particularly interesting, because, as will be shown later, the main features of SILC (slopes of versus curves, critical voltages for slope changes, are remarkably independent of technological details (n- rather , thus clearly than p-type substrates, oxide growth and suggesting the presence of the same fundamental physical mechanisms. However, the small value of the tunneling barrier extracted from experimental data [1]–[4], that cannot be justified in the light of the present theoretical models and the recent discovery of a significant energy loss mechanism [5] are important features of the phenomenon still waiting for convincing explanations. In such a context, the present paper introduces a new model that is able to interpret the main features of lowfield conductivity of virgin as well as stressed oxides and to accurately represent experimental data obtained from devices fabricated with different technologies. II. EXPERIMENTS Accurate measurements of SILC’s have been performed using two sets of MOS capacitors both fabricated with advanced, though different technologies, provided by two companies with leading position in the field of nonvolatile memories. All
Manuscript received November 10, 1997; revised February 13, 1998. The review of this paper was arranged by Editor W. Weber. The authors are with DEIS, University of Bologna, 40136 Bologna, Italy. Publisher Item Identifier S 0018-9383(98)04500-6.

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devices feature n polysilicon gates, but those of the first set ranging (SET1) have an n-type (implanted) substrate and from 7 to 5 nm, while those of the second set (SET2) have in the range 5–3 nm. p-type substrates and In our experiments, electrons are normally injected from the n gate toward the substrate, although with the devices of SET1 reverse bias has also been used. The structures of SET2 do not allow electron injection from the substrate, however during injection from the gate both cathode and anode interfaces are accumulated, thus minimizing the biasdependent voltage drops within the semiconductor electrodes that play a non-negligible role in determining the diode characteristics. Of course, in the calculation of the effective oxide field the fixed value of the device flatband voltage 1 V for the devices of SET2) has been taken into ( account. The thickness of the oxides used in this work has been determined with the method described in [6], and the devices have A/cm been stressed forcing a constant current (other values of have also been used without substantial differences in device behavior). All SILC measurements have been made shorting the device terminals between measures. Each measurement has been repeated twice, in order to check that no transient phenomenon was occurring. Furthermore measurements in a few samples have been repeated two days after the stress, without finding any significant difference with the results of previous experiments. Fig. 1 shows typical results obtained with devices of SET2 and nm, as well as of SET1 featuring nm. As an example of different type of with representation, Fig. 2 shows the data relative to the 5.0-nm versus (where denotes oxides in the form the oxide field), normally used for Fowler–Nordheim (FN) plots. In these measurements, currents are limited toward the lower values by noise and setup detection capabilities, and toward the higher ones by the need not to break the device. Therefore, as schematically shown in Fig. 3, currents are observed only within a window with respect to which the experimental decreases and increases, curves move up and down as respectively. Fig. 3 also illustrates that the (apparent) differences in oxide (shown in the characteristics found for different values of insets on the right side of the figure), in reality come from different regions of the same general curves shown in solid lines. In Fig. 3, regions B, C, and D indicate SILC; region

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. At this regard. [5]. In agreement with [4]. C. while the thicker one is from SET1 and has an n-type substrate. 3. 0 Fig.. they can play a dominant role. Fig. 4 shows the currents measured nm) biased in the same stressed devices (featuring in reverse. An important result of our experiments is that the slopes of versus curves are essentially the same for the SILC fabricated with different technolodevices with the same gies. fundamental microscopic mechanisms. a voltage drops present within the substrate. Consequently. then consider the relative importance of different current contributions... indicate conventional FN and direct tunneling. with cathode and anode reversed with respect to those used to stress the device. VG > 0). THE MODEL In this work the low field conductivity of (stressed as well as virgin) thin oxides is attributed to trap-assisted tunneling (TAT).` et al. with positive gate bias. VG < 0) and from the substrate in those of SET1 (i. The three thinner oxides shown here belong to devices of SET2 featuring a p-type substrate. [7]. electron were injected from the gate in the devices of SET2 (i.e.8 eV for the Si–SiO2 barrier height. while at lower ones this is not the case because the series voltage drop becomes smaller and significantly bias dependent. Fig. while under negative bias the polysilicon gate is not so because it is very heavily doped. that are the main subject of this paper. and this also holds for a number of cases presented in the literature [2]. while the voltage drop in series with the capacitors is practically negligible under negative gate bias.: MODELING AND SIMULATION OF STRESS-INDUCED LEAKAGE CURRENT RICCO 1555 Fig. The currents due to this phenomenon coexist with the classical (i. thus current is substantially independent of the sign of indicating also that the stress-induced damage is essentially uniform throughout the oxide (or at least symmetric with respect to the silicon electrodes). In this section. Trap-Assisted Tunneling and Let us consider tunneling electrons at an energy assume that a population of traps is present throughout the .e. V is at high applied field. A denotes the low-field current of virgin devices (as shown not coincident with the extrapolation of the tunneling regime found at higher fields. A. Typical experimental I V curves of virgin and stressed thin oxides. we will first present the model for TAT currents. The MOS devices used in this work have been fabricated with different technologies. that is assumed to be whole oxide with a concentration . unassisted) tunneling in the well know FN and Direct regime (namely in cases where the tunneling barrier has a triangular or a trapezoidal shape). these curves can be explored only within a window limited by noise toward the lower currents and by oxide breakdown toward the higher values. the n-type substrate is inverted. FN and DIR. producing the typical experimental results shown in the insets. If interpreted by means of the classical FN model.e. respectively.. Simulation results giving an overview of low field I –V curves of thin oxides showing different characteristics regions. Typical example of SILC data in the conventional form used for FN plots. 4 clearly shows that. the reverse characteristic is essentially coincident with that in forward mode at high fields.e. and D denote SILC regions of the curves. while FN and DIR denote the classical (i. here represented with dotted line). the curve regions for VOX 3:12 eV lead to the extraction of a value 0.e. i. this result demonstrates that the SILC . strongly suggests that SILC is due to the same. different regions fall within such a window. unassisted) tunneling currents and. III. In the experiments. 2. namely a microscopic phenomenon where electrons tunnel into and successively out from traps located within the tunneling distance from the injecting interface. respectively. For different values of oxide thickness. With regard to the voltage drops within the semiconductor electrodes. The substantial agreement between experiments performed on different oxides (particularly when the voltage drop within the semiconductor electrodes of the MOS diodes is taken into account). Fig. When the gate voltage is positive. depending on stress and bias conditions. In these experiments. and forward mode. 1. when this effect is accounted for. [3]. j j  A is the low-field conductivity of virgin devices. The letters B.

. If oxide conduction is due to tunneling. is the concentration of trapped electrons (i. Considering only such traps. (tunneling-) baricentric traps. since to different slopes of the (4) and (5) In these equations the factor 2 at the exponent’s denominator discussed with regard to comes from the square root of [m/(V eV (when (3). (4) and (5) establish curves a direct link between the slopes of the and the barrier height of the dominant tunneling mechanism. i. is the transmission coefficient of the barrier controlling unassisted electron injection. as well as with the consideration made at the end of Section II). however. 4. the TAT current is given by (3) . thus the . The dots represent baricentric traps belonging to a population assumed to be uniformly distributed in space and with energy confined in bands.. NO. The model of TAT. JULY 1998 Under static conditions. i. the trapping and detrapping process of a group of traps at the same energy and position can be expressed as [9] (1) is the supply current at the injecting interface. VOL. (b) Schematic representation of the tunneling barriers and transmission coefficients of interest for TAT. with indicating the where transmission coefficient of the whole barrier separating the cathode from the anode. (a) Schematic representation of the essential tunneling mechanisms considered in this work.e. with the same anode and cathode as in the stress configuration or with the electrodes swapped. Conversely. TCA .1556 IEEE TRANSACTIONS ON ELECTRON DEVICES. . 7. instead. is expressed in eV). tunneling barrier. (and ). of filled traps) and is their attempt-to-escape frequency. where is the trap capture section. since they lead versus characteristics. As discussed later. the voltage drop within the n-type substrate for positive gate voltages inverting the Si–SiO2 interface. for a given electron energy. represents mass for tunneling. from (1) it is (2) Consequently. 0 (a) (b) Fig.e. denotes the voltage drop across the Planck’s constant. uniform in space (in agreement with [4] and [8]. Fig. those for which play a largely dominant role. The energy of these traps is confined within bands. Equation (1) should be written for all traps along the tunneling path. Equation (5) is particularly important for the conductivity of ultrathin oxides at low-applied voltages. is independent of energy and will first be presented in general form. the slopes of the different regions of the experimental curves can be used to identify the dominating tunneling mechanism.e. TL and TR denote the tunneling coefficients of the barrier on the left and on the right of the considered trap.e.. The open squares represent the reverse characteristics shifted toward the left by 28F . respectively. 5. respectively). but it can be easily seen that the contribution given by each trap to the total current is proportional to the smaller of the two transmission coefficients. the cases of FN or As for the expression of DIR tunneling regimes must be distinguished. as schematically represented by the shaded region in Fig. respectively. I V characteristics of stressed devices with n-type substrate measured in the forward and reverse configuration (i. we will consider electrons tunneling from both bands of the cathode and assume the existence of two populations of traps at different energy. denotes the electron effective is the electron charge. and are the transmission coefficients of the barriers separating the traps from the cathode (at the left) and anode (at the right) of the tunneling diodes. 45. 5..

In all simulations we have used the same set of parameter and . at lower applied voltages. using (4) and (5). Furthermore. As can be seen in the typical SILC region (VG = 3 V) the obtained trap concentrations largely exceed the threshold voltage. hence it will be neglected hereafter. respectively). typically only one of the current components of (6) dominates the measured characteristics. uniformly distributed in space within the oxide ([4]. even in virgin devices the current due to unassisted tunneling (that can be calculated extrapolating the curve at higher fields) is much lower than those measured (Fig. 3) it is (8) Naturally. Thus. Example of trap concentrations of interest for this work. i. (3) indicates that they are essentially proportional to the concentration of available baricentric traps and. [8]. 6. in good agreement with the theoretical value of [12]. is present with a concentration devices and features a uniform distribution in energy between Fig. However. let us take as an example the nm and consider typical bias point in the SILC case . ([2]–[4]. Finally. As for velocity ( 10 cm the supply current corresponding to the cathode CB. unless time-dependent breakdown terminates the experiments. The second part. namely s ([9]). denote the TAT currents due to electrons of the cathode CB and VB. in the SILC regions [i. 3(b)–(d)]. the other. created by the high field stress. 6. independent of the high also in virgin field stress. they are bound to dominate the conductivity of stressed oxides. in all cases tunneling is of the FN or DIR type depending on whether or not the voltage drop across the tunneling barrier is larger or smaller than the barrier height. trap-assisted current play the dominant role. A representative set of results of in this sense is shown in Figs. we have arbitrarily fixed the numerical values (significant only as far as orders of magnitude are concerned) cm ([8]) and of a few parameters. RESULTS AND DISCUSSION The model presented in the previous section is able to accurately describe the experimental characteristics of virgin and stressed oxides of both types of structures and of all values considered in this work. obtaining (here is expressed in V/cm) for devices of SET1 as well as of SET2. it is (7) while for virgin devices at low field (region A of Fig.. respectively. IV. it is easy to verify that unassisted tunneling from the cathode VB is negligible and compared to its CB counterpart for all values of explored in this work.e. in the former case the measured current but not for in practice coincides with its TAT components. we have simply expressed the supply current at injecting interface corresponding to the cathode VB as A/cm . In our model. shows the (bias-dependent) with tOX concentrations of traps required for TAT currents to equal the conventional. the measured current can be expressed as (6) is the device area. = 2 and 3 eV ([11]) from the oxide conduction band. while in the latter this is not the case (in agreement with the experiments V but not at V). while the opposite holds in the unaffected region corresponding to conventional FN tunneling (VG = 6 V). where denotes the concenis the electron thermal tration of VB electrons. Depending on bias and suffered stress. thus suggesting the presence also of a stress-independent TAT mechanism. one. The second part of Fig. and and 10 cm/s. the concentration of traps obtained by fitting experimental data (consistent with the values expected in stressed devices V. as these are created by the high-field stress.` et al.5 m). In fact. Current Contributions Considering electrons tunneling from both the cathode conduction band (CB) and valence band (VB). and used conventional values for the Si–SiO barrier height (3. current components due to unassisted and TAT from both bands should be taken into account. 6 gives the threshold and to equal the trap concentrations for FN contribution. that values except for the trap concentrations . where SILC is detected at In particular. we have made the following assumptions: there are two sets of important traps. The first part of the table gives the concentration of original and stress-induced traps obtained fitting the experimental data (relative to a device of SET1 5 nm). and FN regions (corresponding to low and high values of respectively). As for TAT currents..1 eV) as well as for the electron effective mass (0. as shown in the first part of Fig. 7–11. 3). we have determined by fitting the experimental curves in the SILC-free FN region at [A/cm (relatively) high fields. [8]). unassisted components due to electrons coming from the cathode conduction band. Since.: MODELING AND SIMULATION OF STRESS-INDUCED LEAKAGE CURRENT RICCO 1557 B. is the unassisted tunneling where and component due to cathode CB electrons. To give an idea of the conditions for TAT currents to dominate unassisted components. is located at about 3 eV below the oxide conduction band ([8]) and has a concentration that increases with stress time and voltage. since the contains a suitable ratio theoretical expression of effective masses [12].e. instead. [10]) exceeds such a threshold for V. in general. Fig.

1558 IEEE TRANSACTIONS ON ELECTRON DEVICES. 9. Dots and dotted lines represent experimental data and the results of simulations. respectively (for the thicker oxides the current in the region A of the characteristics falls below the noise limit and cannot be measured). NO. respectively. have been obtained fitting experimental data. 7. I –V characteristics of virgin and stressed oxides of devices belonging to SET2 with tOX = 5:0 nm. JULY 1998 Fig. Dots and dotted lines represent experimental data and the results of simulations. For given stress conditions. 10. In particular. VOL. the maximum value NMAX increases with stress time. Fig. 3). Fig. As expected. . 7. 12. respectively. 12. and 10 cm for while . I –V characteristics of virgin and stressed oxides of devices belonging to SET2 with tOX = 4:1 nm. I –V characteristics of virgin and stressed oxides of devices belonging to SET1 with tOX = 5:7 nm. is found to increase with stress time and voltage. respectively. 11. has been determined fitting the SILC characteristics. I -V characteristics of virgin and stressed oxides of devices belonging 3:2 nm. 2 10 . I –V characteristics of virgin and stressed oxides of devices belonging to SET1 with tOX = 6:8 nm. respectively. Dots and dotted lines represent experimental data and the results of simulations. 8. Dots and dotted lines represent experimental data and the results of simulations. has been extracted fitting the low field characwhile teristics of virgin samples (region A in Fig. = Fig. 45. turn out to be 10 . and nm. with the assumption of the (same) trap distribution of Fig. Energy distribution of stress-induced traps used in our model. respectively. Fig. Dots and dotted lines represent experimental to SET2 with tOX data and the results of simulations. Fig.

in no way the regions B. 2) the number of traps as different giving rise to TAT from the VB changes with regions of the distribution of Fig.` et al. the low-field conductivity of the thinner oxides (for instance the of this work) is dominated by TAT through case intrinsic traps: thus. 7. since the excess current exhibits the same slope as in the virgin samples. curves are simply if the slopes of the experimental interpreted by means of the conventional FN tunneling model. but also above flatband condition. and D of the experimental characteristics can be attributed to tunneling of electrons belonging to the cathode CB. the concentration of stress-induced traps increases and TAT of VB electrons becomes progressively stronger. as indirectly demonstrated by the decrease of the voltage needed to sustain a constant stress current. The resulting voltage-dependent concentrations of such traps is illustrated in Fig. believe that such an experiment is not really conclusive since electrons possibly tunneling from the substrate VB can be replaced by others coming from their same VB (with a corresponding increase in as assumed in [5]. the marked increase of conexceeds the flatband voltage can ductivity found when . On the basis of the obtained results. as already mentioned. but also by CB electrons recombining with a Shockley–Read–Hall (SRH) mechanism (enhanced by the large number of midgap states present at the Si–SiO interface of stressed devices). while the trap concentration. the implicit dependence on in (5) explains the shift of the char(through acteristics within the measurements window represented in Fig. Thus. 12. We. 3 can be univocally attributed to different types of conduction mechanisms. Fig. are due to traps from the leading edge. In this regard. 3. however. C. In virgin devices. [10]. When the oxides are stressed. using (4) and (5). respectively. in agreement with [3] and [8]. [3]) and enhanced SRH recombination is likely to play a dominant role in experiments such as that in [5]. 2) the role of traps is neglected. 13. since in the case of the oxides of Fig. however. the model of this work uses only usual and 4. 13 are brought in baricentric position.: MODELING AND SIMULATION OF STRESS-INDUCED LEAKAGE CURRENT RICCO 1559 Fig. and D of the experimental curves are produced by the same fundamental tunneling mechanism. in this way the experimental data of Fig. while the low-field region A is due to TAT of CB electrons involving the stress-independent.e. respectively).. obtained integrating the distribution of Fig. 13 for a typical case. hence the reason why SILC cannot be (easily) seen in (relatively) thick oxides. is consistent with the result of [2]–[4]. instead. The substantial immunity of ultrathin oxides regarding SILC is in agreement with the suggestion of [2] of a minimum stress voltage ( 4. while. through (3).2 eV for electrons tunneling from values (i. As for barrier heights. Because of the the increase of with decreasing . respectively. In particular. it is very high. The possibility of significant tunneling injection from the cathode valence band has been ruled out in [5]. cannot be attributed to tunneling assisted by stress-induced traps. unphysically small values of this parameter are calculated.7 V) required for the creation of stressinduced traps. flat part and trailing edge of the distribution of Fig. [8]. until eventually it dominates the low field oxide conductivity. 2 provide a barrier height of 0. is due to a combination of errors. As for the thinner oxides. with a corresponding increase in source/drain currents. Concentration of baricentric traps found after a given stress at energy corresponding to the cathode conduction and valence band as a function of the gate voltage used in SILC measurements. in substantial agreement with [7]. it establishes a linear relationship between SILC and trap concentration. with electrons tunneling from the MOSFET inversion layer toward the gate. and 3) the (non negligible) voltage drops within the silicon electrodes are not properly taken into account. This result. C. because no significant SILC-induced increase has been detected in an experiment in substrate current performed with n-channel transistor structures. but virtually immune from SILC. thus explaining how the different slopes of the SILC regions B. it is worth stressing that. The typical SILC regions B. contained Furthermore.8 eV (in substantial agreement with [1]–[3]). More precisely. In our opinion. the main features of the curves of Fig. however. the model of this work provides an explanation for the energy loss found to occur with SILC ([5]). mid-gap states can be in the order of the recombination time can be extremely low ( s. the small effect of stress is essentially due to the build-up of positive charge within the oxide. in particular. The bias-dependence of trap concentration is due to the edges of the distribution of Fig. C. but no Since in stressed MOS devices the density of effect on cm ([3]). This effect. a slight effect of stress can be detected particularly below. the CB and VB. 7 a V is enough to sustain the stress current voltage A/cm Finally with regard to Fig. 12. Furthermore. original traps. the regions FN and DIR correspond to unassisted tunneling of CB electrons in the FN and DIR regime. namely: 1) the tunneling regime is assumed to be FN. this Figure illustrates that the number of baricentric traps in front of the CB and VB injecting energies changes with the applied voltage so that 1) tunneling from the VB starts dominating the overall conductivity because of the drop in the number of traps able to assist TAT from the CB (at 2 V in the considered case). even when it is DIR. As an example. and D. 12. 7 shows that they are largely unaffected by SILC.

40. Olivo. K. In particular. Moazzami and C. [5] S. Italy. Maes. Degraeve. Bruno Ricc` o was born in Parma. and A. Zambuto. he has been European Editor of IEEE TRANSACTIONS ON ELECTRON DEVICES. R. and digital applications of nonvolatile memories. Phys. p. in 1995.e. Lett. degree in 1975 from the University of Cambridge. 103.” IEEE Trans. In 1983. hot electrons effects in MOSFET’s. in 1947.. May 1993. M. 343. 20. He is also involved in research topics concerning new techniques for IC testing. [11] K. 139. Phys. he has published more than 200 papers on the main international journals and conferences. Gianfranco Gozzi was born in Bologna. . 2259.. Van Houdt. Appl. Ricc` o et al. “High field induced degradation in ultrathin SiO2 films. showing that the device characteristics are essentially independent of technology and thickness. R. 1989. no. 1971. p.” in Proc. “Tunnel electron induced charge generation in very thin silicon oxide dielectrics. Weinberg. 1809. he became Full Professor of Applied Electronics at the University of Padova. M. vol. 1988. “Electron trapping/detrapping within thin SiO2 films in the high field tunneling regime. [10] R. 432. D.” Appl. “Stress-induced leakage current in ultrathin SiO2 films. vol. S. DeBlauwe. he has been consulting for the European Economic Community in the area of microelectronics. Sept.1560 IEEE TRANSACTIONS ON ELECTRON DEVICES. vol. Andersson.” J. although in practice different regions of the same basic curves can be explored. NO. His scientific interests concern solid state devices and integrated circuits. JULY 1998 be attributed to the larger number of recipient states becoming available within the anode when its CB drops below that of the cathode. L. nonvolatile memory cell characteristics and reliability. Takagi. latch-up in C-MOS structures. he has worked on electron transport in semiconductors. a microscopic phenomenon where electrons tunnel into and successively out from traps located within the tunneling distance from the injecting interface. Electron Devices. 323. He graduated in electrical engineering from the University of Bologna. [4] J. p. [3] J. where his research activity is focused on MOS reliability and. and MOS transistors experimental characterization. vol. Yasuda. 0 Massimo Lanzoni was born in Bologna. Ph. depending on insulator thickness and stress conditions... “Correlation of stress-induced leakage current in thin oxide with trap generation inside the oxides. 1961. no. University of Bologna. U. Farmer.as well as p-substrates). Patel and A. 1996. He received the “Laurea in Ingegneria Elettronica” degree from Bologna University in 1997. “Experimental evidence of inelastic tunneling and new I V model for stress-induced leakage current. p. design-for-testability techniques. Italy. [8] R. T. New York: McGraw-Hill. Bologna University. Ricc` o. E. and E. and O. A. N. i. 23. Wellekens. 1499. Monte Carlo device simulation.. p. physics and reliability of nonvolatile memories.” Appl.” IEEE Trans. in particular. 54. Dec. Maddux. “Soft breakdown of ultrathin gate oxide layers. and B. he has been with the Microelectronics Research Group at the Department of Electronics. 1992. “Stress-induced current in thin silicon dioxide films. REFERENCES [1] P. he became Director of the Italian Journal of Electronics (Alta Frequenza). Dumin and J.” Solid-State Electron.. 14. p. Deferm. 1994. Italy. compared to the situation below flatband when electrons must tunnel into states belonging to the semiconductor gap. IEEE IEDM. From 1988 to 1996. Scott et al. Such a model is essentially based on TAT. 986. 2666. 1983. Depas. On these subjects. Roussel. Italy. B. Olivo. and the paper has presented a new model by means of which low-field conductivity of both stressed and virgin devices can be accurately simulated using the concentration of traps as adjustable parameter. 64. TAT of electrons from the cathode conduction band is responsible for the low-field conductivity of virgin oxides. 58. In particular. 35. 43.’ IEEE Trans. in 1994. in 1971. The presented model has been shown to accurately simulate the characteristics of oxides fabricated with different technologies and featuring different structures (in particular. analog. Apr. Groeseneken. 5267. In particular. He received the “Laurea in Ingegneria Elettronica” degree from the University of Bologna in 1987. [13] M. VOL. p. on August 9. n. 35. [9] P. Electron Devices. “Oxide-thickness determination in thin-insulator MOS structures.” in Proc. while stress-induced leakage is due to tunneling of electrons from the valence band assisted by stress-induced traps. and M.” IEEE Trans. and the Ph. [6] B. This result clearly suggests that the same fundamental mechanism is responsible for the low-field conductivity of all considered oxides. 7. Ricc` o. R. he was elected President of the Group of Electronics of the Italian Association of Electrical and Electronic Engineers (AEI). July 1996. on January 30. Engstrom. Nguyen. self-checking circuits. Heyns. no. his scientific interests cover the characterization of thin dielectrics reliability.” IEEE Trans. “Properties of high-voltage stress generated traps in thin silicon oxide. 1977. 43. L.. 1988. Sept.. Sangiorgi. IEEE IEDM. Hu. vol. working on research projects in the fields of the experimental characterization and simulation of EEPROM memory cells and MOS devices and of the automatic test of VLSI devices. silicon dioxide physics. V. and design and test. Electron Devices. [7] M. p. Phys. 1133. vol. p. Electron Devices. IEEE IEDM. vol.K. “Tunneling of electrons from Si into thermally grown SiO2 . S. p. Italy. 45. “A new quantitative model to predict SILC-related disturb characteristics in flash EEPROM devices. CONCLUSIONS This paper has studied the low field conductivity of virgin as well as high-field stressed MOS capacitors featuring ultrathin oxides (with thickness down to 3 nm). he joined the Department of Electronics of the University of Bologna. tunneling in heterostructures. Nigam. [2] N. J. In the area of integrated circuits he is currently working on fault modeling and simulation. vol. 1996. 9. Semiconductors Devices. as nonvolatile memories endurance testing and CMOS IC latch-up testing.D. Haspeslagh. In 1980. June 1991. T. Since 1987. Toriumi. 11. p. vol. [12] Z. Electron Devices. on high field effects in ultrathin insulators. Toriumi. and H. p. Since 1983. 1996. He is currently working at the Microelectronics Laboratory. Lett. G. where he had been working at the Cavendish Lab. p.” in Proc.