You are on page 1of 3

Two Weeks Hands on Training on

VLSI Design & Verification

About the Training:


The training aims to cover basic to advanced concepts of VLSI Design and Verification with Verilog, System
Verilog, System C and C/C++. The training covers from digital design concepts to advanced RTL design and
verification technologies. During this course, you will gain valuable hands-on experience, which provides a
practical foundation for creating synthesizable RTL code and creating verification environment based on
System Verilog and C/C++ with proper design flow.
The focus of this training is completely based on the current market requirement in the semiconductor
industries.

Level:
Fundamental to Intermediate

Prerequisites:
Basic digital design knowledge

Skills Gained:
 Advanced Digital Design, Timing Analysis, State Machines, Memory Devices, RISC & CISC architecture
 CPLD and FPGA Architecture, ASIC Design Flow
 Basics of Synthesis, HDL for Synthesis and Advanced Synthesis Concepts
 Verilog Language for Hardware Design and Logic Synthesis, Design Flow with Verilog
 The File-IO and PLI concepts
 Functional Verification Flow & Terminologies, Verilog Testbench for Simulation
 An Introduction to System C/C/C++ based Hardware Modeling
 A mini Project for Testbench Modeling with C & Verilog
 Design & Verification Methodology with System Verilog
 Understanding the complete Project Execution Cycles

Who Should Attend?


Engineers who want to learn advanced VLSI design and verification concepts.

For more details contact:


itie Knowledge Solutions
nd th
#934, 2 Floor, 17 Main Road,
rd
Rajajinagar 3 Block
Bangalore – 560010

Phone: +91. 80. 23146816


Email: itie.vlsi@gmail.com
http://www.itie.in
Schedule Plan:

Day Topic of Discussion Self Study


Day 1 Advanced Digital Design,  Digital Electronics
Verilog Introduction with basic  Combinational & Sequential
examples, Circuits
State Machines,
Memory Devices

Day 2 RISC & CISC architecture,  Microprocessors


CPLD and FPGA architecture,  Programmable Logic devices
ASIC design flow,  Any Book on Verilog
HDL Coding Guidelines

Day 3 Basics of synthesis,  Any Book on Verilog


Timing Analysis,  Timing Analysis Fundamentals
HDL for synthesis and advanced
synthesis concepts

Day 4 Verilog for hardware design and  Any Book on Verilog


logic Synthesis,
Design Flow with Verilog,
Tasks and Functions,
Timing Controls,

Day 5 State Machine Coding,  Any Book on Verilog


The File-IO and PLI concepts,
Discussion on Coding Exercises

Day 6 Functional Verification flow  Verification Methodology


Verilog testbench for simulation  Any Book on Verilog

Day 7 System C/C/C++ based Hardware  Any Book on C/C++


Modeling  Any Book on System C

Day 8 A Mini project for Testbench  Articles A-1, A-2, A-3


modeling with C & Verilog

Day 9 A Mini project for Testbench  Verification Methodology


modeling with C & Verilog -  Any Book on Verilog
Continued

Day 10 Design & Verification methodology  Any Book on System Verilog


with System Verilog,
Basic Exercises on System Verilog,
Understanding the complete project
execution cycles