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IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 24, NO. 2, JANUARY 15, 2012

**Truly Modular Burst-Mode CDR With Instantaneous Phase Acquisition for Multiaccess Networks
**

Bhavin J. Shastri, Student Member, IEEE, and David V. Plant, Fellow, IEEE

C D R C P A

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−π/2

January 6, 2012. The authors are with the Photonic Systems Group, Department of Abstract— We demonstrate a novel 10-Gb/s burst-mode clockElectrical and Computer Engineering, and data recovery circuit (BM-CDR) for multiaccess networks. McGill University, Montreal, QC H3A 2A7, Canada (e-mail: Our design is based on a hybrid topology of a feedback CDR and a shastri@ieee.org; feed-forward clock phase aligner utilizing space-sampled − clocks.david.plant@mcgill.ca). The BM-CDR achieves a bit error rate (BER) < 10 10 while Color versions of one or more of featuring instantaneous (0-bit) phase acquisition for any phase stepthe figures in this letter are available (±2π rad) between successive bursts. We also develop a online at http://ieeexplore.ieee.org. probabilistic theoretical model for space-sampled BM-CDRs to Digital Object Identifier quantify the BER performance. The theoretical model accounts for 10.1109/LPT.2011.2173480

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φ

Alexander

x

PD

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+π/2

Fig. 1. Block diagram of BM-CDR architecture.

the phase step between consecutive packets, packet preamble length, and jitter on the sampling clock. Index Terms— Burst-mode, clock and data recovery, clock phase aligner, probabilistic theory, space sampling.

I. INTRODUCTION

S THE explosive growth in Internet traffic continues, the need for highly-specialized low-cost integrated circuits is undeniable, with clock and data recovery (CDR) being a

A

critical function in back plane routing and chip-to-chip interconnects. Furthermore, the traffic received on these multiaccess links—passive optical networks [1] and packet-switched networks [2]—is inherently bursty with asynchronous phase steps | ϕ| ≤ 2π rad, that exist between the consecutive kth and (k +1)th packets. This inevitably causes conventional CDR circuits to lose pattern synchronization leading to packet loss. Preamble bits can be inserted at the beginning of each packet to allow the CDR feedback loop enough time to settle down and thus acquire lock. However, the use of a preamble reduces the effective throughput and increases delay. Consequently, to deal with bursty data, these networks require a burst-mode CDR (BM-CDR). Different approaches have been proposed to build BM-CDRs with short phase acquisition times—the most important characteristic. The first approach, based on feedback, consists in increasing the bandwidth of a phase-locked loop (PLL)-based CDR to reduce the settling time [3]. The disadvantages include stability issues, jitter peaking, and limited jitter filtering. The second approach, based on feedforward, consists of gated oscillators [4]. Here, clock phase alignment is done by triggering the local clock on each transition of the input. Phase acquisition is rapid, but this solution

Manuscript received July 11, 2011; revised September 15, 2011; accepted October 16, 2011. Date of publication October 25, 2011; date of current version

is susceptible to pulse distortions and does not filter out input jitter. The last approach is based on time oversampling [1], [2] which requires electronics operating at twice or thrice the aggregate bit rate resulting in wasted power, in addition to the knowledge of a predefined unique delimiter (start of packet) that is exploited as a signature for phase picking. In this letter, we present a novel BM-CDR architecture based on space sam-pling with a hybrid topology of feedback and feedforward. The BM-CDR uses electronics operated at the bit rate with no a priori knowledge of the delimiter, leading to more efficient power consumption and being truly modular across application testbeds, respectively. The 10-Gb/s BMCDR achieves a bit error rate − (BER) < 10 10 with instantaneous (0-bit) phase acquisition for any phase step | ϕ| ≤ 2π rad, between consecutive bits. We also develop a probabilistic theoretical model for space-sampled BM-CDRs to quantify the BER performance while accounting for phase steps between successive

with a voltage-controlled oscillator late” detection principle. 1. −π/2 rad. to provide multiple clocks: C Ko . an Alexander PD [5] which inherently . Thereafter the CPA (feedThe BM-CDR is composed of a phase-tracking CDR and a clock forward) uti-lizes multi-phase clocks and a phase picking phase aligner (CPA). and jitter on the sampling clock. NOVEL BM-CDR ARCHITECTURE frequency of interest. with respect to C K . C K−π/2. and generates a algorithm based on an “earlysynchronized clock C K . an Alexander phase an error signal that is passed through the charge pump (CP) and detector (PD). respectively.the low-pass filter (LPF) to set the voltage required by the VCO to oscillate at the II. and C K+π/2. The φshifters utilize the clock recovered by the CDR C K . Next. 1041–1135/$26. generating shifters. preamble length. A block diagram of the proposed BM-CDR is shown in Fig. a φ-picker. and a packets. The (VCO) in a PLL (feedback). The phase and frequency of C K is CPA is comprised of phase ( φ-) compared to Din in the phase/frequency detector (PFD). with low skew and different phases: 0 rad. The CDR senses data Din.00 © 2011 IEEE D flip-flop (D-FF). and +π/2 rad.

[−π.SHASTRI AND PLANT: TRULY MODULAR BURST-MODE CDR WITH INSTANTANEOUS PHASE ACQUISITION 135 whereas clock C K+π/2 will correctly sample the data [see ϕ = 0 rad A TB −π< ϕ < 0 rad A TB 0 < ϕ < +π rad A TB Fig. 1/ 2π x exp −λ2/2 d λ is the normalized Gaussian tail probability. and a sample of the current bit at the zero crossing T. with consecutive clock C Ko edges. III. Similarly for a phase step 0 < ϕ < +π rad. sample. (b) if A = T = B (X ↑. 3(a)]. For a phase step −π phase steps | ϕ| ≤ 2π rad. When there is no phase difference between the consecutive packets. This is also true for an antiphase step ϕ = ±π rad—not shown as this is a modulo-π process. clock C K+π/2 will sample the bits on or close to the transitions of the data eye. ϕ = 0 rad. 3(b)]. Moving forward. (a) Three-point sampling scheme. can determine the location of the clock edge with respect to the data edge as follows: (a) if A = T = B (X ↓. and (d) if A = B = T (X ↑. 3(c)]. Three different phase steps are considered: (a) ϕ = 0 rad. is provided to the φpicker. will correctly sample the data bits of the phase shifted (k + 1)th packet [see Fig. l =2 ϕ Q π− ψ 2π σts [UI] ψ 1 + Q 2 η( l ) . either C K−π/2 or C K+π/2. ±2π ] . 2π. 2(c)]. that will yield an accurate D FF1 Din Q B Din k k+1 k k+1 k k+1 D FF2 Q A x CK0 t (a) Clock late (b) t Clock early (c) t CK 0 Fig. 3. C K−π/2 and C K+π/2. at multiple points in the vicinity of expected transitions [see Fig. (c) if A = T = B (X ↓. current bit B . +π ] . 4. σts = | − × − is the (rms) jitter (ψ. and Q(x ) o n t h e sampling clock in < ϕ < 0 rad. Y ↑) ⇒ C Ko lags Din—is late—when −π < ϕ < 0 rad [see Fig. there will be at least one clock. regardless of any phase step. The clock C Ko early-late information (X and Y ) together with the two multiphase clocks. the Alexander PDs probability of correctly determining an early/late clock can be written as Pr (C Ko ) = Pr ( A) × Pr ( B ) × Pr (T ) and the probabilities of √ ∞ . The foregoing concepts on the Alexander PD and φ-picker lead to the circuit topology in Fig. Depending on the phase difference between the consecutive packets. Y ↓) ⇒ no data transition is present due to consecutive identical digits (CIDs). 3. [±π. (b) and (c) Early-late waveforms. and an l -bit prea P s ϕ | | ψ . ϕ) ∈ 0. 4. (b) −π< ϕ<0 rad. and (c) 0< ϕ<+π rad. clock C K−π/2 will sample the bits on or close to the transitions. from these two possibilities for driving the DFF to sample the noisy data (retime) yielding an output Dout with less jitter. PROBABILISTIC THEORY The sampling error probability of the CDR in presence of exhibits bang-bang (binary) characteristics is used to strobe the data waveform Din. CPA phase picking algorithm. 2(a)]. Y ↑) ⇒ no decision is possible. resulting in three data samples: previous bit A. 2. 0 < ϕ < +π rad k +1 k DFF Q 3 y ϕ = 0 rad k −π < ϕ < 0 rad k D FF Q 4 T Din k 1 Alexander PD P k+1 Fig. The idea behind the phase picking algorithm is depicted with the aid of eye diagrams in Fig. either of the clocks. That is. whereas clock C K−π/ 2 will correctly sample the data [see Fig. where CDRs lock acquisition time [1]. the PD aided by these samples. Hardware implementation of Alexander PD a CK−π/2 CK+π/2 (a) (b) (c) Fig. Y ↓) ⇒ C Ko leads Din—is early—when 0 < ϕ < + π rad [see Fig. 2(b)]. X ≡ T ⊕ B and Y ≡ A ⊕ T. C K−π/2 and C K+π/ 2. The φ-picker then selects the most accurate clock C Kout.

. +π ] . can be given as: Pr ( A) = Pr ( B )× Pr ( B )= Pr ( T ) 1 − Ps | ϕ| P s 1 − Ps | ϕ| Pr(T ) 1 ( 3 ) ( 4 ) (5) ϕ | π where Ps | ϕ| = Ps | ϕ|.(HMC538LP4). RESULTS AND DISCUSSION Pr(T ) = × = 1− ϑP s − | ϕ − + P s ϕ | + π ( 6 ) The BM-CDR is built from commercially available low cost/complexity electronics rated at 13 Gb/s. B . 1. ϕ) ∈ 0.correctly sampling the points A. ±2π ] . [±π. and T .5. [−π. The CDR is from Centellax (TR1C1-A) and the CPA is built by − PsBM CDR = Pr (C Ko ) × min Pintegrating Hit-tite Microwave where tk = ±π/2 are the evaluation boards: φ-shifters sampling points for the multi. and (ϑ. Consequently. IV. l = 0 sampling error probability of a bit. for the BMCDR based on space sampling and the CPA. the sampling error probability is expressed as phase clocks C K−π/2 or C K+π/2.

VOL.05 0.01 0. 2012 π 0 π 2π − − 1 − 2 − 3 − 4 − 5 − 6 − 7 − 8 − 9 − 1 −11 0 −100 Experim ental Theoret ical Loss of lock −75 −50 CDR −25 0 25 Phase steps. NO.136 0 − 2 π IEEE PHOTONICS TECHNOLOGY LETTERS.04 0.02 0. JANUARY 15. 2. φ [ps] 5 0 75 100 (a) 800 BMCDR C D R 700 600 500 400 | | = π rad 300 200 100 0 0 0. 24.03 0.06 0. σts 1[UI] (d) .07 0.08 Maximum RMS jitter.

Fig. (a) CDR. for a zero preamble length.close CDR is almostas the preamble length isagreement with sampling at theincreased. The BM-CDR is tested using a At standard burst-mode test setup [3].2 π − − 1 − 2 0 − π 2 π − 2π 0 π 0 Experi mental π Theoret ical 2 π l=0 − 1 − 2 − 3 − 4 − 5 7 5 − 5 (BER ) − 6 = − 6 − 7 − 8 l= 125 − 9 6 − 4 2 0 2 4 − − P hase steps. data eye.for the jitter input to the receiver and not for jitter generated by the circuitry. these represent the half-bit periodswe can (±π rad). 5. 2:1 g in a selector (HMC748LC3C). 5(a) and measure theoperation for any phase step.(near 0 As expected. 5(a) shows the experimentally BER performance of the CDR at small 10 Gb/s as a function of the phase phase step between two consecutive data shifts bits. (f) − length BER < 10 10 for worst. φ [ps] ( b ) 0 (c) π 2 π − 2 π π − 1 − 2 − 3 BMCDR C D R D 0.02 UI 100 mV CKout 36 ps −6 − 4 − 2 0 2 4 6 Phase step.relative Fig. (c) BM-CDR. (b) CDR performance with increasing preamble length.acquire lock until error-freeresults are in because theoperation is achieved.BER > 10 6 as (“1010· · ·we achieve error-free operation forthe ”pattern) canany phase step | ϕ| ≤ 2π rad withprobabilistic be inserted atzero preamble bits allowing formodel accounts the beginninginstantaneous phase acquisition. BERthe CDR to settle down andexperimental − < 10 10. For the phase However. Tobits we perceive error-freeFigs. for example. BER performance versus phase step for zero preamble length. In Fig. reducing thetheoretical time of theeffective throughput andbound is CDR. 5(c). Alexander PD (HMC6032LC4B).(c). the worst-case phaseor ±2π steps are around ±50 ps becauserad). the use of a preambleCDR. φ [rad] ( e ) (f) Fig. (d) Preamble versus rms jitter to achieve case phase step | | = π rad. φ [rad] Log − 7 − 8 − 9 1 0 BMCDR − 1 1 6 −100 −75 − 5 0 −25 0 25 5075 1 0 0 Phase steps.01 UI 0. VCO phase noise. increasing delay. 5(d) shows the number of preamble bits required by the BM-CDR and CDR to obtain − a BER ≤ 10 10 as a function of maximum allowable rms . After 125 preamblepredictions in data bit. the acquisition introduces overhead. For the proposedoptimistic for − preamble bitsBM-CDR as depicted in Fig. lock. resultin AND gate (HMC672LC3C).04 UI o ut − 4 − 5 − 6 − 7 − 8 − 9 − 1 0 −11 0.Recovered data and clock. and D-FF loss of (HMC673LC3C). there is an improvementthe theoretical middle of eachin the BER. and therefore the CDR iseasily sampling near the edges of theachieve error-free of the packet to help the PLL ofThe operation. (e) Effect of rms jitter. 5(b).

and D. “Burst-mode clock and data recovery [4]J. vol. Zicha. 2006.. Oct. H. Where as the BMCDR achieve s instantaneousnovel BM-CDR architecture based phase on space sampling that achieves acquisition for any phase stepinstantaneous phase acquisi-tion when rms jitterwhich can be used to increase the σts ≤ 0. pp. pp. Plant. this is true for any phase step |imposs ϕ| ≤ 2π rad. Y. 11. H. Plant. Netw.jitter for the worst case phase stepsignal | ϕ| = π rad.5 ps. S. no. feasible for the CDR to achieveAs a instantaneous phase acquisition as functio n of a jitter-free phase steps. Technol. and Y. no.can refine theoretical models of The responsemultiaccess networks and provide to CIDs isinput for establishing realistic power similar to thatbudgets. Terada. 5(f)eloquent. 541–542. Ohtomo. N. REFERENC ES J. [5]J. pp. USION B.. C We have demonstrated a and experimental. A. Shastri. vol./Oct. “Clock recovery from random binary data. 2010. Kimura. [3]A. Sep. Alexander. ” IEEE J. 43. N. Shastri and D. 5(e) plots the BER perfor mance for differe nt rms jitter and zero preamb le bits.3 Gb/s burst-mode CDR using a DAC. Katsurai. M’Sallem. 1298–1320. 16. 5.04practic ally UI. V. 1– 9. J. and D. Fig. Fig. 2. This model recovered clock is 2. V.” J. 1. S.. Commun. Lett. However. 73–75. V. Li.” Electron. “5/10- [1] Gb/s burst-mode clock and data recovery based on semiblind oversampling for PONs: Theoretical . in optical multiaccess networks using broadband PLLs. Lett. vol. Opt. pp. 22. vol. vol. 18. “Experimenta l study of burst-mode reception in a 1300 km deployed fiber link. Thesampled BM-CDRs validated by the rms jitter of theexperimental results. L. Topics Quantum Electron. D. instantaneous phase acquisition (lis = 0) when the rms jitter σts ≤ 0. “A 10.network’s: power budget by the CDRreducing the burst-mode sensitivity performance penalty. The proposed BM. it is notible. 2010.” IEEE J. Jan.-B. Jan. Plant.σtmaxs CDR is able to achieve= 0 UI. Faucher. response to aWe have also developed a 215 − 1 PRBSprobabilistic theory for spacepattern. Rusch. 1. no. Solid-State Circuits. Nishimura. Dec. recovered data and clock inproviding a cost-effective solution. scalable architecture shows the eyeleverages the design of low diagram of thecomplexity commercial electronics. or effective throughput by degrades withincreasing the information rate. no. no.. Yoshimoto. 2008.04 UI. pp. 2921– 2928.” IEEE Photon. 1. 1975. K. in [1]. Sel. LaRochelle. [2]B. 12. J. Our increasing rms jitter. V.

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