Removal of Decaying DC Offset in Current Signals for Power System Phasor Estimation

Amir A. A. Eisa, K. Ramar

Multimedia University, Malaysia amir.abdelfattah@mmu.edu.my cannot be tolerated in some relaying applications such as high performance relays and fault locators. Many techniques have been proposed to eliminate the effect of decaying dc offset on phasor estimation. Benmouyal [1] has proposed a digital mimic filtering technique to attenuate the decaying dc component. This filter, however, achieves its best performance once the time constant of the decaying dc component is equal to the time constant of the mimic filter. Another shortcoming of the mimic filter is that it acts as a high-pass filter that amplifies high frequency noise. Gu and Yu [2] have proposed a method that applies full-cycle DFT for one cycle plus two samples to calculate and compensate for the dc offset. Reference [3] presents an algorithm which is based on applying weighting least error squares (LES) technique to a three-state signal model. The estimator has the form of the regular recursive full-cycle DFT with additional adaptive correction for the decaying dc component. The algorithm proposed in [4] uses three consecutive phasors computed by DFT to estimate the parameters of the decaying dc component. The computations involved, however, are rather complex. An algorithm that uses partial summation technique to eliminate the influence of decaying dc offset on the Fourier algorithm has been proposed in [5]. Three simplified algorithms have also been proposed to compromise between computational burden and accuracy. Sidhu et al. proposed a modified DFT-based fullcycle phasor estimation algorithm that is immune to decaying dc [6]. The algorithm removes the decaying dc offset from phasor estimates by means of two orthogonal digital DFT filters tuned at different frequencies. This algorithm, however, requires extensive amount of computation to calculate the decaying dc parameters. Balamourougan et al. [7] improved on the technique proposed in [6] by using three off-line look-up tables in order to reduce the computational burden. Reference [8] has implemented the technique proposed in [6] and [7] using half-cycle LES filters. A computationally efficient method for removing the exponentially decaying dc component has been presented in [9]. The method exploits the periodicity of the fundamental frequency component and the integer harmonics to calculate the parameters of the decaying dc offset using one cycle plus two samples. This paper proposes a new method for the removal of decaying dc offset from current signals. The method is based on the fact that sinusoidal signals and exponential signals have different mathematical properties. Namely, a purely

AbstractThis paper presents a new method for the removal of decaying dc offset from current signals in digital protective devices. The method is based on the fact that a purely sinusoidal signal has a zero average over a full cycle or multiples of the full cycle of its fundamental frequency, whereas an exponential signal has a nonzero average over that same interval. A full cycle plus one sample of post fault data are required to calculate the parameters of the decaying dc offset in order to completely eliminate it from the current signal. Decaying dc offset removal is carried out before applying the current signal to the digital filter used for phasor estimation. The method has been tested by applying it to a fault current signal generated by computer simulation. Results obtained indicate that the method has greatly improved the performance of the full-cycle DFT algorithm. The new method can be applied in real time on digital protective devices because of its simplicity and computational efficiency. Index TermsDigital protective devices, removal of decaying dc offset, fault currents, full-cycle DFT, phasor estimation.

I.

INTRODUCTION

Most digital protective relays are based on phasors. The relay is usually required to estimate the magnitude and the phase angle of the fundamental frequency component in current and voltage signals as accurately and as quickly as possible. The phasor estimator is required to retain only the component of interest and reject all unwanted components such as harmonics, subharmonics, exponentially decaying dc offset, high frequency oscillations, and noise. Decaying dc offsets significantly affect the performance of digital protective relays. This effect, however, is more pronounced on current signals than on voltage signals. Both the initial magnitude and time constant of the decaying dc component are unpredictable because their values depend on random factors, such as fault resistance, fault location, and fault inception angle. All digital filter algorithms, such as full-cycle DFT, half-cycle DFT, least-error-squares (LES), cosine, Walsh, and Kalman filters, are affected, to different extents, by the presence of decaying dc offset in their input signals [1]. Generally, the decaying dc offset will cause an initial overshoot followed by oscillations in the output of the filter. The output will eventually converge to the final value after a period of time that depends on both the algorithm used and the time constant of the decaying dc offset. The decaying dc component therefore seriously affects the accuracy and convergence speed of digital filter algorithms. Such errors

sinusoidal signal has a zero average over a full cycle or multiples of the full cycle of its fundamental frequency, whereas an exponential signal has a nonzero average over that same interval. The removal of the dc offset is performed before applying the current signal to the digital filter used for phasor estimation. II. PROPOSED METHOD Let the signal of interest be represented by:
y (t ) = Ae t / +

1 T

t + T t

y(t ) dt = T (e
T

T /

1) e t /

(5)

To solve (3) and (5) for the unknowns A and , let:

Avg 0 = 1 T

y(t ) dt ,
0

(6)

An cos( n t + n )

Avg1 =

(1)

1 T

t + T t

y(t ) dt ,

(7)

n =1

and

magnitude of the decaying dc offset; time constant of the decaying dc offset; amplitude of the nth harmonic; n phase angle of the nth harmonic; 100 rad/s. The signal contains an exponential component in addition to a set of harmonics, which is usually limited by an antialiasing filter. If we take the average value of both sides of (1) over a complete cycle (T) of the fundamental frequency we get:
1 T
T

where A An

E = e t / . Equations (3) and (5) become:

Avg 0 = Avg1 = A N ( E 1) , T

(8)

(9) (10)

A N ( E 1) E . T

From (9) and (10) we can easily conclude that:

E= Avg1 Avg 0

y (t ) dt =

M A t / 1 e dt + ( An cos( n t + n )) dt T 0 T 0 n =1

(2)
A=

(11)

The average value of the sinusoidal part of the signal over a complete cycle of the fundamental frequency is zero. Therefore, (2) becomes:
1 T
T

N Avg 0 ln( E ) ( E N 1)

(12)

y(t ) dt = T (e
0

T /

1)

(3)

The decaying dc offset can then be removed from sample number k using:
ycor (k ) = y (k ) AE k

(13)

If the signal y(t) is sampled by taking N samples per cycle then these samples can be used to numerically compute the integral on the left-hand-side of (3). Any numerical integration technique, such as the trapezoidal rule or Simpsons rule, can be used here. After computing the value of the integral we have two unknowns on the right-hand-side of (3); the initial value A and the time constant of the exponential component. In order to evaluate these two unknowns a second equation is required. If the sampling interval is given by
t = T / N ,

The steps for dc offset removal are as follows: Avg0 and Avg1 are calculated using (6) and (7), and any numerical integration technique. 2. E and A are obtained from (11) and (12). 3. The signal is corrected using (13). Notice that a full cycle plus on sample of post fault data are required to apply the proposed method. The corrected signal (ycor) can now be used with any digital filter algorithm, such as the full-cycle DFT, to obtain the magnitude and the phase angle of the fundamental frequency phasor or those of any harmonic. 1. III. PERFORMANCE E VALUATION In order to test the performance of the proposed technique, the transmission system shown in Fig. 1 is simulated using PSCAD/EMTDC. A single line to ground solid fault is created at a distance of 50 km from bus S. The faulted phase current is sampled by the relay at bus S using a sampling rate

(4)

then we can obtain a second equation by taking the average value of both sides of (1) over the interval [t, t + T]. This results in:

~
ES

ZS

230 kV, 200 km

ZR

~
ER0

This improvement in performance is achieved by eliminating the oscillations and speeding up convergence. Because of its computational efficiency, the method can be applied in real time on digital protective devices.
3 2.5 2 Fault Current (kA)

Relay

RF

Fig. 1. The simulated transmission system.

1.5 1 0.5 0 -0.5 -1 -1.5 -2 0.85 0.9 0.95 1 1.05 1.1 time (s) 1.15 1.2 1.25 1.3

of 20 samples per cycle. The parameters of the simulated system are given in Appendix A. The fault current waveform is shown in Fig. 2. It can be seen that the fault current contains a considerable amount of dc offset. The proposed dc offset removal method is applied to the fault current waveform and the corrected signal obtained is shown in Fig. 3. It is obvious that the dc offset has been removed. The dc offset waveform (given by: y ycor) is shown in Fig. 4. Simpsons rule of integration has been used to numerically evaluate the integrals in (6) and (7) because of its high accuracy. Any other rule of integration can be used. It should be pointed out, however, that accurate rules of integration should be used if the sampling rate used is low. The full-cycle DFT algorithm is used to extract the fundamental frequency phasor of the fault current both before and after decaying dc offset removal. The magnitude and the phase angle of the fundamental frequency phasor before and after decaying dc offset removal are shown in Figs. 5 and 6. It can be seen that removing the dc offset from the current signal has greatly improved the performance of the full-cycle DFT algorithm. The oscillations have been eliminated and the convergence has become almost immediate. The proposed method is computationally efficient and can be applied in real time on protection devices. It should be noted, however, that the technique should be applied to the post-fault part of the signal only. Therefore, a fault detector can be used as the triggering mechanism for the dc offset removal procedure. IV. CONCLUSIONS A simple and numerically efficient method for the removal of decaying dc offset from current signals in digital protective device has been proposed. The method requires a full cycle plus one sample of post-fault data in order to calculate the parameters of the decaying dc offset. The removal of the dc offset from the current signal is performed before applying the signal to the digital filter used for phasor estimation. The method is tested by applying it to a fault current signal generated by PSCAD/EMTDC simulation. The results obtained demonstrate that the method is capable of completely eliminating the dc offset and thus greatly improving the performance of the full-cycle DFT algorithm.

Fig. 2. Fault current waveform before dc offset removal.

3 2.5 2 Fault Current (kA) 1.5 1 0.5 0 -0.5 -1 -1.5 -2 0.85 0.9 0.95 1 1.05 1.1 time (s) 1.15 1.2 1.25 1.3

Fig. 3. Fault current waveform after dc offset removal.

3 2.5 2 DC Offset (kA) 1.5 1 0.5 0 -0.5 -1 -1.5 -2 0.85 0.9 0.95 1 1.05 1.1 time (s) 1.15 1.2 1.25 1.3

Fig. 4. Decaying dc offset waveform.

1.4 1.2 Phasor Magnitude (kA) 1 0.8

10 m 5m 5m G2 C2 C1 10 m C3 G1

0.6 0.4 0.2 0 0.85

Before dc offset removal After dc offset removal

30 m Tower: 3H5 Conductors: chukar Ground Wires: 1/2" High Strength Steel

0.9

0.95

1.05 1.1 time (s)

1.15

1.2

1.25

1.3

Fig. 7. Transmission line tower configuration. Fig. 5. Magnitude of the fundamental frequency phasor. TABLE I CONDUCTOR AND GROUND WIRE DATA Conductors
Before dc offset removal After dc offset removal

-0.8 -1 -1.2 Phasor Phase Angle (rad) -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 0.85 0.9 0.95 1 1.05 1.1 time (s) 1.15 1.2 1.25 1.3

Ground Wires 0.0055245 2.8645 10

Radius (m) DC Resistance (ohm/km) Sag (m)

0.0203454 0.03206 10

REFERENCES
[1] [2] [3] [4] G. Benmouyal, Removal of dc offset in current waveforms using digital mimic filtering, IEEE Trans. Power Delivery, vol. 10, no. 2, pp. 621630, Apr. 1995. J. C. Gu and S. L. Yu, Removal of DC-offset in current and voltage signals using a novel Fourier filter algorithm, IEEE Trans. Power Delivery, vol. 15, no. 1, pp. 73--79, Jan. 2000. E. Rosoowski, J. Izykowski, and B. Kasztenny, Adaptive measuring algorithm suppressing a decaying dc component for digital protective relays, Electric Power Systems Research, vol. 60, pp. 99--105, 2001. Y.H. Lin and C.W. Liu, A new dft-based phasor computation algorithm for transmission line digital protection, IEEE/PES Transmission and Distribution Conference and Exhibition: Asia Pacific, vol. 3, pp.17331737, 2002. Y. Guo, M. Kezunovic, and D. Chen, Simplified algorithms for removal of the effect of exponentially decaying dc-offset on the Fourier algorithm, IEEE Trans. Power Delivery, vol.18, no 3, pp. 711717, Jul. 2003. T. S. Sidhu, X. Zhang, F. Albas, and M. S. Sachdev, Discrete-Fouriertransform-based technique for removal of decaying dc offset from phasor estimates, Proc. Inst. Elect. Eng., Gen., Transm. Distrib., vol. 150, no. 6, pp. 745--752, Nov. 2003. V. Balamourougan and T. S. Sidhu, A new filtering technique to eliminate decaying dc and harmonics for power system phasor estimation, IEEE Power India Conference, Apr. 2006. T. S. Sidhu, X. Zhang, and V. Balamourougan, A new half-cycle phasor estimation algorithm, IEEE Trans. Power Delivery, part 2, vol. 20, no. 2, pp. 1299--1305, Apr. 2005. J. F. Minambres Arguelles, M. A. Zorrozua Arrieta, J. Lazaro Dominguez, B. Larrea Jaurrieta, and M. Sanchez Benito, A new method for decaying dc offset removal for digital protective relays, Electric Power Systems Research, vol. 76, pp. 194--199, 2006.

Fig. 6. Phase angle of the fundamental frequency phasor.

APPENDIX A The parameters of the simulated transmission system are given here: Power system frequency = 50 Hz Equivalent source impedances: ZS1 = ZS0 = 52.980 ZR1 = ZR0 = 52.980 Equivalent source voltages: ES = ER = 230 kV = 15 Transmission line parameters: Line length = 200 km Transmission line tower configuration is given in Fig. 7. Conductor and ground wire data are given in Table I.
[5]

[6]

[7] [8]

[9]