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JOURNAL OF COMPUTING, VOLUME 5, ISSUE 4, APRIL 2013, ISSN (Online) 2151-9617 https://sites.google.

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A Compact Priority based Architecture Designed and Simulated for Data Sharing based on Reconfigurable Computing
Bhavya Alankar and B K Kanaujia
Abstract— Reconfigurable Computing devices are coming very strongly in the digital hardware systems due to the availability of
ready to use resources, parallel logic operations and reconfigurable designs. The usage of Reconfigurable systems in real time domain is also a very fruitful proposition as the FPGA devices are coming with processing cores for Real Time data processing. This paper mainly focuses on the application of Reconfigurable Computing systems in the data sharing domain and in order to depict this application we have designed and simulated a priority based data sharing architecture through which we can interface two Processors, which in turn can intercommunicate with each other. The main advantage of this architecture is that it is highly compact, easy to use and designed using a modular approach so that it could be easily implemented on Reconfigurable hardware. All the different modules along with the complete architecture is simulated using modelsim 6.0 and synthesized using Xilinx 7.1(iSE).
Index Terms—Reconfigurable Computing, FPGA, Master-Slave processor.

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1 INTRODUCTION
econfigurable computing based architectures offers a unique opportunity to address the memory access and interfacing issues via customization. Improvements can be achieved by creating specialized architectures and this architecture is mainly designed to explore those opportunities of Reconfigurable computing [1], [2], [3]. In our design FPGA Spartan-3 kit [7] is acting as an interactive device through which two processors can intercommunicate with each other such that one processor has been given priority over the other processor and their priority is been decided by the conflict resolving block. Initially this design is simulated for 8-bit processor but it can be extended up to any number of bits. The organization of this paper is as follows: Section 2 shows the design overview and the details of different functional modules. Section 3 depicts the simulation waveform of the architecture. Section 4 discuss the conclusion and future work

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the  priority  over  slave  and  we  have  used  multiplexed  address  data  bus  for  the  master  which  can  be  used  for  slave as well.       Moreover  in  our  design  we  have  used  the  signals  of  peripheral  component  interconnect  bus  [5]  for  the  master  processor  to  communicate  and  the  slave  processor  can  communicate  via  busy,  address,  data  and  read  write  sig‐ nals  as  shown  in  Fig  1.,  but  depending  upon  the  applica‐ tion you can modify them.       The  detailed  description  of  each  of  the  blocks  depicted  in  the  main  block  diagram  along  with  their  functional  description  and  device  utilization  summary  is  given  and  it  can  be  seen  that  the  architecture  is  highly  compact  as  the device utilization is quiet low.   

2.1 Conflict Resolving Block
This  block  grants  the  control  for  accessing  Dual‐port  memory  to  the  requesting  system.  we  are  mainly  having  two  signals  viz  slave  request  (pr)  and  master  request  (pcirq) and the main functioning of this block is to resolve  the  conflict  between  them  by  making  either  slave  busy  (probussy) or master busy (pci bussy) as low (see Table 1)  TABLE 1 TRUTH TABLE OF CONFLICT RESOLVING BLOCK pcirq master Low Low High High pr slave Low High Low High pcibussy master Low Low High High Probussy slave High High Low High

2 DESIGN OVERVIEW
The  designed  architecture  is  fully  user  friendly,  flexible  and synchronous. One Processor acts as MASTER and the  other Processor acts like a SLAVE and can intercommuni‐ cate  with  each  other  [4].  Memory  provided  via  two  sepa‐ rate and fully synchronous ports. Master will always have 
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 Bhavya Alankar is a Assistant Professor, Hamdard University, New Delhi, India.  B.K. Kanaujia is a Associate Profoessor, Ambedkar Institute of Advanced Communication Technologies & Research (AIACTR) Govt. of N.C.T..New Delhi, India.

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2.2 Interactive Controller Blocks
When both (Master and Slave) request for the access of  memory  ,The  Conflict  resolving  block  drives  the  busy  line  of  the  Master(pcibussy)  while  keeping  the  Slave  processor  in  a  wait  state  until  the  Master    finishes  its  operation.When  the  Master  generates  the  address  on  address  lines,  data  on  data  lines  and  write/read  signal  then  the  control  block  check  for  the  busy  line  of  Mas‐ ter.  When  the  control  block  receives  the  busy  line  of  Master  driven  to  low,  it  allows  the  address  on  valid  addresslines,data  on  valid  data  lines  and  wr_rd  signal  as  valid  wr_rd  signal  to  access  the  memory.  When  the  Slave Processor generates the address on address lines,  data  on  data  lines  and  write/read  signal  then  the  con‐ trol  block  check  for  the  bussy  line  of  Slave  Processor.  When  the  control  block  receives  the  busy  line  of   Slave  Processor(probussy) driven to low  it allows the address  on  valid  address  lines,  data  on  val  id  data  lines  and  wr_rd signal as valid wr_rd signal to access the memory  as shown in Fig 3. 

    Fig.1. Compact Architecture of Data sharing between  Master‐Slave.  Based on the information obtained from the above truth table, Two Boolean equations have been derived and based on that equations, following digital design of Conflict resolving block has been obtained in Fig 2.

   
              Fig.3. Interactive Controller Block 

Fig. 2.Digital design of conflict resolving block      The  device  utilization  summary  of  this  block  imple‐ mented  on  the  Spartan‐3  XC3S200  FPGA  (200  K  gates)  is  shown  in  Table  2.  And  It  shows  that  this  block  was  de‐ signed  in  such  a  way  so  as  to  utilize  the  minimum  num‐ ber of resources  on FPGA.  TABLE2 DEVICE UTILIZATION SUMMARY OF CONFLICT RESOLVING BLOCK Number of 1 out of 1920 0% slices Number of 4 1 out of 3840 0% input LUTs Number of 3 out of 173 1% bonded IOBs

       Now  its  clear  that  the  main  function  of  the  Interactive  controller  block  is  to  just  select  or  decide  whether  the  Master  or  Slave  should  access  the  memory  on  the  basis  of  the output of Conflict resolving block, So this block is just  a  combination  of  the  Conflict  resolving  block  and  the  memory read and write block.      The  device  utilization  summary  of  the  Interactive  Con‐ troller  block  implemented  on  the  Spartan‐3  XC3S200  FPGA  (200  K  gates)  is  shown  in  Table  3.  As  this  block  is  the  combination  of  mainly  the  muxes.  It  shows  the  num‐ ber  of  slices  and  other  resources  available  utilized  in  im‐ plementing the design on FPGA.             

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        TABLE 3  DEVICE UTILIZATION SUMMARY OF INTERACTIVE  CONTROLLER BLOCK  Number of slices  Number of 4 input LUTs  Number of bonded IOBs  Number of GCLKs    1 out of 1920  1 out of 3840  4 out of 173  1out of 8  0%  0%  1%  15% 

    TABLE 4  DEVICE UTILIZATION SUMMARY OF MEMORY   BLOCK    Number of slices   Number of slice flip  flops   Number of 4 input LUTs  Number of bonded IOBs  Number of BRAMs  Number of GCLKs  3 out of 3840  49 out of 173  1 out of 12  2 out of 8  0%  28%  8%  25%  9 out of 1920  16 out of 3840  0%  0% 

2.3 Memory block
It is one of the main block and as it is clear from the name  that  the  main  purpose  of  this  block  is  to  fulfill  the  storage  requirement  of  both  the  Master  and  the  Slave  Processor.  This  storage  core  is  a  dual  port  memory  of  64  k  size,  fully  synchronous  such  that  the  data  is  to  be  written  on  the  rising  edge  of  the  clock.  It  is  the  central  block  which  de‐ pends  on  the  output  of  all  the  blocks  such  that  first  of  all  the  Conflict  resolving  block  will  decide  whether  Master  or Slave Processor will access the memory and depending  on  the  output  of  that  the  controller  block  will  allow  the  valid signals to access the memory as shown in Fig.4.      The  device  utilization  summary  of  the  memory  block  implemented  on  the  Spartan‐3  XC3S200  FPGA  (200  K  gates)  is  shown  in  Table  4.  It  shows  the  number  of  slices  and  other  resources  available  utilized  in  implementing  the design on FPGA. 

3. SIMULATION RESULTS
3.1  Master  Continuous  write  and  Slave  continuous  read  cycle: In this the Master take the control from the Conflict resolving block by driving its bus request (pcirq) to access the memory. Then it broadcasts the address and data on address_data line such that first the address is send and by driving frame# as low and irdy# and trdy# driving high the address is latched and then the data is send and by driving frame# high and driving irdy# and trdy# low the data is latched and in the mean time the pciwr(Master write) signal is also made low such that the data is written in the memory.After the data is written in to the memory the data can be continuously read by the Slave processor by just giving the address in the read address line and by applying read clock and in the mean time the pw(Slave write) signal should also be high and the data ouput will be coming on the Slave processor data (pd) output line, Fig 5.  

  Fig. 4. Memory Block and Its Connectivity Fig. 5. Master Write and Slave read cycle

 

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  3.2  Slave  Continuous  write  and  Slave  continuous  read  cycle: In this the Slave processor take the control from the Conflict resolving block by driving its bus request (pr) to access the memory. Then it broadcasts the address on addresslines (pa [0:7]) and data on datalines (pd [0:7]) then it drives its write/read signal (pw) to low after that it drives its chip enable signal (pe) to low, which causes the data to be written to memory of the specified address.For reading the data from memory the Slave processor broadcasts the address on addresslines (pa [0:7]) then it drives its write/read signal (pw) to high after that it drives its enable signal (pe) to low, which causes the data to be read from the memory corresponding to the specified address, as shown in Fig  6.

4 CONCLUSION
The  performance  of  any  Reconfigurable  Computing  sys‐ tem mainly depends critically upon its flexibility and ease  of  interfacing  with  other  hardware  architectures.  In  this  paper  we  have  described    an  architecture  which  could  easily  be  used  for  intercommunication  between  the  proc‐ essors  in  prioritized  manner  .  We  have  also  described  clearly  the  architecture  and  working  of  different  modules  along with their device utilization summary. The architec‐ ture is fully synthesized and simulated for inter processor  communication.  The  on‐going  work  is  the  implementa‐ tion  of  this  architecture  using  FPGA  kit  along  with  the  microcontrollers  which  could  easily  depicts  the  inter  processor  communication  in  real  time,  as  this  architecture  is  basically  designed  to  support  the  advances  in  Recon‐ figurable Computing. 

REFERENCES
[1] Joa  O  m,.  P.  Cardoso,  Pedro  C.  Diniz  and  Markus  WeinHardt,  Compiling  for  Reconfigurable  Computing:  A  Survey,  ACM  Computing Surveys, Vol. 42, No.  4, Article 13, Publication date:  June 2010.  Katherine    Compton  and  Scott    Hauck,    Reconfigurable  Com‐ puting:  A  Survey  of  Systems  and  Software,  ACM  Computing  Surveys, Vol. 34, No. 2, June 2002, pp. 171–210.  T.J.  Todman,  G.A.  Constantinides,  S.J.E.  Wilton,  O.  Mencer,  W.  Luk  and  P.Y.K.  Cheung  Reconfigurable  Comput‐ ing:architectures  and  design  methods.published  in  IEE  Proc.‐ Comput. Digit. Tech., Vol. 152, No. 2, March 2005  Banerjee,T.P,konar,chaudhary  High‐speed  communication  system  developed  using  FPGA  based  CAM  implementation  published in ICETET‐2009  PCI bus manual website  :http://www.pciadda.com/manual/manual1.html  Xilinx user  guide:http://www.xilinx.com/itp/xilinx10/books/docs/xst/xst.pd f  FPGA Spartan‐3  website:  http://www.xilinx.com/support/documentation/boards_and_kit s/ug230.pdf 

[2]

Fig. 6. Slave Write and Slave read cycle 3.3  Master  Continuous  write  and  Master  continuous  read  cycle:  In this the Master take the control from the Conflict resolving block by driving its bus request (pcirq) to access the memory. Then it broadcasts the address and data on address_data line such that first the address is send and by driving frame# as low and irdy# and trdy# driving high ,the address is latched and then the data is send and by driving frame# high and driving irdy# and trdy# low ,the data is latched and in the mean time the pciwr(Master write) signal is also made low such that the data is written in the memory. After the data is written in to the memory the data can be continuously read by just giving the address in the same way on the address_data line and afterwards just driving the pciwr signal as high such that the data will appear on the output line(pcida), Fig 7.

[3]

[4]

[5] [6]

[7]

Bhavya Alankar is a Assitant Professor in Hamdard University, New Delhi. He has acquired his Master degree in VLSI design. His main research interests areReconfigurable computing, VLSI design and Software Engineering.He is having years of research experience in VLSI design and published numerous research papers and conducted workshops related to his research area. B K Kanaujia is a Associte Professor in Ambedkar Institute of AdvancedCommunicationsTechnologies& Research (AIACTR), Govt. of N.C.T.New Delhi, India. He did his M.Tech. & Ph.D. from Electronics Engineering Department of Banaras Hindu University Varanasi, His keen research interest are in design and Modeling of Microstrip Antenna, Dielectric Resonator Antenna, Left handed Metamaterial Microstrip Antenna, Shorted Microstrip Antenna Wireless Communication, Wireless Communication, Microwave Engineering,Reconfigurable computing and VLSI design etc.Till date he has been credited to publish more than 45 research papers in peerreviewed journals and International/national conferences.

Fig. 7. Master Write and Master read cycle