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D.Module2.

DM642
Board Revision 1.0 SUMMARY •

Technical Data Sheet
Document Rev. 1.1 Mar/2009

D.SignT
Digital Signalprocessing Technology

High performance fixed- point DSP module for video and image processing, radar, sonar, ultrasonics, and biometrics 5760 MIPS Texas Instruments TMS320DM642 DSP Three 80 MHz buffered video ports for cameras, video- interfaces, and high-speed ADCs and DACs 533 Mbytes/s external bus bandwidth Large on-board memories: 64M- Byte SDRAM, 8M- Byte non-volatile Flash

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10Base- T / 100Base- TX Ethernet controller High- speed USB2.0 peripheral controller Dual- UART with auto- flow control, receive and transmit FIFOs, RS232 and RS422/485 interface 3.3V single- supply, Supervisor and Watchdog D.Module2.BIOS programming support for all on-board resources, USB / RS232- based Setup Utility for convenient fieldmaintenance

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BLOCK DIAGRAM

JTAG I²C PRGIO

8

EMU I²C GPIO TMS 320 DM 642

VP0,1,2

EXP (Video Ports)

ETH

PHY

MDII McBSPs Timer, Int, GPIO EMIF

6 6

McBSP0 McBSP1

DATA (32) ADDR (20)

EXT BUS

CTRL (12)

EXT BUS Controller and Driver

32 bit

64 bit SDRAM 64 MByte

GPIO INT 4 3

Local Bus Controller and Driver

Clocks

BOARD Configuration Registers

8 bit

8 bit

Flash 8 MByte

PRGIO

8

COM0 COM1

RS232 Dual-UART RS422/485

8 bit

Reset, Supervisor, Watchdog

Power Supply, USB 2.0 USB Controller 16 bit Voltage Regulators

The D.Module2 series represents the next generation of high-performance,stand-alone DSP boards. These boards are optimized for highest I/O bandwidth to satisfy even de­ manding applications. The 32-bit wide external bus, con­ figured in synchronous mode, can transfer up to 533 Mbytes/s of data between DSP and peripherals.

The self-stacking design allows to build complete signal processing systems by stacking the required DSP, I/O, data acquisition,and networking modules. If data preprocessing is needed an FPGA module can be inserted between data ac­ quisition and DSP.

© D.SignT 2006

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Module2. Four GPIO signals are configurable in the Board Configuration Register and allow to route DSP Timer and/or GPIO signals to external peripherals.20 Mbytes/sec data throughput can be achieved. D. and synchronous serial interfaces.Mod­ ule2. throughput can be achieved. Up to 133 Mbytes/sec.DM642 Besides the high-speed peripheral bus all D. 12 control signals. In synchronous configuration the bus drivers operate re­ gistered to maximize setup and hold timing margins for the external peripherals. (block)write and (block)read functions. The Flash Memory also stores the board's hardware set­ tings.0 device controller provides a high-speed interface for data exchange with a PC.BIOS greatly simplifies USB communications by provid­ ing a predefined interface with up to four user-definable end­ points. An 8 Kbyte Fifo buffers incoming and outgoing data.SignT Digital Signalprocessing Technology Programming support for all on-board peripherals is provided by the D. and high-speed A/D and D/A converters. These sectors hold the module hardware configuration and the Re­ covery utility program.. provides straightforward field maintenance via USB or RS232: data and program upload. USB The Philips isp1582 USB2.SignT 2006 2 . The PCB uses auxiliary GND planes to shield signals and provide controlled impedance signal paths. The bus interface uses a 32 bit wide data bus. user data. and the Setup and Recovery Utility programs. Operating at up to 133 MHz. A Setup Utility. The DSP accesses the USB controller with CPU or DMA data transfers.Module2. SDRAM 64 Mbytes. Two boot sectors are hardware write protected.BIOS API functions. 64-bit wide SDRAM is used on the D. 20 address lines. config­ uration. video encoders and de­ coders.Module2. achieves data transfer rates up to 533 Mbytes/sec and sup­ ports FlyBy DMA transfers between SDRAM and external devices. UART A dual-channel UART with RS232 and RS422/485 line in­ terface provides additional communication paths. An extra connector is re­ served for DSP-specific extensions like the video ports in case of the DM642 module.DM642 is built around the Texas Instru­ ments TMS320DM642 fixed-point DSP. EXTERNAL BUS INTERFACE The bus interface is used to connect external peripherals like data acquisition boards or FPGAs. and configuration settings. and the connector pinout provides ample signal return ground connections. six ALUs. FLASH MEMORY 8 Mbytes non-volatile Flash Memory provide storage for application programs. an US­ B2. and bus timings. The D.. Synchronous mode. synchronous or asynchronous operation. and data transfer. The TM­ S320C64x™ core provides 64 32-bit general purpose re­ gisters. user-programmable I/O ports. The boot­ load function loads and executes programs stored in the Flash Memory.BIOS and the application without any special programming equipment. Asynchronous transfer timing is widely program­ mable. These ports allow glueless con­ nection to most image sensors. configuration changes. The advanced L1 and 4-way L2 caches of the DM642 further optimize memory performance. 15.0 peripheral controller. these sectors remain intact and allow to recover the D. hence no software adaptations due to peripheral component or silicon revision changes are re­ quired in the user and application programs. The DM642 also features three built-in video ports with capture and display buffers.DM642.Module2 DSP boards provide a variety of interfaces: two UARTs. and three external interrupt or DMA request inputs. The ALUs support single 32-bit. Even in case the flash memory is completely erased or overwritten by accident. covering initialization. Inter­ rupt and isochronous transfers are supported. and basic debugging functionality are available without the need for special emulator or programming equipment. External device can request additional wait states via the WAIT_N input.D. Bulk. the power supply lines are extensively filtered. Two predecoded memory areas are available. also resident in the Flash Memory. supporting © D.Module2. It is configurable to asynchronous and synchronous mode. the D. PROCESSOR The DModule2. Hardware dependencies are en­ capsulated by the BIOS. The bus drivers source/sink up to 24mA and are able to drive long signal lines with passive or active termination. and a function to program the Flash with Intel-Hex files.Mod­ ule2. The D. or quad 8-bit operations per cycle. a throughput of 1 Gbyte/s can be achieved. double 16-bit.BIOS functions provide erase. 7OUT) can be used. SDRAM can be used for program code and data. making this DSP an excellent choice for image pro­ cessing and related algorithms. a set of functions resident in the module's Flash Memory. The high-speed design required special care for signal in­ tegrity and EMC. and two multipliers. which can be indi­ vidually configured to different data formats.Module2. In user-defined configurations up to 14 end­ points (7IN.BIOS.

video en­ coders / decoders.Module2. using the DM642 built-in MAC and an on-board PHY and magnetics. ETHERNET The D. and other options are configured ac­ cordingly. and brownout conditions.BIOS provides con­ figuration and data transfer functions. Ethernet opens the door to remote control and mainten­ ance.Module2. provide a high-speed serial interface for A/D and D/A con­ verters and Audio Codecs.3V single sup­ ply. and control and status registers for all on-board peripherals. RS232 driver supply. It is also usable to expand the system with additional GPIO signals and at­ tach temperature monitors. is the close coupling between low-level API functions and hardware: Should one of the module's peripherals need to be substituted during product lifetime.SignT Digital Signalprocessing Technology Note: The TMS320DM642 McASP0 signals are not avail­ able on the D. database-connectivity for biometric applications. The McBSPs share pins with the Video Ports: McBSP0 shares pins VP0. and data transfer functions for the on-board peripherals. VP2 also supports Y/C mode.) are generated on-board by high-efficiency switch-mode converters and charge-pumps. The UART features 64 bytes transmit and receive Fifos for efficient block transfers and Xon/Xoff or RTS/CTS auto-flowcontrol. VP0 and VP1 share pins with the McBSPs BOARD CONFIGURATION D. the eight signals from the board logic can be reprogrammed to custom interfaces. POWER SUPPLY The D. It will reset and reboot the system if the DSP program crashes and fails to trigger the watchdog periodically. Video-over-IP surveillance systems and many more new markets. The watchdog can be enabled (but not disabled) by software. The BIOS is a set of API functions. The power sup­ ply is controlled by a supervisor chip. or permanently by closing a solder link. © D. At system start-up the Module configuration File is read and DSP clock. PWM output. D. The Board Configuration Register also provides multiplex­ ers to route internal or external interrupt events to the DSP. and the ana­ logue front-ends of data acquisition boards. the McB­ SPs can also operate as SPI master or slave interface. McBSP1 shares pins with VP1. In OEM systems. PRGIO 16 bit-programmable I/Os are available on the DM642 module: 8 GPIO signals directly connected to the DSP.DM642 provides a 100Base-Tx / 10BaseT Ethernet interface. power-off.656 mode.D. The high transfer speed up to 150 Mbits/sec also make them usable as data links to FP­ GAs or other DSPs Besides the standard mode.Module2. A highly optimized TCP/IP stack. The DModule2. e. HPI / PCI The HPI and PCI signals of the TMS320DM642 processor are not available on the D. or – preferably – stored in the Module Configuration File.DM642 D. BIOS functions cover initialization.Module2. One of these methods is activating the watchdog circuit. Image Sensors. and high-speed data converters.SignT 2006 3 .Module2. Advanced features like interrupt on change are available. All other required voltages (core voltage. All ports support raw and BT. I²C The I²C interface can be used to control and configure peripherals like Audio Codecs. and 8 implemented in the Board Logic. configuration.BIOS SYNCHRONOUS SERIAL PORTS These ports. WATCHDOG Stand-alone systems typically require methods for auto­ matic recovery from system faults. These functions are copied to SDRAM at system start-up and are available to all user programs. tailored for DSP systems.DM642 VIDEO PORTS The three video ports with built-in capture and display buf­ fers are ideally suited to connect image sensors. permanently stored in the Flash Memory. all board set­ tings are software-configurable in the Board Configuration Register. is available from D.Module2 boards use a jumperless design. called McBSP on the D. The configuration can be set by the user program. the BIOS will be adapted to the new hard­ ware and the application program will continue to work without any changes. which guarantees a proper hardware reset on power-on. etc.DM642 operates from a 3. Data transfers can be accomplished by CPU (polling or interrupts) and DMA.SignT too.DM642 up to 230 Kbaud on RS232 and 3 Mbaud on RS422/485. rather than providing them as a library.g.Module2.MODULE2. The reason to store these functions permanently in the Flash Memory. . bus clock.DM642.

blockread low-level functions for user-defined interfaces UART functions • open. and provides some basic debugging functions like reading and writing memory and memory-mapped peripher­ als. Should the Flash be erased or overwritten accidentally. blockwrite. Setup is invoked during a module reset by pulling the SETUP_N input low. upload a Module Configuration File. blockread. The Recovery utility is stored in a hardware write protec­ ted Flash sector. load and execute programs from Flash. even severe problems can be fixed in-field without special emulat­ or programming equipment. The Setup program communicates via RS232 or USB. close • configure • write. write string • read. read string Flash Memory Functions • • • • • open.SignT Digital Signalprocessing Technology USB functions • • • • • • • open. read block write Intel-Hex file Also permanently stored in the Flash Memory are the Setup and Recovery utility programs. Setup is intended for field maintenance: Service techni­ cians can upload program updates without direct access to the DSP hardware. Recovery uses a RS232 connection. Board Functions • initialize • bootload • get hardware and software revision • DSP configuration and clocking • external bus configuration and clocking © D.DM642 • delay • watchdog enable and trigger • interrupt and GPIO mapping • read and clear multiplexed interrupts SETUP AND RECOVERY PROGRAM D. this program can be used to re-install the cor­ rupted programs. close configure endpoints status change callback custom string descriptor table interrupt handler blockwrite.Module2. It allows to upload IntelHex program and data files to the Flash Memory.D. Recovery is invoked at module re­ set by pulling both SETUP_N and IN1_N inputs low. and execute diagnostics and calibration programs stored in the Flash Memory. get architecture information sector erase write.SignT 2006 4 . write block read. or at any time from within an applica­ tion program by calling the BIOS bootload function: DM2_bootload (0x8000).

0000 .... 0x8000. 0x0000. 0x9018.0000 .0003 0x9018.0000 .03FF 0x0000.DM642 MEMORY MAP Address 0x0000...8000 ...7FFF 0x0003.4000 . 0x0001..FFFF 0x9010...0000 .0167 0x9014. 0x0003.0000 0x0003.0000 ..FFFF 0x9000.. 0x0200. 0xAFFF.01FF 0x0000.000F 0x9018. 0x0003.3FFF 0x8000.. 0x0003.. 0x901C.0000 .D.0400 .0000 . 0x900F.0000 .SignT Digital Signalprocessing Technology 64 Kbytes direct mapped L2RAM or L2-cache 32 Kbytes direct mapped L2RAM or L2-cache 32 Kbytes direct mapped L2RAM or L2-cache DM642 on-chip peripheral control registers 64 bit BIOS functions 64 bit 63.98 Mbytes free SDRAM 8 bit 8 Mbytes Flash Memory in 16 banks..FFFF 0x0002.FFFF 0xB000.003F 0xA000.0000 . 0x9018. 0x9014.0000 ..001F 0x901C.0010 .FFFF BIOS SDRAM FLASH USB USB UART UART BOARD CS0 CS1 Memory IVT BIOS L2RAM L2RAM L2RAM L2RAM Location internal internal internal internal internal internal internal CE0 CE0 CE1 CE1 CE1 CE1 CE1 CE1 CE2 CE3 Width Description interrupt vector table hardware initialization and bootloader code 127 Kbytes direct mapped L2RAM D.Module2.SignT 2006 5 .FFFF 0x0180.0200 . 0x83FF. 0x0000.0033 0x8000.0000 . 0x9010..0000 . 512 Kbytes each 16 bit USB Controller 16 bit USB Controller 8 bit UART 0 8 bit UART 1 8 bit Board Configuration Registers 32 bit External Bus Interface CS0 32 bit External Bus Interface CS1 BOARD CONFIGURATION REGISTER Register USBCTRL UARTCTRL BUSCTRL WDOGCTRL DSPCTRL SETUPSTAT FLASHCTRL INTMUXLO INTMUXHI GPIOMUXLO GPIOMUXHI MUXINTEN ETHCTRL PRGIODAT PRGIODIR UART1 PHYRES DAT_IO7 DIR_IO7 UART0 UART0 DAT_IO6 DIR_IO6 MUXINTSRC UART1 D7 USBRES UARTRES RESOUT DSPRES CONFIG D6 ENDIAN INT5_SOURCE INT7_SOURCE GPIO1 GPIO3 PHY PHY DAT_IO5 DIR_IO5 CPLD CPLD DAT_IO4 DIR_IO4 USB USB DAT_IO3 DIR_IO3 DAT_IO2 DIR_IO2 D5 MACEN A22 D4 D3 D2 INTSTAT RDREG DSPCLK SETUP A21 IN1 A20 INT4_SOURCE INT6_SOURCE GPIO0 GPIO2 INTSTAT DAT_IO1 DIR_IO1 LEDSTAT DAT_IO0 DIR_IO0 D1 EOT_WR DRVEN_1 FLYBY ENABLE D0 EOT_RD DRVEN_0 SYYNC TRIGGER IN0 A19 BUSCLK © D. 0xBFFF.

fixed-point.. max. 64 bits wide.8V output drive: external bus interface: ± 24mA. 8 bits wide Philps isp1582 USB2.SignT 2006 6 . two Timers with external inputs and outputs.0 up to 14 endpoints. DMA support 16C752 dual-channel UART. 32 bit wide. supports raw and BT. a third 32 bit wide timer is available with internal clocking only 32 bit wide data bus.8 x 58. 64 bytes transmit and receive Fifos. 12 control signals supports synchronous and asynchronous operation. 8 Kbyte shared FIFO. up to 5760 million instructions per second 8/16/32/64-bit native data type support configurable core clock: 480. supports up to 400 Kbits/sec. configurable as master or slave built-in in DSP. operating at up to 133 MHz.2V. supports raw and BT. 0. 230. independent receive and transmit channels.656 format Note: shares pins with McBSP0 VP1: 10 bit wide. +85°C DSP core clock 480 or 600 MHz external bus and SDRAM clock 83. 1Gbyte/sec throughput 8 Mbytes non-volatile Flash Memory.3 V ± 5% TBD 0 .SignT Digital Signalprocessing Technology Texas Instruments TMS320DM642.DM642 SPECIFICATIONS DSP D. or 133 Mhz 3 external interrupt inputs. Y/C. TDM. up to 80 MHz clock VP0: 12 bit wide.5V. DMA support. timeout: 1 second standard 14-pin header. 2V. supports USB 1. Serial Ports Video Ports Watchdog Emulation Supply Voltage VCC Power Consumption Operating Temperature Logic Levels Size Weight Connectors industrial grade version operating temperature -40 . BUS1 and BUS2 : Molex 71436-2164 Emulator: standard 14-pin header Memory USB UART Ethernet I²C Timer External Bus Interface Sync. internal or external clocking. 3. RS232 and RS422/485 line interface max. 600. -0. on-board PHY and magnetics built-in in DSP. 100. compatible with all JTAG inc-circuit emulators for TMS320C64x™ devices 3. RTS/CTS) 100Base-Tx and 1Base-T. Low Level min. sector architecture .3 or 100 MHz © D. 16 Kbyte level-1 program cache 64 Mbytes SDRAM. standard. programmable and external wait states up to 533 Mbytes/sec throughput in synchronous mode configurable bus clock: 83. Auto-flow-control (Xon/Xoff. and BT. with built-in capture / display buffers. MAC built-in in DSP.. +70 °C LVTTL. 3 Mbaud RS422/485. supports raw.4 mm.4 mm if JTAG connector is removed) 36g COM. McBSP1 with VP1 3. all others ± 8mA 86.1 and USB 2. overall height: 19.656 format Note: shares pins with McBSP0 VP2: 20 bit wide.Module2.656 format enabled by software or hardware.0 peripheral controller. 20 address lines.5mm (can be reduced to 15. High-Level min. and SPI mode data rate up to 150 Mbit/sec Note: McBSP0 shares pins with Video Port VP0. max. or 720 MHz 256 Kbyte DSP-internal direct mapped or level-2 cache DSP-internal 16 Kbyte level-1 data cache. EXP.D.4 Kbaud RS232. also using as DMA trigger 2 McBSPs. 125.

© D. and strobe cycles are programmed in the EMIF control registers. 100 MHz (10 ns cycle time).3 ns 8 ns ind.5 ns *1) setup. the strobe cycle ends.DM642 TIMINGS external bus asynchronous read D.Module2. grade 1.SignT Digital Signalprocessing Technology BUSCLK CSx_N OE_N A19:A0 BE3:0 t1 RD_N t4 D31:D0 t6 WAIT_N t7 t5 t2 t3 Timing t1 t2 t3 t4 t5 t6 t7 min max Description address and control signals setup before read strobe activated read strobe width address and control signals hold after read strobe deactivated data valid before read strobe deactivated data valid after read strobe deactivated WAIT_N high before BUSCLK rising edge *2) WAIT_N high after BUSCLK rising edge *2) programmed SETUP cycles *1) programmed STROBE cycles *1) programmed HOLD cycles *1) 10.4 ns 0 ns 5. The timing is based on BUSCLK.D. Two cycles after WAIT_N is high. the current bus cycle is extended until WIAT_N is sampled high.3 MHz (12 ns cycle time). 125 MHz (8 ns cycle time) or 133 MHz (7.5 ns cycle time) *2) WAIT_N is sampled two cycles before the end of the programmed strobe period. which is programmable to 83. hold.SignT 2006 7 . If WAIT_N is found low at this time.

D. the strobe cycle ends. grade 2.5 ns cycle time) *2) WAIT_N is sampled two cycles before the end of the programmed strobe period.4 ns data hold after control signals invalid 6. 100 MHz (10 ns cycle time). Two cycles after WAIT_N is high.6ns ind.SignT Digital Signalprocessing Technology BUSCLK CSx_N A19:A0 BE3:0 t1 WR_N D31:D0 t4 t2 t3 t5 t6 t8 t9 t7 WAIT_N Timing t1 t2 t3 t4 t5 t6 t7 t8 t9 min max Description address and control signals setup before write strobe activated write strobe width address and control signals hold after write strobe deactivated bus driver active after control signals valid programmed SETUP cycles *1) programmed STROBE cycles *1) programmed HOLD cycles *1) 2. grade 1.DM642 external bus asynchronous write D. hold.9 ns data valid after control signals valid 9. grade 5.3 ns 8 ns ind. If WAIT_N is found low at this time.6ns ind.5 ns WAIT_N high before BUSCLK rising edge *2) WAIT_N high after BUSCLK rising edge *2) *1) setup. and strobe cycles are programmed in the EMIF control registers. the current bus cycle is extended until WIAT_N is sampled high. which is programmable to 83.3 MHz (12 ns cycle time). The timing is based on BUSCLK. 125 MHz (8 ns cycle time) or 133 MHz (7.9 ns bus driver disabled after control signals invalid 9. © D.Module2.SignT 2006 8 .4 ns 6.

125 MHz (8 ns cycle time) or 133 MHz (7. unregistered reads however offer one more pipeline cycle between read command and data.Module2.7ns 0 ns 0. 100 MHz (10 ns cycle time).7ns BUSCLK. is programmable to 83.4 ns 5.9 ns Description BUSCLK rising edge to address and control signals valid address and control signals hold after BUSCLK rising edge unregistered reads: data setup to BUSCLK rising edge registered reads: data setup to BUSCLK rising edge unregistered reads: data hold after BUSCLK rising edge registered reads: data hold after BUSCLK rising edge 1.D. grade 1.9 ns 7 ns ind. © D.SignT 2006 9 .DM642 external bus synchronous read D.5 ns cycle time) The synchronous interface is configurable to registered or unregistered reads. Registered reads simplify the interface be­ cause of relaxed data setup timing.SignT Digital Signalprocessing Technology BUSCLK t3a D31:D0 not registered D31:D0 registered CSx_N A19:A0 RD_N n n+1 n+2 n+3 n t1 n t3b n+1 t4a n+1 t4b n+2 t2 n+3 n+1 n+1 Timing t1 t2 t3a t3b t4a t4b min max 4.3 MHz (12 ns cycle time).

grade BUSCLK. is programmable to 83. Please refer to the Texas Instruments TMS320DM642 data sheet for de­ tailed information © D.6 ns 8 ns ind.SignT Digital Signalprocessing Technology BUSCLK t3 D31:D0 n t4 t5 n+1 n+2 t6 n+3 t1 CSx_N A19:A0 WR_N n n+1 n+2 n+3 t2 Timing t1 t2 t3 t4 t5 t6 min max 4.D. 100 MHz (10 ns cycle time). 125 MHz (8 ns cycle time) or 133 MHz (7.Module2.4 ns 2 ns 7.4 ns 2 ns 6. McBSP Timings these signals are directly connected to the DSP.9 ns 1. grade 4.3 MHz (12 ns cycle time).DM642 external bus synchronous write D.9 ns Description BUSCLK rising edge to address and control signals valid address and control signals hold after BUSCLK rising edge bus driver active after BUSCLK rising edge BUSCLK rising edge to data valid data hold from BUSCLK rising edge 1.5 ns cycle time) Video Ports.SignT 2006 10 .5 ns ind.3 ns bus driver disabled after BUSCLK rising edge 8.

used to detect USB cable USB power and reference signal ground USB data. non-inverted signal USB data.56. active low.46.36. RS232 RTS (if RS422: TXD0-) UART0. RS422 non-inverted data output (if RS232: TXD1) 100Base-Tx Ethernet ground 100Base-Tx Ethernet non-inverted data input 100Base-Tx Ethernet inverted data input 100Base-Tx Ethernet non-inverted data output 100Base-Tx Ethernet inverted data output I²C Bus Clock. internal 4K7 pull-up programmable I/O signal from Board Logic GPIO3.47.53 54. DIF – differential signal © D.8 9 10 12 11 13 15 14 16 19 20 21 22 25 27 26 28 29. 35. IO – bidirectional.. RS422 non-inverted data input UART1.51. RS232 data input (if RS422: TXD0+) UART1..24.57. RS422 inverted data output (if RS232: RTS1) UART1. 59.58.40.50. internal 10K pull-up.3V Setup Input.D. RS422 inverted data input (if RS232: CTS1) (if RS232: RXD1) UART1. internal 4K7 pull-up I²C Bus Data. 0V Power Supply Input.4 5. supplied by Host or Hub. RS232 CTS (if RS422: RDX0-) UART0. inverted signal UART0. internal 10K pull-up.7. 30 31 33 32 34 37 38 43.63 I DIF I DIF O DIF O DIF IOZ IOZ IOZ IOZ Type PWR PWR I I I I I I IO DIF IO DIF I O I O I DIF I DIF O DIF O DIF Description Power Supply Input. GPIO9.DM642 PINOUT AND SIGNAL DESCRIPTION COM Connector Signal GND_IN VCC_IN SETUP_N IN0_N IN1_N RESIN_N USB_VCC USB_GND USB_D+ USB_DCTS0 RTS0 RXD0 TXD0 RXD1RXD1+ TXD1TXD1+ ETH_GND ETH_RX+ ETH_RXETH_TX+ ETH_TXSCL SDA PRGIO0. start Recovery-Utility if SETUP_N and IN0_N are found low at reset active low. 49. 44.15 SGND Pin 1.. Z – high impedance.3. PWR – power.52.18.2.Module2.45.GPIO15 from DSP Signal Ground (signal current return path) I – Input.64 17.41. internal 10K pull-up. O – Output. start Setup-Utility if found low at reset D. 60.SignT Digital Signalprocessing Technology active low.SignT 2006 11 .62.23. internal 10K pull-up USB Power.6.48.7 PRGIIO8. RS232 data input (if RS422: RXD0+) UART0. reserved for configuration Reset Input.55. active low. 3.61.

12. 18.30. 7.46.25.SignT 2006 12 .20.5. O – Output.57.27 VP2CTL0 VP2CTL1 VP2CTL2 VP2CLK0 VP2CLK1 VP1D0 VP1D1 VP1D2 VP1D3 VP1D4 VP1D5 VP1D6 VP1D7 VP1D8 VP1D9 VP1CTL0 VP1CTL1 VP1CTL2 VP1CLK0 VP1CLK1 VP0D0 VP0D1 VP0D2 VP0D3 VP0D4 VP0D5 VP0D6 VP0D7 VP0D8 VP0D9 VP0D10 VP0D11 VP0CTL0 VP0CTL1 VP0CTL2 VP0CLK0 VP0CLK1 STCTL VCTL SGND 28 29 31 32 34 35 36 BUS2-58 * BUS2-59 * BUS2-57 * 37 BUS2-54 * BUS2-56 * BUS2-55 * 39 40 42 44 43 45 47 48 BUS2-51 * BUS2-52 * BUS2-49 * 50 BUS2-46 * BUS2-48 * BUS2-47 * 51 52 53 55 56 58 59 60 63 64 1.. PWR – power * multiplexed with McBSP peripheral © D.Module2.15.13.8.SignT Digital Signalprocessing Technology VP2D0.22. 17.54. 23.11.38.3.14. Z – high impedance. IO – bidirectional.4.26.6.41.9.24.19..VP2D19 2.10.2 DAC Output for Genlock VCXO Signal Ground (signal current return path) I – Input. 33.D. 49.21.DM642 EXP Connector Signal Pin Type IO Description Video Port 2 data D. 62 IO Video Port 2 programmable control signals IO IO Video Port 2 programmable clocks Video Port 1 data IO Video Port 1 programmable control signals IO IO Video Port 1 programmable clocks Video Port 0 data IO Video Port 0 programmable control signals IO I O Video Port 0 programmable clocks Master Clock Input for VP0.61.16.

41.42.38.54.35. 28. INT2_N BE2_N.50. active low Wait State Request.37. 7. asserted during Read Cycles Read Strobe.SignT 2006 13 .11. +3.39. negative voltage rail Reset Output to Peripherals.3V Power Supply Output to Peripherals. 0V Analogue Power Supply to Peripherals. O – Output.Module2. 40.48.33.D.43.D31 12. IOWR_N during FlyBy DMA Transfers Signal Ground (signal current return path) I – Input. 0V Analogue Power Supply to Peripherals.49. active low D..55 57.16.27. 10 INT1_N.D31. PWR – power © D. or IORD_N. active low Address Bus Address Bus Data Bus INT0_N.D23 and D24. Z – high impedance. use if external bus configured to synchronous operation External Interrupt Inputs. 46.DM642 BUS 1 Connector Signal VCC_OUT GND_OUT AGND AVCC+ AVCCRESOUT_N BUSCLK Pin 1. 64 5 6 Type PWR PWR PWR PWR PWR O O I O O O O I O O O O IOZ Description Power Supply Output to Peripherals. 62 63..32.SignT Digital Signalprocessing Technology Bus Clock. 2 3.23.51... active low. GPIO1 SGND IOZ General Purpose IO. active low Write Strobe. active low Chip Select 1.44.31. internal 1K pull-up Chip Select 0. positive voltage rail Analogue Power Supply to Peripherals..A19 D16.29 30. active low Output Enable.47. BE3_N OE_N RD_N WR_N WAIT_N CS0_N CS1_N A0. 58 8.34 36. 60 61. active low.45.26.53.19. internal 1K pull-up Byte Enable for D16. IO – bidirectional.25. active low. 56 GPIO0. 4 59. 14 13 15 17 18 20 22 21. 9.A5 A16. 24. 52.

28 30.12. 24.17.D15 Pin 63. transmit frame sync input or output.38.DM642 BUS 2 Connector Signal VCC_OUT GND_OUT AGND AVCC+ AVCCGPIO2. 0V Analogue Power Supply to Peripherals. GPIO3 D0. 8 9.42..50. 4 1. positive voltage rail Analogue Power Supply to Peripherals.33. 14. 6 3.A15 O Address Bus BE0_N. 40. 2 7.27. transmit clock input or output.3V Power Supply Output to Peripherals. DATX1 / VP1D4 57 I – Input. receive frame sync input or output.37. 19. mux'ed with video port 0 Sync Serial Port 0. mux'ed with video port 1 Sync Serial Port 1.18. mux'ed with video port 0 Sync Serial Port 0. PWR – power © D.31. mux'ed with video port 1 Sync Serial Port 1.10. mux'ed with video port 0 Sync Serial Port 0. receive clock input or output. active low Signal Ground (signal current return path) DATR0 / VP0D6 46 CLKR0 / VP0D8 47 FSR0 / VP0D7 CLKX0 / VP0D2 FSX0 / VP0D3 48 51 52 DATX0 / VP0D4 49 DATR1 / VP1D6 54 CLKR1 / VP1D8 55 FSR1 / VP1D7 CLKX1 / VP1D2 FSX1 / VP1D3 RESOUT_N SGND 56 58 59 60 13.36. 29.34.39. data receiver. 45.23.20. transmit frame sync input or output.41 43.D7 and D8.SignT 2006 14 . 0V Analogue Power Supply to Peripherals.Module2. active low Sync Serial Port 0. mux'ed with video port 0 Sync Serial Port 0. O – Output. 64 61.22. 44 Type PWR PWR PWR PWR PWR IOZ IOZ Description Power Supply Output to Peripherals.25. Z – high impedance. data transmitter. mux'ed with video port 1 Reset Output to Peripherals..D15.21.D.32. data receiver. mux'ed with video port 1 Sync Serial Port 1. +3.11.16.. receive clock input or output. mux'ed with video port 1 Sync Serial Port 1. mux'ed with video port 0 Sync Serial Port 1.26. BE1_N O I IO IO O IO IO I IO IO O IO IO O Byte Enable for D0. negative voltage rail General Purpose IO Data Bus D. mux'ed with video port 1 Sync Serial Port 1. IO – bidirectional.53.SignT Digital Signalprocessing Technology A6.15. 62 5. 35. mux'ed with video port 0 Sync Serial Port 0. data transmitter. transmit clock input or output.. receive frame sync input or output.

SignT Digital Signalprocessing Technology Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 VP2D0 VP2D2 SGND VP2D5 VP2D6 VP2D8 SGND VP2D11 VP2D12 VP2D14 SGND VP2D17 VP2D18 VP2CTL0 SGND VP2CLK0 VP2CLK1 VP1D1 SGND VP1CTL0 VP1CTL1 VP1CTL2 SGND VP0D1 VP0D5 VP0D10 SGND VP0CTL1 VP0CTL2 VP0CLK1 SGND VCTL © D.SignT 2006 15 .Module2.DM642 BUS 1 Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 BUS 2 Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Signal AVCCAVCC+ AGND GPIO2 D0 D2 SGND D5 D7 D8 SGND D11 D13 D14 SGND A7 A9 A10 SGND A13 A15 BE0_N SGND CLKR0 DATX0 CLKX0 SGND CLKR1 DATX1 FSX1 GND_OUT VCC_OUT Signal AVCCAVCC+ AGND GPIO3 D1 D3 D4 D6 SGND D9 D10 D12 SGND D15 A6 A8 SGND A11 A12 A14 SGND BE1_N DATR0 FSR0 SGND FSX0 DATR1 FSR1 CLKX1 RESOUT_N GND_OUT VCC_OUT Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 Signal VCC_OUT GND_OUT RESOUT_N INT0_N INT1_N SGND OE_N RD_N WR_N SGND A0 A1 A2 SGND A5 A17 A18 SGND D17 D19 D20 SGND D23 D25 D26 SGND D29 D31 GPIO0 AGND AVCC+ AVCCSignal VCC_OUT GND_OUT BUSCLK SGND INT2_N BE2_N BE3_N SGND WAIT_N CS0_N CS1_N SGND A3 A4 A16 SGND A19 D16 D18 SGND D21 D22 D24 SGND D27 D28 D30 SGND GPIO1 AGND AVCC+ AVCCPin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 COM Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Signal GND_IN GND_IN VCC_IN VCC_IN SETUP_N RESIN_N USB_VCC USB_GND SGND CTS_0 RXD_0 SGND RXD_1RXD_1+ ETH_GND ETH_RX+ ETH_RXSGND SCL rsvd SGND PRGIO0 PRGIO1 SGND PRGIO4 PRGIO6 PRGIO7 SGND PRGIO10 PRGIO12 PRGIO13 SGND EXP Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Signal SGND VP2D1 VP2D3 VP2D4 SGND VP2D7 VP2D9 VP2D10 SGND VP2D13 VP2D15 VP2D16 SGND VP2D19 VP2CTL1 VP2CTL2 SGND VP1D0 VP1D5 VP1D9 SGND VP1CLK0 VP1CLK1 VP0D0 SGND VP0D9 VP0D11 VP0CTL0 SGND VP0CLK0 SGND STCTL Signal Signal GND_IN GND_IN VCC_IN VCC_IN IN0_N IN1_N USB_D+ USB_DSGND RTS_0 TXD_0 SGND TXD_1TXD_1+ ETH_GND ETH_TX+ ETH_TXSGND SDA SGND rsvd (CLKIN) SGND PRGIO2 PRGIO3 PRGIO5 SGND PRGIO8 PRGIO9 PRGIO11 SGND PRGIO!4 PRGIO15 D.D.

5 mm © D.76 mm 2.8 mm 83.3 mm 61.5 mm 5.0 mm (8.4 mm Molex 71439-0164 Molex 71439-0164 top side 5.54 mm I/O connector center pins on peripheral boards 2.SignT Digital Signalprocessing Technology max.D. component height 5.4 mm 8.Module2.DM642 MECHANICAL DIMENSIONS D.0 mm 3.54 mm BUS1 BUS2 4*d=2.8 mm 3.SignT 2006 16 .1 mm 4.2 mm EXP 25.5 mm for I/O connector) 4.04 mm 58.5 mm bottom side Molex 71436-2164 Molex 71436-2164 86.3 mm 54.1 mm COM 84.8 mm 29.9 mm 2.4 mm 54.

power supply. sample programs for DSP and PC. Technical Support Our products include free of charge technical support.SignT D.de www http://www. 600 MHz DSP core clock.de) phone or fax. and documentation TCP/IP Evaluation Package including D. Pricing Please ask for our current price list and volume discounts.SignT GmbH & Co. base board.de © D.TCP/IP-DM642 TMDSCCSALL-1 XDS560R XDS510USB_PLUS XDS510USB XDS510pp_plus standard module D.­ For special modifications or non-standard D. KG Marktstr. Distributed and supported locally by D. 100 MHz Bus and SDRAM clock OEM quantities (25++) only Development Support Package including support software.Module2 boards come with a 12 month warranty . 10 D-47647 Kerken phone +49 (0) 2833 / 570 977 fax 49 (0) 2833 / 33 28 email info@dsignt.SignT offers customer specific modifications of the hardware either to reduce costs through reduced functionality or to increase functionality to meet the customers application requirements. Availability Our standard D.D. documentation.0 JTAG in-circuit emulator Spectrum Digital high-speed USB2.Modules are available typically ex-stock. Warranty All D.DM642 ORDERING INFORMATION D. You can reach the technical support by e-mail (support@dsignt.0 JTAG in-circuit emulator Spectrum Digital USB JTAG in-circuit emulator Spectrum Digital parallel port JTAG in-circuit emulator Additional Options On Volume Purchase For volume purchase D. Extensive experience in custom designs and the powerful engineering tools of our development department bring your application and our DSP know how together for your solution.SignT TCP/IP protocol library.dsignt.DM642 Options: DS. max. cables. For additional information contact your local distributor or D.Module2 please consult our sales department. Please contact D. and evaluation license Texas Instruments Code Composer Studio code generation and debug tools Spectrum Digital high-speed USB2.DM642 DS.Module2.SignT Digital Signalprocessing Technology -I : industrial grade. max.SignT directly.SignT 2006 17 .Module2.SignT directly.