KTH/ESDlab/LiRong Zheng
IL2201 Digital Integrated Circuit Design  VLSI
Signaling Conventions
Home reading: 7.17.3
2/3/2012 2
KTH/ESDlab/LiRong Zheng
Navigation
Lecture 1. Course Overview & Introduction (Ch.1 & Ch.4)
Lecture 2: Wires as Interconnects in VLSI ( B1 Ch4 & 9)
Lecture 3. Interconnect Design – transmission lines (Ch.3)
Lecture 4. Noise in Digital Systems (Ch.6, B1 Ch.9)
Lecture 5. Noise (continue) (Ch.6)
Lecture 6. Signaling Conventions (Ch.7)
Lecture 7. Signaling Techniques (Ch.8 & 11)
Lecture 8. Power Distribution Design (Ch.5)
Lecture 9: Timing Conventions (Ch.9 & B1 Ch.10)
Lecture 10: Clock Distribution Design (Ch.9 & B1 Ch.10)
Lecture 11: Synchronization (Ch.10 B1 Ch.10 )
Lecture 12: Synchronizer Design (Ch.10)
Lecture 13: Signaling and Timing Circuits (Ch.11 & 12)
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Outline
Signaling basics: transmission line view
Signaling over capacitive loads
Signaling over lossy RC and LC lines
– lumped interconnect model
Bidirectional signaling
Signaling circuits
– termination
– voltage and current mode drivers
– risetime control
– receiver circuits
Low voltage onchip CMOS signaling circuits
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Signaling —The Main Idea
Signaling method defines how digital information is presented in
electrical form and how this information is transmitted from one
location to another in the system
A good signaling system isolates the signal from noise rather than trying
to overpower the noise
– cross talk : terminate both ends
– ISI : matched terminations, no resonant sections, risetime control
– power supply noise : currentmode signaling, stable reference, differential
signaling
– reference noise : bipolar signaling, differential signaling
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An Example Signaling System
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Signaling basics
Transmission line model
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Overview
Introduction to Signaling
transmission method
– current vs. voltage
– bipolar vs. unipolar
termination scheme
– parallel, source, both, underterminated
references
– 0 reference, transmitter reference,
receiver reference
source termination
– use reflection to double signal
amplitude
differential signaling
– 1.31.8x as many pins but many nice
properties
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Basic signaling system
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Transmission Mode (Output Impedence)
Output impedance of the transmitter determines whether we have a voltagemode
or currentmode transmission
– small output impedance (<<Z
0
) =>voltage source
» large voltage swing
– large output impedance (>>Z
0
) =>current source
» small voltage swing
Z
0
Z
0
0 0
0
0
Z R
V
Z
V
I
V
Z R
Z
V
O
T S
T
T
O
S
+
= =
+
=
V
S
I
T
V
S
0
Z I V
T S
=
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Signaling design parameters
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Voltage Mode vs. Current Mode
In reality a continuum, because R
O
can vary from 0 to ·
Both inject the “same” signal into the line: V
S
= I
T
Z
0
– However,in voltagemode signaling I
T
and V
S
are much larger than in
currentmode signaling
– This means that the current mode consumes less power than the voltage
mode
A small current with a large transmitter output impedance is much
easier to generate than a small voltage with a small transmitter output
impedance
A currentmode transmitter has typically a very large impedance Z
GT
to
the local power supply (ground)
– provides good isolation of the line voltage from the noisy power supply
Due to small return currents, a currentmode system is more immune to
the return cross talk than a voltagemode system
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Output Resistance and Signal Return Cross Talk (1)
Assume that we have N transmitters
which have a shared return path
impedance Z
R
Assume that only the voltage source
V
a
is active and the other N–1
sources are replaced with shorts
Then the transmitted current I
a
=V
Ta
/
Z
0
sees the shared return impedance
Z
R
in parallel with the parallel
composition of the impedances
R
O
+Z
0
from the other signals. Hence
the total return impedance Z
X
is
0
0
0
) 1 (
) (
1
Z R Z N
Z R Z
N
Z R
Z Z
O R
O R
O
R X
+ + ÷
+
=

.

\

÷
+
=
I
a
–
+
V
Ta Z
0
Z
0
R
O
R
O
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Output Resistance and Signal Return Cross Talk (2)
The multiple return paths form a
current divider. The current I
X
flowing
through each of the N –1 line
impedances Z
0
is then given by
(
¸
(
¸
+ + ÷
=


.

\

+
=
+
=
0
0 0
) 1 ( Z R Z N
Z
I
Z R
Z
I
Z R
Z I
I
O R
R
a
O
X
a
o
x a
X
I
a
I
X
I
X
+
+
–
–
V
X
V
X
(
¸
(
¸
+ + ÷
=
(
¸
(
¸
+ + ÷
=
=
0
0
0
0
) 1 ( ) 1 ( Z R Z N
Z
V Z
Z R Z N
Z
I
Z I V
O R
R
Ta
O R
R
a
X X
–
+
V
Ta
This current induces a return cross talk
voltage V
X
across each of the N–1 line
impedances Z
0
:
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Output Resistance and Signal Return Cross Talk (3)
In the worst case, N –1 signals switch
simultaneously. Then the total return
cross talk voltage experienced by the
single unswitched line is (N –1)V
X
The transmitter signal return cross talk
ratio k
xrT
is the total return cross talk
voltage divided by the transmitted
voltage V
Ta
:
Hence, in an ideal voltagemode system, with R
O
= 0, the return cross talk has a
maximum value, while in an ideal currentmode system, with R
O
= ·, the return
cross talk is completely eliminated !
However, to eliminate reflections, it is usually better to have a matched source
termination R
O
=Z
0
also for a currentmode system !!
0
0
0
) 1 ( because ,
) 1 (
) 1 (
) 1 ( ) 1 (
Z R Z N
Z R
Z N
Z R Z N
Z N
V
V N
k
O R
O
R
O R
R
Ta
X
xrT
+ << ÷
+
÷
~
+ + ÷
÷
=
÷
=
I
a
I
b
=I
a
2I
X
+
+
–
–
V
Tb
=V
Ta
2V
X
–
+
V
Ta
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Transmitter (Driver) Design Principles (1)
Voltagemode transmitter
– transmitted swing V
S
should be > 0.9·AV
=> R
O
s 0.1·Z
0
– to obtain a low output resistance, the driver must be
built from very large transistors (NMOS, PMOS)
» for example, to obtain R
O
=5 O (Z
0
=50 O) using
a 0.35 µm technology, we need an NMOS with
W/L =320 and a PMOS with W/L =800 !!
– these large transistors must be driven with multistage
buffers (e.g. “exponential horns”)
– R
O
can be doubled, i.e., the transistor size can be
halved, if the termination voltage V
T
is not set to V
0
,
but is selected to be in the middle of the logic swing
AV
– selecting V
T
=AV/2 gives also the minimum driver
current for a given signal swing and line impedance
V
1
V
0
Z
0 R
O
R
T
V
T
Driver
AV = V
1
–V
0
(logic swing)
V
S
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Transmitter (Driver) Design Principles (2)
Currentmode transmitter
– transmitted voltage swing V
S
is usually s 0.1·AV and
transmitted current I
S
s 0.1·AV / Z
0
=> R
O
> 10·Z
0
– the size of driver transistors (NMOS,PMOS) is about
510% of the size in a voltagemode driver
– transistors are biased to operate in the saturation
region in order to have a constant current flow through
them
– current mirrors are used to adjust the current
– termination voltage V
T
is usually either V
1
, V
0
,or the
midrail voltage AV/ 2 which is used especially in
bipolar drivers to ensure symmetric operation in push
(PMOS sends a logic 1) and pull (NMOS sends a logic
0) events.
V
0
Z
0 R
O R
T
V
T
Unipolar Driver
V
S
I
S
V
1
V
0
Z
0 R
O R
T
V
T
Bipolar Driver
AV = V
1
–V
0
(logic swing)
V
S
I
S
logic 1
logic 0
logic 0
logic 1 “no current” :
x
kx
bias
switch
line
I
ref
kI
ref
Simple unipolar
current mirror driver
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Unipolar vs. Bipolar Signaling
Unipolar signaling
– logic 0 is 0 mA (V) ±offset
– logic 1 is 2x mA (V) ±offset
– reference level (detection threshold)
is x mA (V)
Bipolar signaling
– logic 0 is x mA (V) ±offset
– logic 1 is x mA (V) ±offset
– reference level (detection threshold)
is 0 mA (V)
– gives balanced transmitter offsets
for 0 and 1
Bipolar signaling draws half the
peak current drawn by unipolar
signaling with the same signal
swing !
Input
Output
Input
Output
Input Output
Receiver Transmitter
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A Typical Bipolar CurrentMode Driver
Drives the differential outputs out+
and out
– logic 1 (in+ high, in low)
» inverter Inv1 sinks current from
out =>I
out
=2.5 mA
» inverter Inv2 sources current
into out+ =>I
out+
=2.5 mA
– logic 0 (in+ low, in high)
» inverter Inv1 sources current
into out =>I
out
=2.5 mA
» inverter Inv2 sinks current from
out+ =>I
out+
=2.5 mA
Current flow is controlled by the bias
voltages pbias and nbias
Can be used for singleended
signaling by connecting out to the
return path
Inv1
Inv2
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Receiver References
Receiver detects the arrived symbol
by comparing the received voltage
or current to a reference
Reference errors (offsets) do not
depend on the signal swing, and
hence they are considered a part of
independent noise
References can be generated in
several ways
– derive from the receiver power
supplies
– derive from the return path voltage,
i.e., the voltage across the
termination resistor, if the receiver
side is terminated
– generate in the transmitter and send
to the receiver
V
ref
Receiver
Receiver
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Source Termination without Receiver Termination
amplitude and length t
B
, but the nearend voltage V
S
and the midpoint voltage V
M
both
execute two halfamplitude pulses of the length t
B
and never reach the full swing.
Injected voltage V
S
, if R
T
=Z
0
:
– voltage mode : V
S
=V
T
/ 2
– current mode : V
S
=I
T
Z
0
/ 2
Immediately after one line delay t
L
the
received voltage V
R
reaches the full
amplitude due to the full reflection at the
open end
– voltage mode : V
R
=V
T
– current mode : V
R
=I
T
Z
0
If V
T
or I
T
is a single step, the midpoint
voltage V
M
gets the full amplitude half
line delay later, the nearend voltage V
S
one line delay later
If the line delay t
L
is longer than the bit
duration (“bit cell”) t
B
, the receiver sees
a clean pulse with the full
Voltage mode : Series termination
R
T
Z
0
, t
L
R
T
Z
0
, t
L
V
T
V
S
V
S
I
T
V
R
V
R
Current mode : Parallel termination
V
M
V
M
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Source Termination Advantages and Disadvantages
Advantages compared to receiver
termination
– Power consumption
» energy per bit is halved in the
voltage mode
» no reduction in the current
mode, because the total current
need does not actually change
!
– Cross talk
» rejects nearend cross talk
Disadvantages compared to receiver
termination
– Proper waveform is observed only
at the receiver => can be used in
pointtopoint signaling only —not
in multidrop buses
– More sensitive to intersymbol
interference because of the
reflection at the receiver
Voltage mode : Series termination
R
T
Z
0
, t
L
V
T
V
S
V
R
R
T
Z
0
, t
L
V
S
I
T
V
R
Current mode : Parallel termination
V
M
V
M
Bottom line is that there is only a little
difference between terminating just at the
source and just at the receiver
=>it is better to terminate both ends of the
line !
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A Typical VoltageMode Source Terminated Driver
Looks like a usual voltagemode driver, but
now the size of the transistors is smaller, so
that the output resistance is ~ Z
0
instead of
s 0.1·Z
0
Because of process variations, it is very
hard to adjust the resistance of a single
transistor accurately to Z
0
=>
compensation is needed
– Digital trimming
» transistor sizes for each control bit
bit 0 : 1 (unit size)
bit 1 : 2
bit 2 : 4
bit N – 1 : 2
N – 1
» hence, 2
N
– 1 different resistance values
can be selected with N bits : 1, 1/2,
1/3, 1/4, … , 1/(2
N
– 1 )
This kind of driver is also called selfseries
terminating driver
Digitally Trimmed (Segmented) Driver
Z
0
in
Z
0
Z
0
in
b
0
b
2
b
1
selection bits
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Underterminated Drivers
Underterminated drivers are voltage
mode transmitters with
– high output resistance R
O
» typically R
O
=6 – 10 ·Z
0
» example : R
O
=400 O =>
R
O
/Z
0
=8, if Z
0
=50 O
– high voltage swing
» typically around 2.5 V
If such a transmitter tries to drive a
line with R
T
=· (open end, i.e., no
receiver or parallel termination) to
full swing, it must ring up the line
through multiple reflections at both
ends
– large delay (several line delays)
Z
0
R
T
an interesting combination of voltage and
current mode signaling:
– received voltage V
R
equals injected voltage
V
S
:
V
R
=V
S
=[Z
0
/(Z
0
+R
O
)] (AV – V
T
)
– terminating the receiver to the midrail
voltage V
T
=AV /2 gives the symmetrical
response with the current
I =V
S
/ Z
0
=AV / [ 2(Z
0
+R
O
) ]
V
1
V
0
AV = V
1
–V
0
(logic swing)
However, if we terminate the receiver side to
the termination voltage V
T
with the matched
resistance R
T
=Z
0
, we get
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–
+
Differential Signaling
A differential signal is sent as a
difference in voltage or current
between two distinct lines. For
example:
– to send a 1, the upper voltage source
drives V
1
on the line A , and the lower
voltage source drives V
0
on the line B
– to send a 0, the upper voltage source
drives V
0
on the line A , and the lower
voltage source drives V
1
on the line B
Differential signaling requires more
wires and pins than singleended
signaling
– differential signaling can have a
separate return for each signal
» reduces the number of ground
pins needed for an interface
Line A
Line B
– singleended signaling has usually 1
shared return for 2 – 8 signals
– typically differential signaling requires
1.3 – 1.8 times as many pins as
singleended signaling
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Properties of Differential Signaling
Signal serves as its own reference
– compare a signal to its complement to
detect
Twice the signal swing
– if the voltages applied to the lines are V
1
and V
0
(high and low voltages), then
the effective swing is
AV =2(V
1
–V
0
)
Noise immunity
– because of the double swing, also the
noise margin is doubled !
– many noise sources become common
mode and are filtered out by the
differential receiver
– very little selfinduced power supply
noise (practically no AC current)
Return current
– has a constant DC value, because V
1
is
always across one termination resistor
and V
0
across the other
I
R
=(V
1
+V
0
) / R
T
– return current is 0 for bipolar signaling,
because V
1
=V
0
–
+
Unipolar voltage mode
Bipolar current mode
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Differential Signaling through Balanced (Symmetric) Lines
A bipolar differential signal, voltage
or current mode, has zero net return
current
This enables us to replace the two
separate transmission lines carrying
the complementary signals with a
single balanced or symmetric
transmission line which consists of
two equivalent closely packaged
wires with equal inductances
– reduces cross talk with other signals
– because of the symmetry, the two
wires have equivalent delays. This
eliminates noise caused by a delay
mismatch between the lines
Balanced
(symmetric)
transmission
line (e.g. a
twisted pair
cable)
Z
0
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IL2201 Digital Integrated Circuit Design  VLSI
Signaling Techniques
Home reading: 7.4 7.5 & 8.18.3, 11.111.3
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Navigation
Lecture 1. Course Overview & Introduction (Ch.1 & Ch.4)
Lecture 2: Wires as Interconnects in VLSI ( B1 Ch4 & 9)
Lecture 3. Interconnect Design – transmission lines (Ch.3)
Lecture 4. Noise in Digital Systems (Ch.6, B1 Ch.9)
Lecture 5. Noise (continue) (Ch.6)
Lecture 6. Signaling Conventions (Ch.7)
Lecture 7. Signaling Techniques (Ch.8 & 11)
Lecture 8. Power Distribution Design (Ch.5)
Lecture 9: Timing Conventions (Ch.9 & B1 Ch.10)
Lecture 10: Clock Distribution Design (Ch.9 & B1 Ch.10)
Lecture 11: Synchronization (Ch.10 B1 Ch.10 )
Lecture 12: Synchronizer Design (Ch.10)
Lecture 13: Signaling and Timing Circuits (Ch.11 & 12)
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Overview:
Signaling over Lumped Media, Signaling over Lossy RC and LRC Lines,
Simultaneous Bidirectional Signaling, Signal Encoding
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Capacitive Wires
Capacitive wires —what are they?
– short (around 1mmor shorter) onchip wires with
» large capacitive load, i.e., high fanout or fanin
» negligible inductance and resistance compared to capacitance
» short propagation delay compared to signal rise and fall times
– for example:
» short local buses
» wiring of register files
» wiring of RAM
– Note that long onchip wires are more problematic RC lines !
Goals in signaling over capacitive media
– fast transitions
– low power
– these require a small voltage swing !
– a small signal swing requires isolation of power supply noise !
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Logic Signaling and Transmission Signaling
Signal levels in logic circuits are
wellsuited only for driving short
lines, where the driven capacitive
loads are small, and the logic delays
dominate over line delays
If we try to drive a longer heavily
loaded line with a logic gate, the
transmission
– becomes very slow
– dissipates lots of power
– is sensitive to power supply noise
When the transmission delay becomes
dominant over the logic delay, it is
better to switch from a pure logic
circuit model to a representation,
where the gates, which perform logic,
are separated from the driver and
receiver which transfer bits over the
wire
Short wire with a small capacitive load,
Logic signaling
Transmitter
Long wire, or a wire with a large capacitive load,
Transmission signaling
Receiver
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VoltageMode Capacitive Signaling System
Time constant t determines the
delay of the transmission system,
together with the transmitter and
receiver delay
Ground noise
between the
driver and the
lumped wire
capacitance
Additional noise
between the
signal ground
and the receiver
ground
R
O
V
R
+
÷
V
T
V
0
V
1
C R
C R
t
V V V t V
O
O
R
=


.

\

÷ ÷ + = t , exp ) ( ) (
1 0 1
Response of the line without noise
sources:
affects
the line
voltage
affects the
reference
voltage
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CurrentMode Capacitive Signaling System
Driver (transmitter) sends a small
current I
T
, and the receiver detects
this current as a voltage V
R
across the
resistor R
T
between the signal line and
the receiver ground
Because of the high output resistance
R
O
of the driver, the driver ground
noise V
N1
and the DC part of the
receiver ground noise V
N2
are
attenuated by
R
T
/ (R
T
+R
O
)
Hence, if R
O
is very large, V
N1
and the
DC part of V
N2
are practically
eliminated
V
N1
V
N2
I
T
R
O
C R
T
V
R
V
r
The AC part of V
N2
is highpass filtered by
C and R
T
giving the AC attenuation
R
T
jeC / (R
T
jeC +1)
The frequency components of V
N2
that are
below the cutoff frequency
f
c
= 1/ (R
T
C)
are attenuated, while the higher frequencies
are passed largely unattenuated
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ReducedSwing VoltageMode Signaling
A resistor R
T
is placed in parallel with
the line capacitance at the receiver,
just like in the currentmode system.
This reduces the signal swing V
R
from
V
T
to
V
R
=V
T
R
T
/ (R
T
+R
O
)
As the line capacitance C sees the
resistors R
O
and R
T
in parallel, the
time constant t is reduced to
t =R
T
R
O
C / (R
T
+R
O
)
This
– speeds up the system
– reduces noise, because the cutoff
frequency f
c
of the highpass filter
which attenuates the receiver ground
noise V
N2
is increased from 0 to 1/ (R
T
C)
Driver ground noise V
N1
is attenuated
by the same factor as the signal : R
T
/
(R
T
+R
O
)
V
N1
V
N2
V
T
R
O
C R
T
V
R
V
r
Example
– Fullswing 3.3 V driver with R
O
=200 O
and C =20 pF without R
T
gives the time
constant t =4 ns.
– Adding R
T
=20 O reduces the swing to 300
mV and the time constant t to 360 ps
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Pulsed Signaling (1)
The above signaling systems dissipate
static power. This is a disadvantage,
if the transmission frequency on the
line is low.
To remove the static current flow, one
can use a pulsed signaling system
which is similar to the currentmode
signaling system except that
– there is no resistor R
T
at the receiver
– the line is driven by short current
pulses
For each 0to1 transition, the driver
generates a positive current pulse with
the magnitude I
p
and width t
r
causing
the line voltage to change by
AV
R
= I
p
t
r
/ C
Similar negative pulse ( I
p
, t
r
) is generated
for each 1to0 transition, causing a voltage
change AV
R
Driver is off, i.e., the line voltage remains
constant, when the bit being transmitted is
the same as the previous bit
Consumes less power, but noise rejection is
not as good
– receiver ground noise V
N2
appears
unattenuated at the receiver reference V
r
V
N1
V
N2
I
T
R
O
C
V
R
V
r
I
T
V
R
1 1 0 1 0
2/3/2012 36
KTH/ESDlab/LiRong Zheng
Pulsed Signaling (2)
To make a pulsed signaling system
immune to the receiver ground noise
V
N2
, one should not derive the
receiver reference voltage V
r
from the
receiver ground
Solutions:
– transmittergenerated receiver
reference
– differential signaling
0÷1
1÷0
control
voltages
for refe
rence ge
neration
AV
R
0
AV
R
/ 2
0÷1
1÷0
AV
R
0
AV
R
0
0÷1
0÷1
1÷0
1÷0
Basic pulsed signaling
Reference generated
by the transmitter
Differential signaling
2/3/2012 37
KTH/ESDlab/LiRong Zheng
Signaling over Lumped LRC Interconnect
Short offchip wires often look like
LRC resonant circuits (long ones look
like transmission lines!)
– output impedance (resistance) of a
voltagemode driver
– inductance of a package pin and bond
wire
– capacitance of a load device driven
through a package pin
Transmission of a bit can cause such a
wire section to oscillate. This may
lead to the intersymbol interference
and corruption of later bit cells
Increase the series resistance R
O
to
dampen the oscillations
Increase the rise time t
r
of the signal
to pump less energy into the resonant
circuit
Driver
Package pin
& bond wire
Load
V
T
V
R
+
÷ ÷
+
LC
f
t 2
1
0
=
C
L
R
Q
O
t
1
=
r
r
t
t
K
t 2
0
=
Resonant frequency
Number of cycles before the
amplitude of the oscillation
is attenuated to 1/e
Risetime dependent attenu
ation factor (t
0
= undamped
period = 1/ f
0
)
You can also use parallel termination at the
receiver to reduce signal swing and strengthen
the dampening effect
2/3/2012 38
KTH/ESDlab/LiRong Zheng
Response of an LRC Circuit
L = 10 nH, C = 10 pF
R = 0 .. 16 O
L = 10 nH, C = 10 pF, R = 4 O
t
r
= 0 .. 3 ns
C
L
R
Q
O
t
1
=
(
¸
(
¸


.

\

÷ ÷ = =
d
r
r
r
r tot
t
t
at
t
t
K K K
t
t

2
cos ) exp( 1
2
0
2/3/2012 39
KTH/ESDlab/LiRong Zheng
Delay:
Rise/fall time:
0.0 mm
2.5 mm
5.0 mm
7.5 mm
10.0 mm
Signaling over OnChip RC Lines
Long (around 2 mm or more) onchip
wires are lossy RC lines with
– significant resistance R and
capacitance C
Example: a 0.5 µm wide and
thick aluminium wire:
» R =120 O/mm
» C =160 fF/mm
» t =19 ps/mm
2
– still negligible inductanceL
Line delay t
d
and the signal rise time
t
r
depend quadratically on the
distance d
Large drivers do not help, because the
resistance of wires dominates
This problem gets worse as
technology evolves.
d
2/3/2012 40
KTH/ESDlab/LiRong Zheng
Repeaters
Repeaters (buffers) are needed to
convert the quadratic delay of an RC
line to a linear delay
Repeaters are spaced optimally, when
the repeater delay t
b
equals the delay
of the driven wire segment
– about 3 mm for an 0.35 µm
technology
– about 1 mm for an 0.18 µm
technology
Results in a minimum line delay t
d,min
, a maximum signal propagation
velocity v
max
, and an optimal rise
time t
r,opt
l
l
s
l
s
l
s
t
b
t
b
t
b
( ) RC l t
l
l
t
s b
s
d
2
4 . 0 +


.

\

=
2
1
,
4 . 0

.

\

=
RC
t
l
b
opt s
RC t
v
b
max
8 . 0
= ¬
Buffered line delay
RC t l t
b min d
3 . 1
,
= ¬
b opt s opt r
t RC l t 5 . 2
2
, ,
= =
Optimal buffer spacing
Minimum line delay
Maximum signal velocity
Optimal signal rise time
2/3/2012 41
KTH/ESDlab/LiRong Zheng
Effect of Wire Width on RC Lines
Making wires wider than the minimum width
– decreases the resistance linearly
– increases the capacitance a bit more slowly, because only the parallel plate capacitance
increases while the fringing capacitance remains the same
Hence, a wider wire has a smaller time constant RC
– line delay is decreased
– signal rise time is decreased
– can double the speed of the line in the best case
However, a larger capacitance means a higher power consumption
– for example, doubling the wire width can reduce the delay by 25%, but at the same time the
power consumption increases by 50% !
– not a very good tradeoff =>it is better to use narrow wires and repeaters
2/3/2012 42
KTH/ESDlab/LiRong Zheng
1 2
1
) 0 (
+
·
x
V
R
i
o
  x V
D R i
) ( exp ) 0 ( o o + ÷ ·
) (x V
i
Signaling over OffChip LRC Lines
Long (around 10 cm or more) off
chip wires are lossy LRC lines
– fast rise to AC attenuation
– long tail to DC attenuation
Frequencydependent attenuation
– skin effect
» resistance increases as the square
root of signal frequency
– dielectric loss (if the condutance G is
significant)
Wave (AC) Attenuation
Transmitted waveform
Received waveform
2/3/2012 43
KTH/ESDlab/LiRong Zheng
Attenuation Closes the Eye Opening
Frequencydependent attenuation
reduces the eye opening of the high
frequency components (short pulses)
– the eye is completely closed, when
the attenuated signal sizeA is 0.5 (or
less) of the full amplitude
This results in intersymbol
interference
– the highfrequency components are
“overrun” by the lowfrequency
components
Causes also datadependent jitter
– there is a phase difference between
the edges of short and long pulses
1
A
1–2A
2/3/2012 44
KTH/ESDlab/LiRong Zheng
Equalization of LRC Lines (1)
Frequencydependent attenuation can
be cancelled or compensated by
equalization
This is achieved by placing a digital
equalizing filter (FIR) either in the
transmitter or in the receiver
– transfer function G(s) of the equalizer
must approximate the inverse of the
transfer function H(s) which models
the line, i.e., the combined transfer
function G(s)H(s) must approximate
unity
The idea is to emphasize the high
frequency components that are
attenuated by the line
Transmitter
G(s) H(s)
Equalizer Line
H(s)
G(s)
G(s)H(s)
2/3/2012 45
KTH/ESDlab/LiRong Zheng
Equalization of LRC Lines (2)
Short pulses are barely detectable
Problem solved !
2/3/2012 46
KTH/ESDlab/LiRong Zheng
Simultaneous Bidirectional Signaling (1)
Wire density and pin count of a system can be effectively doubled, if we send bits
simultaneously in both directions on a wire
Waveform on the wire is a superposition of the forward and reverse traveling wave
Received wave is recovered at each end by subtracting the transmitted wave from the
combined waveform
V
T
R
T
/ 2 R
T
/ 2
R
T
R
T
i
f
i
r 1 V
f 1
V
r 1
V
LA
V
LB
i
f 1
i
r
D
TA
D
RA
D
TB
D
RB
Transceiver A Tranceiver B
Z
0
2 2 2
1
0
0
1
T f
r
f
f LA RA
R i
Z i
Z i
V V D ÷ + = ÷ =
2 2 2
1
0
0
1
T r
f
r
r LB RB
R i
Z i
Z i
V V D ÷ + = ÷ =
2/3/2012 47
KTH/ESDlab/LiRong Zheng
Simultaneous Bidirectional Signaling (2)
V
T
R
T
/ 2 R
T
/ 2
R
T
R
T
i
f
i
r 1 V
f 1
V
r 1
V
LA
V
LB
i
f 1
i
r
D
TA
D
RA
D
TB
D
RB
Transceiver A Transceiver B
Z
0
D
TA
D
TA,B
D
TB
D
TB,A
V
LA
V
LB
D
TA
at B
D
TB
at A
2/3/2012 48
KTH/ESDlab/LiRong Zheng
Signal Encoding
We tend to use the 2level or binary signal
encoding because of it simplicity
– one nominal voltage level refers to the
logic symbol ‘1’, the other to the logic
symbol ‘0’
– one threshold voltage, for example V
DD
/2
However, we could as well use N levels
– N symbols
– N nominal symbol voltages
– N –1 threshold voltages
– nominal voltage separated from a
threshold by AV/ [2(N –1)]
– number of bits per symbol is log
2
(N)
» for example, with a 4level signal we
can present the binary numbers 00,
01, 10, and 11 on a single wire
2/3/2012 49
KTH/ESDlab/LiRong Zheng
MultiLevel Signals and Noise
In the worst case, signal can swing
through AV, from the symbol 0 to the
symbol N –1, or vice versa
– proportional noise is proportional to
the full swing AV, not to the voltage
difference between two distinct
symbols
Gross noise margin V
GM
is the
distance from a nominal voltage to
the closest threshold
Proportional noise factor K
N
must be
kept very small to enable the use of
several signal levels
) 1 ( 2
1
) 1 ( 2
÷
s
¬
÷
A
=
N
K
N
V
V
N
GM
2/3/2012 50
KTH/ESDlab/LiRong Zheng
MultiLevel Signals and Power Consumption
When to use multilevel signaling?
– when the channel is bandlimited, multilevel
signaling may be the only way to increase bit
rate
– when the SNR is exceptionally large, so that
proportional noise does not destroy the
multilevel signal
In the worst case, power per symbol
is proportional to AV
2
The swing AV must be chosen in
such a way that the independent noise
V
NI
does not exceed the gross margin
of symbols. This means that
AV >2V
NI
(N –1)
Hence, power per symbol is
proportional to N
2
So, because each symbol corresponds
to log
2
(N) bits, power per bit is
proportional to
N
2
/ log
2
(N)
Binary signaling with two symbols 1
and 0 results in the minimal power
consumption per bit !
2/3/2012 51
KTH/ESDlab/LiRong Zheng
Signaling Circuits Design
Ch.11.13
2/3/2012 52
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Onchip vs. offchip termination
2/3/2012 53
KTH/ESDlab/LiRong Zheng
FET termination
2/3/2012 54
KTH/ESDlab/LiRong Zheng
Automatic terminator adjustment with servo loop
2/3/2012 55
KTH/ESDlab/LiRong Zheng
Selfseries termination control
2/3/2012 56
KTH/ESDlab/LiRong Zheng
Voltage mode drivers
2/3/2012 57
KTH/ESDlab/LiRong Zheng
Tristate buffers
2/3/2012 58
KTH/ESDlab/LiRong Zheng
Currentmode drivers
2/3/2012 59
KTH/ESDlab/LiRong Zheng
Differential current steering driver (unipolar)
2/3/2012 60
KTH/ESDlab/LiRong Zheng
Bipolar current mode drivers
2/3/2012 61
KTH/ESDlab/LiRong Zheng
Risetime control
2/3/2012 62
KTH/ESDlab/LiRong Zheng
Multiplexing transmitter
2/3/2012 63
KTH/ESDlab/LiRong Zheng
Multiplexing transmitter
2/3/2012 64
KTH/ESDlab/LiRong Zheng
Receiver circuits
2/3/2012 65
KTH/ESDlab/LiRong Zheng
Receiver structures: inverter
2/3/2012 66
KTH/ESDlab/LiRong Zheng
Selfbiased sourcecoupled FET amplifiers
2/3/2012 67
KTH/ESDlab/LiRong Zheng
Selfbiased sourcecoupled FET amplifiers
2/3/2012 68
KTH/ESDlab/LiRong Zheng
Clocked differential amplifier
2/3/2012 69
KTH/ESDlab/LiRong Zheng
Amplifier with tailored impulse response
2/3/2012 70
KTH/ESDlab/LiRong Zheng
Demultiplexing receivers
2/3/2012 71
KTH/ESDlab/LiRong Zheng
Next Lecture:
Power distribution, home reading Ch.5