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February 2013 (Spring drive) Bachelor of Computer Application (BCA) – Semester 3 BC0046 – Microprocessor

(Book ID: B0807)

– 4 Credits

(60 Marks)

Answer all questions.

[10 x 6 = 60]

1. Write an assembly language program to find the highest among two numbers.

2. Program 3. MVI D, 8BH 4. MVI C, 6FH 5. MOV A, C 6. ADD D 7. OUT PORT1 8. HLT
2. Draw and explain the internal architecture of 8085 briefly.

Figure 3.1 shows the internal architecture of the 8085. Except for the instruction register, which is actually a 6-byte queue, the control unit and working registers are divided into three groups according to their functions. There is a data group, which is essentially the set of arithmetic registers; the pointer group, which includes base and index registers, but also contains the program counter and stack pointer; and the segment group, which is a set of special purpose base registers. All of the registers are 16 bits wide. The data group consists of the AX, BX, CX and DX registers. These registers can be used to store both operands and results and each of them can be accessed as a whole, or the upper and lower bytes can be accessed separately. For example, either the 2 bytes in BX can be used together, or the upper byte BH or the lower byte BL can be used by itself by specifying BH or BL, respectively.

DX is used to hold the I/O address during certain I/O operations. then the next instruction will be fetched from 0002 Effective address + 12340 beginning segment address . IP.Fig 3. SI. CX and DX registers play special addressing. is determined by the EA and the appropriate data segment (DS). the address put on the address bus. however. BP. or stack segment (SS) register. CX is used as an implied counter by certain instructions. the BX. The word “displacement” is used to indicate a quantity that is added to the contents ‘of a register(s) to form an EA. Although they may be used by themselves. As an example. but must be accessed as a whole. BP. The final data address. SS. SP. SI. thus a 20-bit result is produced. but the complete instruction and stack addresses are formed by adding the contents of these registers to the contents of the code segment (CS) and stack segment (SS) registers. The result of such an address computation is called an effective address (EA) or offset. therefore. a pointer can be used to hold an operand. an effective address has only 16 bits. The segment group consists of the CS. As indicated above. and DI registers. The addition is carried out by appending four 0 bits to the right of the number in the segment register before the addition is made. the BX.1: Internal Architecture of 8086 In addition to serving as arithmetic registers. and ES registers. and I/O roles: BX may be used as a base register in address calculations. DS. BP is a base register for accessing the stack and may be used with other registers and/or a displacement that is part of the instruction. SI or DI register contents. extra segment (ES). The pointer and index group consists of the IP. must contain 20 bits. On the other hand. counting. a data address may be formed by adding together a combination of the BX or BP register contents. called the physical address. the registers that can be used for addressing. and a displacement. SP. The extra 4 bits are obtained by adding the effective address to the contents of one of the segment registers as shown in Fig. To provide flexible base addressing and indexing. The SI and DI registers are for indexing. and DI registers. Except for the IP. The instruction pointer IP and SP registers are essentially the program counter and stack pointer registers. if (CS) = 1234 and (IP) = 0002. 3. are only 16 bits wide and.2. they are often used with the BX or BP registers and/or a displacement.

3." e. all addresses are given in hexadecimal. some of which may be grouped into libraries. normally the linker prints a memory map that indicates where the linked object modules will be loaded into memory. Also. i. All that appears in the user’s program are references to the I/O drivers that cause the operating system to execute them. The arrows indicate that corrections may be made after anyone of the major stages. beginning at an address that is divisible by 16. (IP) means the contents of IP. Linking and Relocation In constructing a program some program modules may be put in the same source module and assembled together.e. An illustration of the example above is given in Fig. 3. If they are assembled separately. must be terminated by an END statement with the entry point specified.12342 Physical address of instruction [It is standard notation for parentheses around an entity to mean "contents of. or paragraph. must be linked together to form a load module before the program can be executed. the beginning segment address. then the main module. In any event.3( a) and the overall segmentation of memory is shown in Fig. boundary.g. and each of the other modules must be terminated by an END statement with no operand. 3. with each segment being 64K bytes long and beginning at a 16-byte. Explain the concept of Linking and Relocation. normally the I/O is done by I/O drivers that are part of the operating system. and the segment address multiplied by 16 as the beginning physical segment address. the resulting object modules. which has the first instruction to be executed. We will hereafter refer to the contents of a segment register as the segment address.3. but the general concepts are the same. The general process for creating and executing a program is illustrated in Fig 5.] Fig. In addition to outputting the load module. others may be in different source modules and assembled separately. or simply. After the load module has been created it is loaded into the memory of the computer by the loader and execution begins..2 Generation of physical Address The utilization of the segment registers essentially divide the memory space into overlapping segments.. .1. The process for a particular system may not correspond exactly to the one diagrammed in the figure.3(b). Although the I/O can be performed by modules within the program.

STACK-If segments in different object modules have the same name and the combine-type STACK. then they are concatenated into a single segment in the load module.1: Creation and Execution of a program Segment Combination In addition to the linker commands. Sometimes segments with the same name are concatenated and sometimes they are overlaid. then they are overlaid so that they have the same beginning address. The possible combinetypes are: PUBLIC-If the segments in different object modules have the same name and the combine-type PUBLIC. the ASM-86 assembler provides a means of regulating the way segments in different object modules are organized by the linker.. 5. only . The length of the common segment is that of the longest segment being overlaid. AT-The AT combine-type is followed by an expression that evaluates to a constant which is to be the segment address. then they become one segment whose length is the sum of the lengths of the individually specified segments. The ordering in the concatenation is specified by the linker command.Fig. Segments that have different names cannot be combined and segments with the same name but no combine-type will cause a linker error. Just how the segments with the same name are joined together is determined by modifiers attached to the SEGMENT directives. If more than one segment with the MEMORY combine type is being linked. It allows the user to specify the exact location of the segment in memory. MEMORY-This combine-type causes the segment to be placed at the last of the load module. A SEGMENT directive may have the form Segment name SEGMENT Combine-type where the combine-type indicates how the segment is to be located within the load module. COMMON-If the segments in different object modules have the same name and the combine-type is COMMON. they are combined to form one large stack. In effect.

. which have the forms: EXTRN Identifier:Type. in order to permit other object modules to reference some of the identifiers in a given module. If an identifier is defined in an object module. . one containing the external identifiers it references and one containing the locally defined identifiers that can be referred to by other modules. and the module in which VARl is defined must contain a statement of the form PUBLIC . . . Identifier where the identifiers are the variables and labels being declared as external or as being available to other modules.. or DWORD and for a label it may be NEAR or FAR. Access to External Identifiers Clearly. the others will be overlaid as if they had COMMON combine types. the assembler must be informed in advance of any externally defined identifiers that appear in a module so that it will not treat them as being undefined. object modules that are being linked together must be able to refer to each other. Also. Fig. .. In the statement INC VAR1 if VAR1 is external and is associated with a word. the given module must include a list of the identifiers to which it will allow access. Therefore. . then it is said to be a local (or internal) identifier relative to the module. then It is referred to as an external (or global) identifier relative to the module. For a variable the type may be BYTE. then there will be an undefined external reference and a linker error will occur. 5. . . . Identifier:Type and PUBLIC Identifier. VAR1 :WORD. For single-object module programs all identifiers that are referenced must be locally defined or an assembler error will occur.2 shows three modules and how the matching is done by the linker while joining them together.VAR1…. For multiple-module programs. .. If this is not the case. each module may contain two lists. These two lists are implemented by the EXTRN and PUBLIC directives. a type specifier must be associated with each identifier in an EXTRN statement. then the module containing the statement must also contain a directive such as EXTRN . there must be a way for a module to reference at least some of the variables and/or labels in the other modules.the first one will be treated as having the MEMORY combine-type.. WORD. That is. . One of the primary tasks of the linker is to verify that every identifier appearing in an EXTRN statement is matched by one in a PUBLIC statement. and if it is not defined in the module but is defined in one of the other modules being linked. Because the assembler must know the type of all external identifiers before it can generate the proper machine code. .

Fig. The offsets associated with all external references can be assigned once all of the object modules have been found and their external symbol tables have been examined. on the other hand the call of macros is done as if it were an assembler instruction. and keep the addition in the BX register: Adding Proc Near . an offset and a segment address. 5. We can say then that a procedure is an extension of a determined program. Example of procedure: For example. Another difference between a macro and a procedure is the way of calling each one. Define macros and procedures. if we want a routine which adds two bytes stored in AH and AL each one. to call a procedure the use of a directive is required. The offsets for the local identifiers can be and are inserted by the assembler. The assignment of the segment addresses is called relocation and is done after the king process has determined exactly where each segment is to be put in memory. but the offsets for the external identifiers and all segment addresses must be inserted by the linking process. there are two parts to every address. In what way is Procedures better than macros. The main difference between a macro and a procedure is that in the macro the passage of parameters is possible and in the procedure it is not. At the moment the macro is executed each parameter is substituted by the name or value specified at the time of the call. while the macro is a module with specific functions which can be used by different programs.there are other programming languages which do allow it. this is only applicable for the MASM . 4. A macro is a group of repetitive instructions in a program which are codified only once and can be used as many times as necessary.2: Illustration of the matching verified by the linker As we have seen. Declaration of the procedure .

Ah Mov Ah. Specifying ports in some IN and OUT operations SI .the base address register (divided into BH / BL). 02H MOV DH. 0 .Mov Bx. CX .the data register (divided into DH / DL): 1. each register has its own name: AX . Generates shortest machine code 2. Row MOV DL.the accumulator register (divided into AH / AL): 1. 0 INT 10H POP DX POP BX POP AX ENDM 5. 8086 CPU has 8 general purpose registers. Input & Output BX . Column MOV BH. Explain the function of any 3 flag of a 8086 flag register with examples. One number must be in AL or AX 4. Ax Ret . Multiplication & Division 5. Content of the procedure Mov B1. Return directive Add Endp . logic and data transfer 3. 00 Add Bx. End of procedure declaration and an example of Macro: Position MACRO Row. Repetitive operations on strings with the REP command 3. Count (in CL) of bits to shift and rotate DX . Arithmetic.the count register (divided into CH / CL): 1. Iterative code segments using the LOOP instruction 2. Column PUSH AX PUSH BX PUSH DX MOV AH. DX:AX concatenated into 32-bit register for some MUL and DIV operations 2.source index register: .

The segment registers have a very special purpose . we could set the DS = 1230h and SI = 0045h. Used as source in some string processing instructions 3.pointing at accessible blocks of memory. Offset address relative to SS 3. An empty stack will had SP = FFFEh SEGMENT REGISTERS CS . Primarily used to access parameters passed via the stack 2. Offset address relative to DS DI . BP and SP work with SS segment register.generally points at segment where variables are defined.points at the segment containing the stack. SS . The CPU makes a calculation of the physical address by multiplying the segment register by 10h and adding the general purpose register to it (1230h * 10h + 45h = 12345h): The address formed with 2 registers is called an effective address. Always points to top item on the stack 2. ES . DS . this is never a good idea. . By default BX.base pointer: 1. Offset address relative to SS SP . For example if we would like to access memory at the physical address 12345h (hexadecimal). it's up to a coder to define its usage.extra segment register.points at the segment containing the current program.destination index register: 1. Although it is possible to store any data in the segment registers. Used as destination in some string processing instructions 3. which is limited to 16 bit values. Can be used for pointer addressing of data 2. Segment registers work together with general purpose register to access any memory value.1. SI and DI registers work with DS segment register.stack pointer: 1. Can be used for pointer addressing of data 2. This way we can access much more memory than with a single register. Offset address relative to ES BP . Always points to word (byte at even address) 4.

. and to 0 when there is odd number of one bits.Other general purpose registers cannot form an effective address. 9.set to 1 when there is an unsigned overflow for low nibble (4 bits). Offset address relative to CS IP register always works together with CS segment register and it points to currently executing instruction.set to 1 when result is negative.) 6. 4. and to determine conditions to transfer control to other parts of the program. FLAGS REGISTER Flags Register . When there is no overflow this flag is set to 0.the processing is done forward.255). 2. 3. Overflow Flag (OF) . 5. BH and BL cannot. For non-zero result this flag is set to 0... Generally you cannot access these registers directly.the instruction pointer: 1.127). Carry Flag (CF) . this allows to determine the type of the result. SPECIAL PURPOSE REGISTERS IP .set to 1 when result is zero. For example.this flag is set to 1 when there is even number of one bits in result. when this flag is set to 0 . When result is positive it is set to 0. although BX can form an effective address. For example when you add bytes 255 + 1 (result is not in range 0. Also. 8.this flag is used by some instructions to process data chains...determines the current state of the processor. Trap Flag (TF) . Always points to next instruction to be executed 2. Auxiliary Flag (AF) . Parity Flag (PF) .Used for on-chip debugging. (This flag takes the value of the most significant bit. 7. when you add bytes 100 + 50 (result is not in range -128. Interrupt enable Flag (IF) . when this flag is set to 1 the processing is done backward.set to 1 when there is a signed overflow.this flag is set to 1 when there is an unsigned overflow. Sign Flag (SF) . Direction Flag (DF) . They are modified automatically by CPU after mathematical operations. 1. Zero Flag (ZF) .when this flag is set to 1 CPU reacts to interrupts from external devices.

As an example consider the problem of moving the contents of a block of memory to another area in memory.2(a). is shown in Fig. Both operands are memory operands. depending on the type of STRING1 and STRING2. When working with strings. thus decreasing overall processing time. A solution that uses only the MOV instruction. 6. which cannot perform a memory-to-memory transfer. 3. Their auto-indexing obviates the need for separate incrementing or decrementing instructions.2: Program sequences for moving a block of data A solution that employs the MOVS instruction is given in Fig. . the advantages of the MOVS and CMPS instructions over the MOV and CMP instructions are: 1. They are only 1 byte long. Note that the second program sequence may move either bytes or words. 6. What are the advantages of the MOVS and CMPS instructions over the MOV and CMP instructions? Explain. Fig. 2. 6.6.2(b).

7. the current thread. or a special instruction in the instruction set which causes an interrupt when it is executed. and after the interrupt handler finishes. or admission. requiring additional care in programming. or short-term scheduler). In systems programming. ISR) to deal with the event. For example. In a real time system. scheduler. Each interrupt has its own interrupt handler. For example. it occupies the "created" or "new" state. A software interrupt is caused either by an exceptional condition in the processor itself. processes are "stored" on main memory. In this state. the process awaits admission to the "ready" state. the processor resumes execution of the previous thread. leading to an inability to meet process deadlines. . if the processor's arithmetic logic unit is commanded to divide a number by zero. such as to request services from low level system software such as device drivers. Created [edit] (Also called New) When a process is first created. saving its state. 9. hardware interrupts are asynchronous and can occur in the middle of instruction execution. Typically in most desktop computersystems. perhaps causing the computer to abandon the calculation or display an error message. This interruption is temporary. admitting too many processes to the "ready" state may lead to oversaturation and overcontention for the systems resources. Unlike the software type (below). What is interrupt? How does the computer respond to interrupts? Explain. The former is often called a trap or exception and is used for errors or events occurring during program execution that are exceptional enough that they cannot be handled within the program itself. An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing. an interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention. Ready or waiting [edit] A "ready" or "waiting" process has been loaded into main memory and is awaiting execution on a CPU (to be context switched onto the CPU by the dispatcher. In most of these states. this admission will be approved automatically. computers often use software interrupt instructions to communicate with the disk controller to request data be read or written to the disk. The following typical process states are possible on computer systems of all kinds. This admission will be approved or delayed by a longterm. pressing a key on thekeyboard or moving the mouse triggers hardware interrupts that cause the processor to read the keystroke or mouse position. The number of hardware interrupts is limited by the number of interrupt request (IRQ) lines to the processor. but there may be hundreds of different software interrupts. either a part of the computer itself such as a disk controller or an external peripheral. and executing a small program called an interrupt handler (or interrupt service routine. There may be many "ready" processes at any one point of the system's execution—for example. however for real-time operating systems this admission may be delayed. The processor responds by suspending its current activities. The act of initiating a hardware interrupt is referred to as an interrupt request (IRQ). For example. this impossible demand will cause a divide-by-zero exception. There are two types of interrupts: A hardware interrupt is an electronic alerting signal sent to the processor from an external device. Draw and explain Process states and state changes. in a one-processor system. Software interrupt instructions function similarly to subroutine calls and are used for a variety of purposes.

For reasons of simplicity. The MULTIBUS has been physically implemented on an etched backplane board which is connected to each module using two edge connectors. Modern computers are capable of running many different programs or processes at the same time. most microcomputers.only one process can be executing at any one time. and P2 is an optional connector consisting of 60 auxiliary lines. and all other "concurrently executing" processes will be waiting for execution. The connector P1 consists of 86 pins which provide-the major bus signals. are not in the ready queue. primarily used for power failure detection and handling. a microcomputer manufacturer makes assumptions about the bus that is to be used to connect its devices together Frequently.e. denoted PI and P2. The process's instructions are executed by one of the CPUs (or cores) of the system. are built around a primary system bus which connects all of the major components in the system. Explain the 8288 Bus controller. the CPU is only capable of handling one process at a time. 9. I shown in Fig.13. Processes that are ready for the CPU are kept in a queue for "ready" processes. these assumptions become formalized and constitute what is referred to as a bus standard The Intel MULTIBUS has gained wide industrial acceptance and several manufacturers offer MULTIBUS-compatible modules. . request/grant) control signals. There is at most one running process per CPU or core.. Other processes that are waiting for an event to occur. The master/slave relationship is dynamic with bus allocation being accomplished through the bus allocation (i. only two devices may communicate with each other over the bus. At any point in time. one being the master and the other the slave. and low cost. flexibility. This bus is designed to support both 8-bit and 16bit devices and can be used in multiprocessor systems in which several processors can be masters. A ready queue or run queue is used in computer scheduling. However. such as loading information from a hard drive or waiting on an internet connection. Running A process moves into the running state when it is chosen for execution. In order to obtain a foundation while designing its products. including those involving multiprocessor configurations. 10.

Because the loader is needed only after a reset. The MULTIBUS has 20 address lines. Data lines. therefore. 4. and I/O write ( ) lines are defined to be the same as they were in the discussion of the 8288 bus controller. where the numeric suffix represents the address bit in hexadecimal. a bootstrap loader may be stored in an auxiliary ROM and a monitor in a ROM. There are 16 bidirectional data lines ( ). the duration of a bus cycle varies depending on the speed of the bus master and the slave. This asynchronous nature enables the system to handle slow devices without penalizing fast devices 10. Explain how 8086 and its coprocessor interacts when an instruction is executed by the coprocessor.Fig. Because a master must wait to be notified of the completion transfer.) The two inhibit signals are provided for overlaying RAM. The memory read ( ).13: Illustration of a module being plugged into MULTIBUS The P1 lines can be divided into the following groups according to their functions: 1. and auxiliary ROM in a common address space. 2. I/O read ( ). could be raised while remains low.Then. to verify the end of a transfer. ROM. If control is passed to the user.. one may want to permit nonstandard MULTIBUS transfers between memory and an 8086. and could both be activated while the loader is executing. thus allowing the RAM to fill the entire memory space during normal operation.e. There is an acknowledge ( ) signal which serves the same purpose as the READY signal in the discussion of the bus control logic. Utility lines. . In a general setting it may be received by bus master. Bus access control lines. The address lines are driven by the bus master to specify the memory location or I/O port being accessed. 9. i. any 16-bit interface must include a swap byte buffer so that only the lower data lines are used for all byte transfers.. 5. Address lines. (It should be pointed out that because an 8086 expects a byte to be put on the high-order byte of the bus when is active. Data transfers on the MULTIBUS bus are accomplished by handshaking signals in a manner similar to that described in the preceding sections. only eight of which are used in an 8-bit system. The MULTIBUS standard calls for all single bytes to be communicated over only the lower 8 bits of the bus. memory write ( ). Command and handshaking lines. 3. labeled through . For example. when the monitor is in control. and could both be deactivated.

BX. Except for the IP. and the segment group. There is a data group. or the upper and lower bytes can be accessed separately. For example. and I/O roles: BX may be used as a base register in address calculations. either the 2 bytes in BX can be used together. which includes base and index registers. The pointer and index group consists of the IP. CX and DX registers. the control unit and working registers are divided into three groups according to their functions. but the complete instruction and stack addresses are formed by adding the contents of these registers to the contents of the code segment (CS) and stack segment (SS) registers. The word “displacement” is used to indicate a quantity that is added to the contents ‘of a register(s) to form an EA. DX is used to hold the I/O address during certain I/O operations.1: Internal Architecture of 8086 In addition to serving as arithmetic registers. BP is a base register for accessing the stack and may be used with other registers and/or a displacement that is part of the instruction. The result of such an address computation is called an effective address (EA) or offset. SP. and DI registers. a pointer can be used to hold an operand. the BX. and a displacement. which is actually a 6-byte queue.Figure 3. The final data address. but must be accessed as a whole. Except for the instruction register. The instruction pointer IP and SP registers are essentially the program counter and stack pointer registers. SI. CX is used as an implied counter by certain instructions. The data group consists of the AX. a data address may be formed by adding together a combination of the BX or BP register contents. .1 shows the internal architecture of the 8086. the pointer group. Although they may be used by themselves. Fig 3. counting. The SI and DI registers are for indexing. To provide flexible base addressing and indexing. These registers can be used to store both operands and results and each of them can be accessed as a whole. All of the registers are 16 bits wide. but also contains the program counter and stack pointer. they are often used with the BX or BP registers and/or a displacement. SI or DI register contents. or the upper byte BH or the lower byte BL can be used by itself by specifying BH or BL. which is essentially the set of arithmetic registers. CX and DX registers play special addressing. respectively. which is a set of special purpose base registers. BP.

data. or stack portion of a program to be more than 64K bytes long by using more than one code. SS.2 Generation of physical Address The utilization of the segment registers essentially divide the memory space into overlapping segments. must contain 20 bits. thus a 20-bit result is produced. SI. beginning at an address that is divisible by 16. with each segment being 64K bytes long and beginning at a 16byte. Allows the instruction. boundary. IP. Allow the memory capacity to be 1 MB even though the addresses associated with the individual instructions are only 16 bits wide. are only 16 bits wide and." e. An illustration of the example above is given in Fig. The advantages of using segment registers are that they: 1. We will hereafter refer to the contents of a segment register as the segment address . (IP) means the contents of IP. As indicated above. called the physical address.3(b). i. SP.Permit a program and/or its data to be put into different areas of memory each time the program is executed. then the next instruction will be fetched from 0002 Effective address + 12340 beginning segment address 12342 Physical address of instruction [It is standard notation for parentheses around an entity to mean "contents of. all addresses are given in hexadecimal.e. BP.3( a) and the overall segmentation of memory is shown in Fig. . the beginning segment address. or simply. 3. On the other hand. the BX. 3. and the segment address multiplied by 16 as the beginning physical segment address . its data. As an example.. or paragraph. therefore. and the stack. Also. 3.however. 2.. the registers that can be used for addressing.] Fig. if (CS) = 1234 and (IP) = 0002. The segment group consists of the CS. and ES registers. or stack segment (SS) register. Facilitate the use of separate memory areas for a program. the address put on the address bus.g. data.3. and DI registers. an effective address has only 16 bits. extra segment (ES).2. is determined by the EA and the appropriate data segment (DS). The addition is carried out by appending four 0 bits to the right of the number in the segment register before the addition is made. DS. 3. The extra 4 bits are obtained by adding the effective address to the contents of one of the segment registers as shown in Fig. or stack segment.

it is set when the MSB needs a borrow and there is no borrow from the MSB or vice versa.Fig 3. otherwise it is cleared. The condition flags are: SF (Sign FIag)-Is equal to the MSB of the result. 3. and a subtraction causes it to be set if a borrow is needed. which reflect the result of the previous operation involving the ALU. for addition this flag is set when there is a carry into the MSB and no carry out of the MSB or vice versa. Each bit in the PSW is called a flag. and the control flags. i. More specifically. but 7 of them are not used. if the previous instruction performed the addition 0010 0011 0100 1101 + 0011 0010 0001 0001 0101 0101 0101 1110 then following the instruction: SF=0 ZF=0 PF=0 CF=0 AF=0 OF=0 . OF (Overflow Flag)-Is set if an overflow occurs. ZF (Zero Flag)-Is set to 1 if the result is zero and 0 if the result is nonzero.4.3 Memory segmentation The 8086’s PSW contains 16 bits. Since in 2’s complement negative numbers have a 1 in the MSB and for nonnegative numbers this bit is 0. PF (Parity Flag)-Is set to 1 if the low-order 8 bits of the result contains an even number of 1’s. This flag is used exclusively for BCD arithmetic. For subtraction. As an example..e. The 8086 flags are divided into the conditional flags. a result is out of range. CF (Carry Flag)-An addition causes this flag to be set if there is a carry out of the MSB. AF (Auxiliary Carry Flag)-Is set if there is a carry out of bit 3 during an addition or a borrow by bit 3 during a subtraction. which control the execution of special functions. this flag indicates whether the previous result was negative’ or nonnegative. The flags are summarized in Fig. Other instructions also affect this flag and its value will be discussed when these instructions are defined.

If zero. . IF (Interrupt Enable Flag)-If set. Otherwise. these interrupts are ignored. the string is processed from the high address towards the low address. a trap is executed after each instruction.4: PSW register of 8086 If the previous instruction performed the addition 0101 0100 0011 1001 + 0100 0101 0110 1010 1001 1001 1010 0011 then the flags would be: SF = 1 ZF = 0 PF = 1 CF = 0 AF = 1 CF = 1 The control flags are: DF (Direction Flag)-Used by string manipulation instructions.Fig 3. otherwise. a certain type of interrupt (a maskable interrupt) can be recognized by the CPU. TF (Trap Flag)-If set. the string is processed from its beginning with the first element having the lowest address.