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Digital Design Using VHDL

Using Xilinx’s Tool for Synthesis and ModelSim for Verification Part (III) Ahmed Abu-Hajar, Ph.D. Digitavid, Inc San Jose, CA

Session Three Outline
Process Sequential Statements Concurrent Conditional Statements Functions

wait statement ( if a sensitivity list is not specified) end process label_name. -. Process M2 M3 M1 M4 .Process In VHDL Process executes statements sequentially Syntax Label_name: PROCESS (sensitivity list) ( if no wait statement is used) --constant declaration -.variable declaration --subprogram declaration begin sequential statement.

functions or procedures They execute sequentially ( one statement after the other) – – – – – – – Wait statement If statement Case statement Loop statement Next statement Exit statement Null statement .Sequential Statements Must be used within processes.

function or procedure .last sequence of statements end if. Must be within a process.IF Statement Syntax: If condition1 then --Sequence of statements elsif codition2 then --sequence of statement elsif codition3 then --sequence of statement else -.

clk : in std_logic. end MY_D_Latch. . Q : inout std_logic).Example: D-Latch Open Project Navigator and create an entity for the given D-latch clk D D Latch Q entity MY_D_Latch is Port ( D.

not required Why? end if. else Q <= Q. end Behavioral. -. Verify your code and view the synthesizer D D Latch Q clk . end process.Example: D-Latch architecture Behavioral of MY_D_Latch is begin proc_1: process(clk) begin if(clk'event and clk = '1') then Q <= D.

Example: D-Latch Verify your code and view the synthesizer Open a new source for simulation and call it TB_My_D_Latch Test the D-Latch by assigning vlaues to the inputs D D Latch Q clk .

end case.CASE Statement Syntax Case expression is When case1 => sequence of sequential statements. when others => sequence of sequential statements. . . Must cover all possibilities Does not have priority when synthesized . . When case2 => sequence of sequential statements.

and F is an 8-bit output a 3 entity MY_DEC is Port ( a : in STD_LOGIC_vector (2 downto 0). F : out STD_LOGIC_VECTOR (7 downto 0)).Example: 3-8 Decoder Create and entity called MY_DEC with a as 3-bit inputs. 3:8 DEC 8 f . end MY_DEC.

when "001" => F<= a[1]. Else Case S when "000" => F<= a[0]. when "101" => F<= a[5]. when "010" => F<= a[2]. a 8 8:1 MUX f RES S 3 . end case. when "100" => F<= a[4]. RES) begin if (RES’event and RES= ‘1’) then F <= ‘1’. when "111" => F<= a[7]. when others => F<=‘0’. when "011" => F<=a[3] . end process.Example: 8-1 MUX architecture Behavioral of MY_MUX is begin process (S. end Behavioral. when "110" => F<= a[6].

B.wait for some specified time Examples: Wait on A.wait until an event has occurred on A or B Wait until A = ’1’.wait until A = ‘1’ is true Wait for 10 ns. -. -. -.Wait Statement Three Types of wait statements Wait on -.waits on a list of variables or signals Wait until -.waits until a specific condition is true Wait for -.process will pause for 10ns The wait for is used for simulation and it is not synthesized .

sequential statements END LOOP loop_label.For and While Loop Statement Syntax: loop_label:FOR Index IN range LOOP -. Syntax: Label_name :WHILE condition LOOP -. .sequence of statements END LOOP Label_name.

Concurrent Vs. Concurrent Signal Assignment executes the statement when there is an event causing a change within the statement. Sequential Signal Assignment Sequential Signal Assignment executes the statement in the order it was listed. Example: – A <= B or C. -.concurrent signal assignment – The concurrent signal statement is activated at the beginning of the simulation and every time there is a change in B or C. .

Conditional Concurrent Signal Statement There are two types: 1.WHEN … ELSE: Syntax: Label: signal_name <= Assignment_1 WHEN condition_1 else Assignment_2 WHEN condition_2 else Assignment_n WHEN condition_n else Assignement_n+1. Example: Ex: A <= ‘0’ when Reset=’1’ else B AND C when contol = ‘1’ else B OR C. .

D WHEN others. B WHEN 1. Assignment_n WHEN choice_n. Example: EX: WITH (S1 + S2) SELECT C <= A WHEN 0.WITH…SELECT … WHEN Syntax: Label: WITH expression SELECT Signal_name <= Assignment_1 WHEN choice_1. Assignement_n+1 WHEN OTHERS. .Conditional Concurrent Signal Statement 2. Assignment_2 WHEN choice_2.

end Behavioral.Example: Conditional Decoder architecture Behavioral of MY_DECODER_3_8 is begin OUTPUT <= B"0000_0000" when RES='1' else B"0000_0001" when RES='0' and INPUT ="000" else B”0000_0010" when RES='0' and INPUT ="001" else B"0000_0100" when RES='0' and INPUT ="010" else B"0000_1000" when RES='0' and INPUT ="011" else B"0001_0000" when RES='0' and INPUT ="100" else B"0010_0000" when RES='0' and INPUT ="101" else B"0100_0000" when RES='0' and INPUT ="110" else B"1000_0000" when RES='0' and INPUT ="111". DECODER 3:8 OUTPUT[0] OUTPUT[1] OUTPUT[2] OUTPUT[3] OUTPUT[4] OUTPUT[5] OUTPUT[6] OUTPUT[7] INPUT[0] INPUT[1] INPUT[2] RESET .

Functions in VHDL FUNCTION is a class of subprograms FUNCTIONs compute and return value when it is invoked FUNCTION may take parameters to compute its returned value FUNCTION may not modify or change its passed parameters FUNCTION may be declared in the declaration section of the architecture or in package body FUNCTIONS are called within the architecture body Three things we need to know about functions: Function Heading: How to declare the function Function Body: How functions evaluate the returned value Function call: how to call function to evaluate a value .

-. -. Function Heading Function Body .variable declarations. BEGIN -.Functions in VHDL Syntax: FUNCTION function_name ( passing_parameters) RETUTN return_data_type i -. END function_name.RETURN returned_value.sequential statements.constant declarations.

b). B:std_Logic) RETUTN std_logic is BEGIN -. Begin f <= compare (a. END function_name. End if . else RETURN A.sequential statements. if (A = ‘0’ and B = ‘1’) then RETURN B. End behavior Function Heading Function Body .Functions in VHDL Example: Architecture behavioral of my_one_bit_comparator is FUNCTION compare ( A:std_logic.