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Jun 03, 2013

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24-bit Sigma Delta ADC Design

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24-bit Sigma Delta ADC Design

Attribution Non-Commercial (BY-NC)

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LIU Yuyu ()**, GAO Jun ( ), YANG Xiaodong ()

AIC Department, Vimicro Beijing LTD, Beijing 100191, China Abstract: This paper describes a low-power low-cost 24-bit - digital-to-analog converter (DAC) for portable digital-audio applications. The interpolation filter uses a no-multiplier scheme to implement the arithmetic units and reading-writing common storage scheme for the delay-line to significantly reduce the die area. A 15-level quantizer, third-order, single-stage - modulator is employed to reduce the passband quantization noise, relax the out-of-band filtering requirements, and enhance immunity to clock jitter. A data weighted averaging algorithm is used to mitigate the nonlinearity caused by capacitor mismatch. A direct charge transfer switched-capacitor low-pass filter (DCT-SC LPF) is used to reconstruct the analog signal to reduce the kT/C noise and capacitor mismatch effect with a small increase of the power dissipation. The chip was

2 fabricated in the SMIC 0.13 m 1P5M CMOS process. The cell area of the digital part is 0.056 mm and the 2 total area of the analog part is 0.34 mm . The supply voltage is 1.2 V for the digital circuit and 3.3 V for the

analog circuit. The power consumption of the analog part is 3.5 mW. The audio DAC achieves a 100 dB dynamic range and an 84 dB peak signal-to-noise-plus-distortion ratio over a 20 kHz passband. The results show that these performances are good enough for high quality portable audio applications. Key words: - digital-to-analog converter; - modulator; halfband interpolation filter; low-cost; low-power

Introduction

The oversampling noise-shaping - digital-to-analog converter (DAC) has advantages over the conventional Nyquist sampling rate DAC. The oversampling noiseshaping technique enables the - DAC to achieve a high conversion precision of more than 20 bits, with only a simple low-bit internal analog DAC and an analog LPF with little additional implementation overhead. The - DAC transfers the design complexity of the analog field to the digital field and trades the time precision for space precision. With advanced VLSI techniques, the oversampling noise-shaping -

Received: 2010-01-05; revised: 2010-04-06

DAC is now being widely applied in the digital-audio field[1]. There are several key specifications for a DAC for portable audio systems. The power dissipation directly affects the battery life, while the chip area directly affects the product cost. A dynamic range of 100 dB is required to ensure high quality sound. This paper describes an audio DAC that meets these needs with the architectural and circuit level design considerations needed to realize these performance goals.

Architecture

E-mail: liuyuyu@vimicro.com; Tel: 86-10-68948888-7100

The - DAC architecture is shown in Fig. 1 where fs is the input data sampling frequency. The input signal is oversampled by the digital interpolation filter and then quantized by the digital - modulator with quantization noise shaping. The analog signal is

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reconstructed and the high-frequency quantization noise is removed by a simple internal DAC and an

analog LPF.

Significant power and area savings can be achieved by proper allocation of the noise budget at the architecture level. In the deep sub-micron technology, the implementation overhead for an analog circuit is larger than for a digital circuit. So, the entire noise budget should be allocated to the analog part to save power and area. The demands on the passband quantization noise of the digital part are then almost negligible. The SNR design objective of this design is near 100 dB. If the output SNR of the digital part is selected as 130 dB, the noise budget of the analog part is 1000 times that of the digital part, and the passband noise from the digital part is small enough to be neglected. Thus, the SNR design objective of the digital part is 130 dB and the SNR of the analog part is 100 dB. For the digital part, the primary passband noise is produced by the - modulator quantization process. Therefore, the - modulator is designed first to meet the SNR objective and then the interpolation filter is designed to cooperate with the - modulator.

and V, to its single output, Y. The output of the linear block is then Y ( z ) = L0 ( z )U ( z ) + L1 ( z )V ( z ) (1)

In practice, the quantizer is usually modeled using the additive quantization noise model. Using E(z) = V(z) Y(z), Eq. (1) can be re-arranged to give the familiar formula for the output V in terms of its input signal and the error signal: (2) V ( z ) = G ( z )U ( z ) + H ( z ) E ( z ) The noise transfer function is 1 H ( z) = 1 L1 ( z ) The signal transfer function is L (z) G( z) = 0 1 L1 ( z )

2.2 Noise transfer function design

(3)

2

2.1

- Modulator

General type choice

(4)

Noise-shaping - modulators can be roughly divided into single-bit single-stage low-order designs, singlebit single-stage high-order designs, multi-stage cascaded designs with feed-forward error cancellation, and multibit single-stage designs[2]. The single-stage topology has the advantages of less effect of imperfect matching and simple circuit design in comparison with the multi-stage topology. The multibit designs have lower quantization noise, smaller idle channel tones, and high loop stability compared to their single-bit counterparts. A multibit high-order single-stage design is employed in this design. Figure 2 shows the universal architecture of a single-quantizer - modulator. The modulator is split into a linear block (the loop filter) and a nonlinear block (the quantizer). The linear block has two transfer functions, L0 and L1 , which connect its two inputs, U

An n-th-order pure noise-differencing - modulator has a noise transfer function of the form H ( z ) = (1 z 1 ) n (5) where n is the order of differentiation. With the white noise approximation and treating the quantization error as having equal probability of lying anywhere in the range of /2, the SNR of the modulator in Eq. (5) is given by 2n 12M M (6) SNR = 10log 2 (2n + 1) where M is the oversampling ratio equal to 128 in this design. is the quantizer step, which for a B-bit quantizer is =1/(2B11). Equation (6) was derived from the linear model and is relative to 0 dB input[3]. The

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theoretical SNR for two - modulators estimated by Eq. (6) are listed in Table 1.

Table 1 Theoretical SNR and stability of - modulators Quantizer n=2 bit number Ideal Ideal Stability (bit) SNR (dB) SNR (dB) 2 3 103 113 Stable Stable 137 146 n=3 Stability Unstable Conditionally stable Ampmax= 7 dB, SNRmax= 135 dB Conditionally stable Ampmax= 3 dB, SNRmax= 148 dB Conditionally stable Ampmax= 1 dB, SNRmax=155 dB

120

Stable

154

optimization methodology was used here to relocate the closed-loop poles of the noise transfer function. The optimization problem was solved numerically using Matlab. The zeros of the optimized noise transfer function are all equal to 1 and the poles of the optimized noise transfer function are 0.36598, 0.39672 + 0.32442i, and 0.39672 0.32442i. The corresponding transfer function is then (1 z 1 )3 = H ( z) = D( z )

(7)

127

Stable

160

The SNRs given by Eq. (6) do not all have meaning. Since the performance level of a higher-order modulator with H(z) given by Eq. (5) is not achievable in practice. Higher-order modulators may be unstable or only conditionally stable. Since their stable input range is limited or nonexistent. The stability evaluations listed in Table 1 are based on discrete-time simulations in Matlab. Ampmax is the maximum stable input amplitude where a unit-amplitude sine wave was the 0 dB reference and SNRmax is the peak SNR. The - modulator with more than 130 dB SNR and a large stable input range used here is based on a 4-bit third-order single-stage topology. The quantization level and the noise-shaping order should not be chosen too large, because this will increase the difficulty in designing the analog post-filtering LPF and make the passband noise even more sensitive to clock jitter. Time-domain simulations and root locus analyses both suggest that the quantizer input must not be too large for the modulator to be stable. Since quantizer overload implies a smaller quantizer gain, this in turn results in larger quantizer input, which may eventually lead to a runaway state and loop instability. To improve the loop stability, the pole locations in the noise transfer function given by Eq. (5) should be optimized so that the in-band quantization noise is minimized while guaranteeing that the quantizer does not overload. The closed-loop analysis of noise shapers (CLANS)[4]

The introduction of poles into H(z) flattens the high-frequency portion of the H(z) curve and reduces the high-frequency gain, as shown in Fig. 3, where the out-of-band gain reduced from 18 dB to 9 dB. Discrete-time simulations show that the maximum stable input of the optimized modulator is 1 dB and the peak SNR is 140 dB. The stable input range is improved in comparison with the pure noise-differencing - modulator, with the penalty that the peak SNR decreases about 8 dB.

2.3 Implementation

With this stable noise transfer function, a chain of integrators with distributed feedback architecture was used to implement the - modulator, as shown in Fig. 4. This topology enables nearly flat passband response using the designed noise transfer function.

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The loop filters for this topology in the universal block diagram in Fig. 2 are then: b z 3 (8) L0 ( z ) = 1 1 3 (1 z ) a z 3 a z 1 a z 2 L1 ( z ) = 1 1 3 + 2 1 2 + 3 1 1 (9) (1 z ) (1 z ) (1 z ) Substituting Eq. (9) into L1(z) in Eq. (3) and matching the resulting expression to Eq. (7) gave the loop coefficients, a1, a2, and a3, listed in the first row of Table 2. In a similar way, the signal transfer function G(z), can be derived from Eqs. (8), (9), and (4). The passband gain of the signal transfer function is approximately equal to its DC gain, that is |G(1)|=b1/a1. Then, b1 is selected to make b1/a1=0.8 to reserve some margin for the input range and to ensure loop stability. For the hardware implementation, the coefficients are rounded to usable numbers which are integral powers of 2, as shown in the second row of Table 2.

Table 2 Double Fixed-point Coefficients of - modulator b1 0.237 98 0.25 a1 0.297 48 0.31 a2 1.234 18 1.25 a3 1.840 58 1.75

overflow and the SNR performance is acceptable. The fixed-point - modulator was then simulated using a 24-bit sine wave input in Matlab at 6.144 MHz (=128 fs, fs=48 kHz). The power spectrum is shown in Fig. 5. The simulations show that the peak passband SNR of the fixed-point - modulator is 135 dB, which is sufficient for this application.

Fig. 5 Power spectrum of the output signal of the fixed-point - modulator for an input sine wave with a frequency=3023 Hz and an amplitude= 1 dB

3 Interpolation Filter

3.1 Algorithm design

A 4-bit 15-level uniform quantizer was then used in the design. The quantizer step is 1/7. The middle quantization level is 0 and the other levels are k, k=1-7. The quantizer has two outputs as shown in Fig. 4, the feedback output and a 4-bit unsigned integer which values from 0 to 14 corresponding to the 15 quantization levels. The 4-bit integer output is sent to the analog part of the DAC. Although this multibit higher-order single-stage - modulator design suffers very little from idle channel tones, a noise-shaped dither was added[5] to improve the precision for small input signals, as shown in Fig. 4. The area cost is reduced by reducing the internal full-precision word lengths at each step along the three integrators, while guaranteeing that the adders do not

The interpolation filter was designed for upsampling the 24-bit data by 128. Since the oversampling ratio was relatively large, a multistage architecture was used to reduce the hardware cost. The first 3 stages of the interpolation are halfband finite impulse response (FIR) filters, which have a steep transition band and linear phase response, to reject baseband images around multiples of fs and to implement 8 interpolation. The final 16 fold interpolation was achieved using a SINC1 filter with a zero-order hold register and so the oversampling ratio can be conveniently adjusted. The block diagram of the multistage interpolation filter is shown in Fig. 6.

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The passband width and stopband attenuation uniquely determine the halfband filter because of the symmetry of the magnitude response. The stopband attenuation should be large enough to reject images and ensure a small passband ripple. The passband width should be appropriate for both passing a useful signal and removing the images. The total gain of the halfband interpolation filter was made equal to 1 by adding a compensation gain equal to 2 following each halfband filter. The S/H stage did not need a compensation gain. Since the inherent DC gain of a SINC1 filter is equal to its interpolation factor. A 16-bit coefficient word length was long enough to preserve the halfband filter characteristics. The interpolation filter magnitude-frequency response from dc to 10fs is shown in Fig. 7, where IF represents the interpolation factor. The filters in Stages 1 to 3 are 47, 15, and 11 long.

The output signal power spectrum of the final fixed-point interpolation filter is shown in Fig. 8, with a passband SNR of 144 dB.

Table 3 Multistage interpolation filter specification (fs=48 kHz) Parameter Oversampling ratio Passband corner frequency Passband ripple Passband droop Stopband corner frequency Stopband attenuation Passband gain 68 1 0.58fs 0.003 Min. Typ. Max. Units 128 0.42fs 0.003 0.04 dB dB dB

Fig. 8 Power spectrum of the output signal of the fixed-point interpolation filter for an input sine wave with a frequency=3023 Hz and an amplitude=0 dB

3.2

Implementation

The specifications of the final interpolation filter are listed in Table 3. The stopband attenuation is 68 dB which is sufficient for this application. The full-precision word length is preserved inside each stage and the output word length is reduced between stages to guarantee the interpolation filter SNR performance and to facilitate the RTL code verification.

The halfband filter implementation cost is approximately half that of a general FIR filter, because the halfband filter coefficients are symmetric with nearly half of them equal to zero. Using the network transpose principle, filtering and oversampling interchangeability principle, and polyphase decomposition principle[3] for filters, a halfband interpolation filter can be implemented using the equivalent structure shown in Fig. 9. This polyphase-folded structure eliminates half of the multipliers and delay-cells, half of the addition operations, and three-quarters of the

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folded delay-line. The shift control module shifts the sum in Reg2 according to the CSD code of each coefficient.

By encoding the coefficients into the canonic signed digit (CSD) code, wide bit-width multiplications can be transformed into a series of shifts and additions. The high clock rate (256fs for this design) allows implementation of all the additions in a single multiplexing adder, thereby reducing the area cost, as shown in Fig. 10 where x represents the input data. MUX1 and MUX2 supply different addends to the adder in different clock periods. Reg1 holds the accumulated sum at the end of each clock cycle and Reg2 holds the sum of a pair of delay-cells in the symmetry location of the

Table 4 Scheme 1 2 3 Adder multiplexing No Yes Yes Delay-line Register Register Storage block

The delay-line also occupies a sizable part of the entire filter. If a delay-line is relatively long, implementation using a storage block will cost less area than an implementation using ordinary registers. Stage 1 was implemented using three different schemes and synthesized using the SMIC 0.13-m process. The cell areas for the three schemes are listed in Table 4.

Three hardware implementation schemes Combinational logic area 57 067 16 733 9851 Sequential logic area 15 606 18 298 14 544 Total area (normalized) 72 673 (1) 35 031 (0.48) 24 395 (0.34)

The combinational logic area for Scheme 2 was reduced to 29% of that of Scheme 1 using the adder multiplexing technique, and the total area of Scheme 3 was reduced to 70% of that of Scheme 2 by replacing the ordinary registers by a storage block. Combining the delay lines for all 3 stages of the entire multistage interpolation filter and implementing them using a larger storage block will reduce the cell area by 15% instead of implementing the three delay lines separately. The final gate count for the multistage interpolation filter

had 9.4 thousand gates with a total cell area of 0.048 mm2.

The block diagram of the analog part of the - DAC is shown in Fig. 11. The 4-bit digital audio signal accompanied by the shaped quantization noise is converted into an analog audio signal which is then used to stimulate the speakers or headphones.

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4.1

DEM

The principal drawback of multibit quantizers is the nonlinearity of the simple 15-level internal DAC caused by element mismatch. This nonlinearity results in an imperfect dc transfer function (integral nonlinearity errors). Dynamic element matching (DEM) techniques can be used to correct the nonlinearities. The data weighted averaging (DWA) algorithm is an effective DEM algorithm which averages mismatch over a series of samples and suppresses mismatch noise by first-order noise-shaping[6,7]. The DWA processing is done in two steps as shown in Fig. 11. Firstly, the 4-bit 15-level output signal of the - modulator is converted into a 14-bit thermometer code which is then encoded to the corresponding DWA code. The 14-bit DWA code is fed to the 15-level internal SC DAC. The capacitors in the internal DAC are then selected cyclically depending on the weighting of the incoming data. The DWA algorithm performance with a random element mismatch of 0.5% standard deviation is shown in Fig. 12. The capacitor mismatch can be restricted to less than 0.5% by using relatively large capacitors, which eliminates the need for other complicated DEM techniques.

dependent on capacitor size than with the conventional SC DAC[8,9]. The SC circuit serves both as a simple DAC and a first-order LPF, which converts the input 14-bit digital signal to a continuous-amplitude signal and reduces the high-frequency quantization noise, and hence, the amount of noise modulated back to the passband. The capacitor size should simultaneously consider element mismatch, LPF passband width, chip area, and power dissipation. For the sampling capacitor, the minimum size which meets the mismatch request (less than 0.5%) was chosen to save chip area and power dissipation. An increase of the feedback capacitor size to reduce the passband width[2] and the effect of clock jitter will increase the area and parasitic effects. In this design, the feedback capacitor was set to approximately 10 the total sampling capacitance, which results in a cutoff frequency of 660 kHz. The fully differential opamp was a two-stage design with a folded-cascode first stage and a class-A second stage. The opamp bandwidth was chosen as 30 MHz with a power dissipation of 1.4 mW. Since the SC DAC output signal is treated as a continuous-time signal and not a discrete-time signal, the low-frequency opamp noise must be restricted to a low-level. The overdrive voltage of the input stage should be small and the overdrive voltage of the load transistor should be relatively large. Also, width and length of the input stage should be large to reduce the flicker noise. This design used a first-order RC LPF circuit to remove the high-frequency noise components, especially with frequencies larger than 128fs. This also converts the differential output of the SC DAC to a singe-ended output for the application. The RC LPF bandwidth is 995 kHz with R=20 k and C=8 pF. The low-frequency noise of the opamp should also be restricted.

5 Measured Performance

Fig. 12 Simulated SNDR of the - DAC for various input sine wave amplitudes for an input signal frequency=3023 Hz and a mismatch=0.005

4.2

This design uses a 15-level direct charge transfer switched-capacitor (DCT-SC) internal DAC. The DCT-SC technique makes the power consumption less

The - DAC performance was tested on an MPW test chip, which included a 24-bit audio CODEC and other circuits. The chip was fabricated using a SMIC 0.13 m 1P5M CMOS process. A microphotograph of the - DAC analog part is shown in Fig. 13. The area of the analog part was 0.34 mm2. The digital part had 11 thousand gates and a cell area of 0.056 mm2. The supply voltage for the digital part was 1.2 V and for the analog part was 3.3 V.

81

The performance is summarized in Table 6. The SNDR was measured over the 20 kHz passband with A-weighting.

Table 6 Performance Output swing Dynamic range SNR Peak SNDR Power dissipation Area Fig. 13 Analog part microphotograph Gate count Performance summary of - DAC Value 2.26 V 95 dB 84 dB Comment Peak-to-peak, single-ended With A-weighting @0 dBFS, with A-weighting

3.5 mW Analog part 0.34 mm2 Analog part 11 000 Digital part

The noise contributions of the various parts of the audio DAC are detailed in Table 5. The noise related to the digital part was a minor contribution and is, therefore, negligible. The significant noise source came from the analog part.

Table 5 Part Interpolation filter - modulator Analog part Total DAC noise distribution SNR (dB) 144 135 95 95 Description 24 bit data path Passband quantization noise With A-weighting With A-weighting

Conclusions

The output fast Fourier transform (FFT) spectrum for a 1 kHz 0 dB signal is shown in Fig. 14 with the output spectrum for a 1 kHz 60 dB signal shown in Fig. 15.

Architecture level and circuit level considerations are given for the design of a low-power low-cost 24-bit - DAC. The design flow for a multi-bit single-stage - modulator architecture is described in detail, including the general type selection, algorithm design and optimization, topology selection, and hardware implementation. Hardware implementation methods for a multistage interpolation filter are presented, including the arithmetic unit multiplexing scheme and the delay-line combination realization scheme. The interpolation filter implementation area cost can be reduced by 66% in comparison with the direct implementation method. The DCT-SC technique is used to reconstruct the analog signal and to obtain a low-power design. Other analog circuit design tradeoffs for the multi-bit - DAC are also introduced. The 24-bit - DAC with these techniques has a 100-dB dynamic range with power dissipation of about 3.5 mW and a die area of about 0.44 mm2.

References

Fig. 14 FFT spectrum of the output signal for an input of 1 kHz and 0 dB

[1] Rabii S, Wooley B A. A 1.8-V digital audio sigma-delta modulator in 0.8-um CMOS. IEEE J. Solid-State Circuits, 1997, 32: 783-796. [2] Norsworthy S R, Schreier R. Delta-Sigma Data Converters: Theory, Design, and Simulation. New York: IEEE Press, 1997. [3] Oppenheim A V, Schafer R W, Buck J R. Discrete-Time Signal Processing. 2nd Ed. New Jersey: Prentice-Hall,

Fig. 15 FFT spectrum of the output signal for an input of 1 kHz and 60 dB

82 data converters. Analog Integrated Circuits and Signal Processing, 1993, 3(3): 259-272. [5] Norsworthy S R. Effective dithering of sigma-delta modulators. IEEE Proc. ISCAS92, 1992, 2: 1304-1307. [6] Nys O, Henderson R K. A 19-bit low-power multibit sigmadelta ADC based on data weighted averaging. IEEE J. Solid-State Circuits, 1997, 32: 933-942. [7] Baird R T, Fiez T S. Linearity enhancement of multibit

Tsinghua Science and Technology, February 2011, 16(1): 74-82 deltasigma A/D and D/A converters using data weighted averaging. IEEE Trans. Circuits Syst. II, 1995, 42: 753-762. [8] Bingham J A C. Application of direct-transfer SC integrator. IEEE Trans. Circuits Syst., 1984, CAS-31: 419-420. [9] Sooch N S, Scott J W, Tanaka T, et al. 18-b stereo D/A converter with integrated digital and analog filters. In: 91st AES Convention. New York, USA, 1991: 8.67-8.78.

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