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3D Stacked Architectures with Interlayer Cooling - CMOSAIC

Prof. John Thome, LTCM-EPFL, Project PI

Prof. Yusuf Leblebici, LSM-EPFL
Prof. Dimos Poulikakos, LTNT-ETHZ
Prof. Wendelin Stark, FML-ETHZ
Prof. David Atienza Alonso, ESL-EPFL
Dr. Bruno Michel, IBM
Dr. Thomas Brunschwiler, IBM




CMOSAIC: Technological Aims

§  CMOSAIC aims to make an important contribution to the development of the first 3D computer chip with interlayer cooling for extremely high computational power with reduced power consumption. §  Very ambitious project that combines significant microchannel cooling research, 3D thermal simulations and novel new microfabrication techniques for TSVs, interconnects, bonding, etc. to make the first 3D thermal/electrical test vehicle.

Two-Phase Cooling of 3D Stacked
Microprocessors: ‘3D Test Vehicle’

Y Madhour, et al..

Fluid outlet
Fluid inlet
Si IC die

DRIE microchannels

Test vehicle

•  Flip-chip bonded (sequential)
•  Force-controlled reflow process
• Total Force on chip: 12.6 [N] at
265°C (2.2MPa)
•  Force on individual joint: 0.6g

Individual joint after reflow
Cross section – polished sample
Contact area: 70% of initial plated surface

Wafer-level TSV Process
Compatible with Interlayer Cooling

Deep TSV Fabrication process
Histogram of the TSV resistance

M Zervas, Y Leblebici

Ctsv Ccoupling Ctsv



Cooling   channel


TSV coupling capacitance simulations in the presence of liquid channels.

§  A deep TSV process, where the wafer thickness is greater than 50µm, is needed to accommodate cooling channels with depth greater than 50µm. §  Aspect ratio of the TSV is more than 1:6.

TSV  coupling  capacintace  o ver  the  cooling  liquid 70
ε  liquid  =  1 ε  liquid  =  3 ε  liquid  =  5 ε  liquid  =  7 ε  liquid  =  9 ε  liquid  =  11


  C oupling   c apacitance   [fF]






0 80






180 200 TSV  D istance  [µm]






§  Average TSV resistance below 1Ω,  with  a  peak  at  13Ω. §  Parasitic MOS capacitance Ctsv 0.8pF (Cu – SiO2- Si) §  Parasitic coupling capacitance Ccoupling over the dielectric cooling liquid up to 60fF

Chip-to-Chip Integration

Chip-level 3D integration platform based on wafer reconstitution, bonding, and TSV fabrication

Y Temiz, Y Leblebici

Microprocessor post-CMOS processing and stacking
§  Top chip thinning and etching §  Bottom chip passivation and redistribution layer patterning §  Bonding and TSV fabrication
Top Chip

§  Two 50µm thick chips are bonded and electrically connected by Cu TSVs. §  Daisy-chain measurements demonstrate 0.5Ω resistance with 99% yield for 1280 TSVs.

Bottom Chip

3D Heat Transfer Test Vehicle

Y Madhour, M Zervas, T Brunschwiler, G Schlottig, B Michel, Y Leblebici and JR Thome

2D Multi-Microchannel Flow Boiling Experiment

S Szczukiewicz, N Borhani, JR Thome –

2D visualisation of two-phase refrigerant flow

slow motion (30fps),
CCD recorded @2000fps,
IR recorded @60fps

Multi-microchannel evaporator having 67 channels with the inlet orifices e=2 and 100x100µm  cross-section areas, Tsat=31.96oC,  ΔTsub=5.63K,  q=30.69W/cm2  

Flow direction

For the test section having the orifices with the expansion ratio e=2, the flow tends to stabilize at the relatively high mass fluxes and heat fluxes.

slow motion (30fps),
CCD recorded @2000fps,
IR recorded @60fps

2D Flow Boiling Tests for Characterizing 3D-ICs

S. Szczukiewicz, N. Borhani, JR Thome

Footprint temperature maps of the test section’s base provided IR camera for two-phase flow boiling of R236fa for Gch=2’299 kg/ m2s, qb=48.6 W/cm2. 600’000 temperature pixels per second using inhouse IR camera calibration.

Water Cooled Electronic Chips – 2D Experiments

Planned: measure and evaluate
§  Impact on cooling performance in 3D chips §  Detailed heat transfer study including fluid temperature maps

Benefits of enhanced flow fluctuations for liquid cooling
§  Higher heat transfer and better hot-spot cooling

Full 3D Heat Transfer/Fluid Flow Simulator

Advantages: •  Mechanistic, flow-pattern-based methods for microchannel boiling and 2-phase pressure drop. •  Heat/fluid flow spreading, TSV’s and non-uniform q. •  Resolves vertical distribution of heat and thermal resistance between evaporator channels.

Novel 3D model for chip stacks with interlayer microchannel two-phase cooling with combined heat and flow spreading
Over three-fold increased performance when properly laying out hot spot locations in the multiple layers

Yassir Madhour, Brian P. D’Entremont and John R Thome

Fast Simplified 3D Thermal Simulator

Arvind Sridhar and David Atienza

Active Run-Time Thermal Management

Mohamed Sabry and David Atienza

Superhydrophobic Surfaces: Enhanced Flow

M. Rossier, D. Paunescu, W.J. Start



3D ALE-FEM for Microscale Two Phase Flows

G. Rabello, N. Borhani, JR Thome


standard approach
surf ace surf ace

Lagrangian approach

[1] Comparison of surface representations;
[2] Arbitrary Lagrangian-Eulerian Technique;
[3] Test case: 3D microchannel


D ( ρu ) 1 1 T + ∇p = ∇ · [ µ ( ∇ u + ∇ u )] + ρ g + f Dt Eo N 1/2

•  3D Arbitrary Lagrangian-Eulerian Finite Element code;
•  Coupled heat transfer and two-phase flow
•  Predict flows in microscale complex geometries;



mesh velocity

gravity surface

∂u ˆ ) · ∇u + (u − u ∂t

u ˆ=u
u ˆ=0

Lagrangian Eulerian



CMOSAIC - Project Summary

CMOSAIC project has: Developed numerous micro-fabrication techniques necessary for making 3D-IC stacked computer chips a future reality. Undertaken extensive micro-scale heat transfer research to understand the physical mechanisms of the flows. Developed new thermal prediction methods to describe the h.t. process. Developed simulation tools to emulate the 3D cooling process and proposed a run-time thermal control code. Developed hydrophobic surfaces. CMOSAIC is the most sophisticated 3DIC test vehicle available to date! CMOSAIC makes an important industrial statement towards 3D-IC computing.