PCM1804-Q1

www.ti.com SLES271A – JUNE 2012 – REVISED AUGUST 2012

FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz STEREO A/D CONVERTER
Check for Samples: PCM1804-Q1
1

FEATURES
Qualified for Automotive Applications AEC-Q100 Test Guidance With the Following Results: – Device Temperature Grade 3: –40°C to 85°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C3B 24-Bit Delta-Sigma Stereo A/D Converter High Performance: – Dynamic Range: 112 dB (Typical) – SNR: 111 dB (Typical) – THD+N: –102 dB (Typical) High-Performance Linear Phase Antialias Digital Filter: – Pass-Band Ripple: ±0.005 dB – Stop-Band Attenuation: –100 dB Fully Differential Analog Input: ±2.5 V Audio Interface: Master- or Slave-Mode Selectable Data Formats: Left-Justified, I2S, Standard 24Bit, and DSD Function: – Peak Detection – High-Pass Filter (HPF): –3 dB at 1 Hz, fS = 48 kHz Sampling Rate up to 192 kHz System Clock: 128 fS, 256 fS, 384 fS, 512 fS, or 768 fS

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Dual Power Supplies: – 5 V for Analog – 3.3 V for Digital Power Dissipation: 225 mW Small 28-Pin SSOP DSD Output: 1 Bit, 64 fS

APPLICATIONS
• • • • • AV Amplifier MD Player Digital VTR Digital Mixer Digital Recorder

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DESCRIPTION
The PCM1804-Q1 device is a high-performance, single-chip stereo A/D converter with fully differential analog voltage input which uses a precision deltasigma modulator and includes a linear-phase antialias digital filter and high-pass filter (HPF) that removes DC offset from the input signal. The PCM1804-Q1 device is suitable for a wide variety of mid- to highgrade consumer and professional applications, where excellent performance and 5-V analog supply and 3.3-V digital power-supply operation are required. The PCM1804-Q1 device can achieve both PCM audio and DSD format due to the precision deltasigma modulator. The PCM1804-Q1 device is fabricated using an advanced CMOS process and is available in a small 28-pin SSOP package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners.
Copyright © 2012, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

PCM1804-Q1
SLES271A – JUNE 2012 – REVISED AUGUST 2012 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION
TA –40°C to 85°C PACKAGE SSOP - DB Reel of 2000 ORDERABLE PART NUMBER PCM1804S1IDBRQ1 TOP-SIDE MARKING PCM1804Q

FUNCTIONAL BLOCK DIAGRAM
OSR0 SCKI CLK Control OSR1 OSR2

VINL+ VINL− VCOML AGNDL VREFL

Delta-Sigma Modulator (L)

Decimation Filter (L)

HPF

S/M FMT0 FMT1

VREFL Serial Output Interface VREFR LRCK/DSDBCK BCK/DSDL DATA/DSDR

VREFR AGNDR VCOMR VINR+ VINR−

Delta-Sigma Modulator (R)

Decimation Filter (R)

HPF

OVFL OVFR BYPAS

Power Supply

RST

VCC AGND

DGND

VDD
B0029-01

2

Copyright © 2012, Texas Instruments Incorporated

PCM1804-Q1
www.ti.com SLES271A – JUNE 2012 – REVISED AUGUST 2012

PIN ASSIGNMENTS
PCM1804 PACKAGE (TOP VIEW)

VREFL AGNDL VCOML VINL+ VINL− FMT0 FMT1 S/M OSR0 OSR1 OSR2 BYPAS DGND VDD

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

VREFR AGNDR VCOMR VINR+ VINR− AGND VCC OVFL OVFR RST SCKI LRCK/DSDBCK BCK/DSDL DATA/DSDR
P0007-02

Pin Functions
PIN NAME AGND AGNDL AGNDR BCK/DSDL BYPAS DATA/DSDR DGND FMT0 FMT1 LRCK/DSDBCK OSR0 OSR1 OSR2 OVFL OVFR RST SCKI S/M VCC VCOML VCOMR VDD VINL– VINL+ VINR– (1) (2) (3) PIN 23 2 27 16 12 15 13 6 7 17 9 10 11 21 20 19 18 8 22 3 26 14 5 4 24 I/O – – – I O – I I I I I O O I I I – – – – I I I Analog ground Analog ground for VREFL Analog ground for VREFR
(1)

DESCRIPTIONS

I/O Bit clock input/output in PCM mode. Left-channel audio data output in DSD mode. HPF bypass control. High: HPF disabled. Low: HPF enabled.
(1)

Left-channel and right-channel audio data output in PCM mode. Right-channel audio data output in DSD mode. (DSD output, when in DSD mode) Digital ground Audio data format 0. See Table 5. Audio data format 1. See Table 5.
(2) (2) (1)

I/O Sampling clock input/output in PCM and DSD modes. Oversampling ratio 0. See Table 1 and Table 2. Oversampling ratio 1. See Table 1 and Table 2. Oversampling ratio 2. See Table 1 and Table 2.
(2) (2) (2)

Overflow signal of left-channel in PCM mode. This is available in PCM mode only. Overflow signal of right-channel in PCM mode. This is available in PCM mode only. Reset, power-down input, active-low
(2) (3)

System clock input; 128 fS, 256 fS, 384 fS, 512 fS, or 768 fS. Slave or master mode selection. See Table 4. Analog power supply Left-channel analog common-mode voltage (2.5 V) Right-channel analog common-mode voltage (2.5 V) Digital power supply Left-channel analog input, negative pin Left-channel analog input, positive pin Right-channel analog input, negative pin
(2)

Schmitt-trigger input Schmitt-trigger input with internal pulldown (51 kµ typically), 5-V tolerant. Schmitt-trigger input, 5-V tolerant. 3

Copyright © 2012, Texas Instruments Incorporated

75 V to ensure continued device functionality. requires capacitors for decoupling to AGND Right-channel voltage reference output. These are stress ratings only. requires capacitors for decoupling to AGND DESCRIPTIONS ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE MIN Supply voltage Ground voltage differences Supply voltage difference Digital input voltage Analog input voltage TA Tstg TJ VCC VDD AGND. VINR– –0. DGND VCC. VCOML.192 32 (1) NOM 5 3. S/M. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range MIN Analog supply voltage. AGNDL. VDD Analog input voltage. LRCK/DSDBCK. RST BYPAS. VCC Digital supply voltage. VDD FMT0.864 192 10 70 MHz kHz pF °C If the VCC drops below the minimum recommended operating condition of 4.75 V. VINR+.5 4 ±0. to avoid a brown out condition the VCC power must be cycled to 0 V and then to > 4. VCOMR. OSR0.3 –0.PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www. differential input Digital input logic family Digital input clock frequency Digital output load capacitance Operating free-air temperature. TA (1) –10 System clock Sampling clock 8.3 ±10 mA 125 150 150 260 260 2 750 °C °C °C °C.25 3.5 VDD + 0.1 V VCC – VDD < 3 6. positive pin Left-channel voltage reference output. AGNDR.ti. OVFL.75 3 36. peak) ESD Rating (1) Human Body Model (HBM) AEC-Q100 Classification Level H2 Charged Device Model (CDM) AEC-Q100 750 V Classification Level C3B Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. DATA/DSDR. and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.com Pin Functions (continued) PIN NAME VINR+ VREFL VREFR PIN 25 1 28 I/O I – – Right-channel analog input. full-scale (–0 dB). VREFR. Texas Instruments Incorporated .3 5 TTL compatible MAX 5.3 –0. FMT1. OSR2. 4 Copyright © 2012. OVFR VREFL. VINL–.3 –0.3 VCC + 0. SCKI.3 MAX 6. VINL+.3 V –40 –55 –0. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. OSR1. 5 s °C kV V V V V V UNIT V V Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) Package temperature (IR reflow.6 UNIT V V Vpp 4. BCK/DSDL.

5-V tolerant) Pin 18: SCKI (Schmitt-trigger input.4 0. quad rate 192 fS.2 ±3 ±4 % of FSR % of FSR % of FSR (5) (5) (5) (5) (6) (6) (7) (7) MHz Pins 6–11. dual rate 128 fS. 24-bit data.5 dB) Bipolar zero error (1) (2) (3) (4) (5) (6) (7) HPF bypass ±0. fS = 192 kHz Copyright © 2012. PARAMETER Resolution DATA FORMAT Audio data interface format Audio data bit length Audio data format DIGITAL INPUT/OUTPUT Logic family (1) (2) TEST CONDITIONS PCM1804DB MIN TYP 24 Standard.com SLES271A – JUNE 2012 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C. dual rate 384 fS.576 36. master mode.576 36. OVFL Single rate. Texas Instruments Incorporated 5 . OVFR.PCM1804-Q1 www. 19: FMT0.ti.864 MAX UNIT Bits Bits VIH VIL IIH High-level input voltage Low-level input voltage High-level input current (3) (1) (2) (3) VDC VDC μA VIN = VDD VIN = VDD VIN = VDD IIL VOH VOL fS Low-level input current High-level output voltage Low-level output voltage Sampling frequency VIN = 0 V VIN = 0 V (1) (2) (3) (1) (2) (3) (4) μA VDC VDC kHz IOH = –1 mA IOL = 1 mA (4) CLOCK FREQUENCY 256 fS.288 18. LRCK/DSDBCK (in slave mode. and 21: DATA/DSDR. unless otherwise noted. fS = 48 kHz Dual rate.3 V. BCK/DSDL. left-justified 24 MSB first. Schmitt-trigger input) Pins 15–17. VCC = 5 V. single rate 512 fS. DSD TTL compatible 2 2 5. OSR2. single rate 256 fS. 5-V tolerant) Pins 12. 16–17: BYPAS.864 24. fS = 96 kHz Quad rate. fS = 48 kHz. FMT1. quad rate DC ACCURACY Gain mismatch. 20. LRCK/DSDBCK (in master mode). single rate System clock frequency 768 fS.432 24. 2s-complement. single-speed mode. BCK/DSDL. single rate 384 fS.864 24.576 36. OSR1.5 VDD 0. OSR0. I2S. channelto-channel Gain error (VIN = –0. VDD = 3. S/M. RST (Schmitt-trigger input with internal pulldown (51 kμ typically). system clock = 256 fS.8 65 100 ±10 ±100 ±10 ±50 2.4 32 192 12.

5/fS fS/48000 MAX –95 UNIT VIN = –0.5 dB DSD mode fS = 48 kHz. system clock = 256 fS fS = 96 kHz. single-speed mode. VDD = 3. dual rate Single rate.005 –100 0.49 fS 0.5 2.ti. 24-bit data. system clock = 256 fS fS = 192 kHz.005 –135 37/fS 9. dual rate Single rate. system clock = 256 fS fS = 192 kHz. system clock = 256 fS fS = 192 kHz.PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www. system clock = 256 fS Channel separation ANALOG INPUT Input voltage Center voltage Input impedance DIGITAL FILTER PERFORMANCE Pass-band edge Stop-band edge Pass-band ripple Stop-band attenuation Pass-band edge (–0. VCC = 5 V. or with 40-kHz LPF in calculation for dual and quad rates .547 fS ±0. system clock = 128 fS fS = 96 kHz.375 fS 0.453 fS 0.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C. system clock = 256 fS Dynamic range (Aweighted) VIN = –60 dB DSD mode fS = 48 kHz.5 dB VIN = –60 dB fS = 48 kHz. system clock = 256 fS SNR (A-weighted) fS = 96 kHz. PARAMETER DYNAMIC PERFORMANCE (8) TEST CONDITIONS PCM1804DB MIN TYP –102 –49 –101 –47 –101 –47 –100 106 112 112 112 112 105 111 111 111 111 97 109 107 107 ±2. master mode. dual rate Quad rate –3 dB Single-ended Differential input fS = 96 kHz. fS = 48 kHz.3 V. Texas Instruments Incorporated . system clock = 128 fS dB dB dB V VDC kμ Hz Hz dB dB Hz Hz Hz dB dB s s Hz The fIN = 1 kHz. with 20-kHz LPF and 400-Hz HPF in calculation for single rate. dual rate Single rate. system clock = 128 fS DSD mode fS = 48 kHz.5 dB VIN = –60 dB VIN = –0. system clock = 256 fS fS = 192 kHz. system clock = 128 fS dB VIN = –0. system clock = 256 fS.77 fS ±0. using System Two™ audio measurement system by Audio Precision™ in RMS mode.5 10 0. unless otherwise noted.005 dB) Pass-band edge (–3 dB) Stop-band edge Pass-band ripple Stop-band attenuation Group delay Group delay HPF frequency response (8) Single rate.5 dB THD+N Total harmonic distortion plus noise VIN = –60 dB VIN = –0. 6 Copyright © 2012. dual rate Quad rate Quad rate Quad rate Quad rate Quad rate Single rate.

PCM1804-Q1 www.3 V mW Power down.3 V TEMPERATURE RANGE Operation temperature θJA (9) (10) (11) (12) Thermal resistance Single rate.3 35 15 27 18 225 265 235 5 –10 100 70 290 MAX 5. PARAMETER POWER SUPPLY REQUIREMENTS VCC VDD ICC IDD Supply current Supply voltage range VCC = 5 V (9) (10) (11) (9) (12) (10) (12) (11) (12) (9) (12) (10) (12) (11) (12) TEST CONDITIONS PCM1804DB MIN 4. unless otherwise noted.25 3. master mode.com SLES271A – JUNE 2012 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C.3 V PD Power dissipation Operation. VDD = 3.3 V mA Operation. VDD = 3. VDD = 3.3 V. fS = 48 kHz. 24-bit data. VCC = 5 V.ti. VCC = 5 V. VDD = 3. VDD = 3. fS = 192 kHz Minimum load on DATA/DSDR (pin 15) °C °C/W Copyright © 2012. Texas Instruments Incorporated 7 . fS = 96 kHz Quad rate. VCC = 5 V. single-speed mode.75 3 TYP 5 3.3 V VDD = 3. fS = 48 kHz Dual rate. VCC = 5 V. system clock = 256 fS.3 V VDD = 3.3 V Operation. VCC = 5 V.6 45 20 UNIT VDC VDD = 3.

00 5. Figure 4.3 V. 24-bit data. 8 Copyright © 2012. system clock = 256 fS.50 −55 4.SINGLE RATE All specifications at TA = 25°C.75 5. DYNAMIC RANGE AND SNR vs SUPPLY VOLTAGE 120 Dynamic Range and SNR − dB −95 −40 115 Dynamic Range −100 −0. VCC = 3.ti.5 dB −45 110 SNR −105 −60 dB −50 105 −110 −20 −55 0 20 40 60 80 T − Temperature − °C 100 −20 0 20 40 60 80 G002 G001 T − Temperature − °C Figure 1.5 dB) −90 −35 THD+N − Total Harmonic Distortion + Noise − dB (−60 dB) Figure 2.00 5.5 dB −45 110 SNR −105 −60 dB −50 105 −110 4. TOTAL HARMONIC DISTORTION + NOISE vs TEMPERATURE THD+N − Total Harmonic Distortion + Noise − dB (−0. Texas Instruments Incorporated .25 5. VDD = 5 V. unless otherwise noted. fS = 48 kHz.50 VCC − Supply Voltage − V 100 4.75 5. TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE THD+N − Total Harmonic Distortion + Noise − dB (−0.50 G004 G003 VCC − Supply Voltage − V Figure 3.PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www.50 4.com TYPICAL PERFORMANCE CURVES . master mode.25 5.5 dB) −90 −35 THD+N − Total Harmonic Distortion + Noise − dB (−60 dB) DYNAMIC RANGE AND SNR vs TEMPERATURE 120 Dynamic Range and SNR − dB −95 −40 115 Dynamic Range −100 −0.

unless otherwise noted.ti. fS = 48 kHz. TOTAL HARMONIC DISTORTION + NOISE vs SAMPLING FREQUENCY THD+N − Total Harmonic Distortion + Noise − dB (−0. VDD = 5 V.com SLES271A – JUNE 2012 – REVISED AUGUST 2012 TYPICAL PERFORMANCE CURVES .PCM1804-Q1 www.SINGLE RATE (continued) All specifications at TA = 25°C. master mode. 24-bit data.5 dB) −90 −35 THD+N − Total Harmonic Distortion + Noise − dB (−60 dB) DYNAMIC RANGE AND SNR vs SAMPLING FREQUENCY 120 Dynamic Range and SNR − dB −95 −40 115 Dynamic Range −100 −0. Texas Instruments Incorporated 9 .3 V. Copyright © 2012. system clock = 256 fS.5 dB −45 110 SNR −105 −60 dB −50 105 −110 32 44.1 48 fS − Sampling Frequency − kHz −55 100 32 44.1 48 G006 G005 fS − Sampling Frequency − kHz Figure 5. −20 −40 −60 −80 −100 −120 −100 −80 −60 −40 −20 0 G009 Signal Level − dB Figure 7. VCC = 3. TOTAL HARMONIC DISTORTION + NOISE vs SIGNAL LEVEL THD+N − Total Harmonic Distortion + Noise − dB 0 Figure 6.

TYPICAL PERFORMANCE CURVES . master mode. System Clock = 256 fS AMPLITUDE vs FREQUENCY 0 −20 −40 Amplitude − dB fS = 96 kHz. and 24-bit data. AMPLITUDE vs FREQUENCY 0 −20 −40 Amplitude − dB fS = 96 kHz. AMPLITUDE vs FREQUENCY 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 12000 f − Frequency − Hz G007 AMPLITUDE vs FREQUENCY 0 Output Spectrum: −0. N = 8192 24000 f − Frequency − Hz 48000 G010 0 24000 f − Frequency − Hz 48000 G011 Figure 10. 10 Copyright © 2012.5 dB. Figure 9.3 V.com TYPICAL PERFORMANCE CURVES . VCC = 3. N = 8192 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 Output Spectrum: −60 dB. unless otherwise noted. Figure 11. unless otherwise noted.5 dB. VDD = 5 V. system clock = 256 fS. VDD = 5 V.ti. VCC = 3. fS = 48 kHz. System Clock = 256 fS −60 −80 −100 −120 −140 −160 0 Output Spectrum: −0. 24-bit data.SINGLE RATE (continued) All specifications at TA = 25°C. Texas Instruments Incorporated .3 V. N = 8192 −60 −80 −100 −120 −140 −160 Output Spectrum: −60 dB. master mode.DUAL RATE All specifications at TA = 25°C. N = 8192 24000 0 12000 f − Frequency − Hz 24000 G008 Figure 8.PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www.

master mode. AMPLITUDE vs FREQUENCY 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 11025 f − Frequency − Hz G014 AMPLITUDE vs FREQUENCY 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 22050 0 11025 f − Frequency − Hz G015 Output Spectrum: −0. N = 8192 Output Spectrum: −60 dB.ti. Figure 13. 24-bit data. VDD = 5 V.5 dB. system clock = 16. Copyright © 2012. VDD = 5 V. N = 8192 −60 −80 −100 −120 −140 −160 Output Spectrum: −60 dB. AMPLITUDE vs FREQUENCY 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 48000 f − Frequency − Hz G012 AMPLITUDE vs FREQUENCY 0 fS = 192 kHz.1 kHz. TYPICAL PERFORMANCE CURVES .5 dB. fS = 44.9344 MHz. master mode. System Clock = 128 fS −20 −40 Amplitude − dB Output Spectrum: −0. unless otherwise noted.3 V. unless otherwise noted. Texas Instruments Incorporated 11 . Figure 15. N = 8192 22050 Figure 14.PCM1804-Q1 www.com SLES271A – JUNE 2012 – REVISED AUGUST 2012 TYPICAL PERFORMANCE CURVES .QUAD RATE All specifications at TA = 25°C.3 V.DSD MODE All specifications at TA = 25°C. VCC = 3. N = 8192 96000 0 48000 f − Frequency − Hz 96000 G013 Figure 12. System Clock = 128 fS fS = 192 kHz. VCC = 3.

02 fS = 48 kHz 0.0 −10 0.51 0.0 G016 −150 0.08 0.5 3.00 0.5 fS −0.02 −0.00 0 −1 −2 −3 Amplitude − dB −4 −5 −6 −7 −8 −9 −0.0 0.47 0.PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www.45 Figure 17. Texas Instruments Incorporated .5 2.0 1.5 0.55 G019 Normalized Frequency − y fS Normalized Frequency − y fS Figure 18.00 G017 Normalized Frequency − y fS Normalized Frequency − y fS Figure 16. Figure 19.5 4.3 0.com TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE .4 0. PASS-BAND RIPPLE CHARACTERISTICS FOR SINGLE-RATE FILTER 0.Single Rate OVERALL CHARACTERISTICS FOR SINGLE-RATE FILTER 50 fS = 48 kHz 0 STOP-BAND ATTENUATION CHARACTERISTICS FOR SINGLE-RATE FILTER 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 fS = 48 kHz Amplitude − dB −50 −100 −150 Amplitude − dB −200 0.0 3.2 0.6 G018 0.53 0.04 −6.25 0.1 0.10 0.0 2.06 −0.75 1.50 0. TRANSIENT BAND CHARACTERISTICS FOR SINGLE-RATE FILTER fS = 48 kHz Amplitude − dB −0.5 1.04 dB at 0.ti.49 0. 12 Copyright © 2012.

08 0.Dual Rate OVERALL CHARACTERISTICS FOR DUAL-RATE FILTER 50 fS = 96 kHz 0 STOP-BAND ATTENUATION CHARACTERISTICS FOR DUAL-RATE FILTER 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 fS = 96 kHz Amplitude − dB −50 −100 −150 Amplitude − dB −200 0.55 G023 Normalized Frequency − y fS Normalized Frequency − y fS Figure 22.2 0.PCM1804-Q1 www.00 0 −1 −2 −3 Amplitude − dB −4 −5 −6 −7 −8 −9 −0.47 0. TRANSIENT BAND CHARACTERISTICS FOR DUAL-RATE FILTER fS = 96 kHz Amplitude − dB −0.6 1.00 G021 Normalized Frequency − y fS Figure 20.8 1.ti.3 0.02 −0.1 0.50 0.02 dB at 0.2 0.25 0.4 0.75 1.10 0.49 0.com SLES271A – JUNE 2012 – REVISED AUGUST 2012 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE . Figure 23.4 1.0 Normalized Frequency − y fS G020 −150 0.51 0.6 0.0 1.04 −6.00 0.6 G022 0. Texas Instruments Incorporated 13 .53 0.45 Figure 21.8 2.2 1.02 fS = 96 kHz 0. PASS-BAND RIPPLE CHARACTERISTICS FOR DUAL-RATE FILTER 0. Copyright © 2012.5 fS −0.5 0.0 −10 0.0 0.4 0.06 −0.

5 fS Amplitude − dB −0.Quad Rate OVERALL CHARACTERISTICS FOR QUAD-RATE FILTER 50 fS = 192 kHz 0 0 −10 −20 −30 −40 Amplitude − dB −50 Amplitude − dB −50 −60 −70 −80 −90 −100 −110 −150 −120 −130 −140 −200 0.00 0.47 0.50 0.PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www. Figure 27.8 0.9 1.10 0.06 −0.2 0.3 0. PASS-BAND RIPPLE CHARACTERISTICS FOR QUAD-RATE FILTER 0. Texas Instruments Incorporated .45 0.ti.com TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE .08 −0.75 1.5 0.51 0.3 0.02 −0.00 G025 Normalized Frequency − y fS Figure 24.7 0.02 fS = 192 kHz Figure 25.00 −2 −3 Amplitude − dB −4 −5 −6 −7 −8 −9 −3.49 0.25 0.1 0.0 Normalized Frequency − y fS G024 STOP-BAND ATTENUATION CHARACTERISTICS FOR QUAD-RATE FILTER fS = 192 kHz −100 −150 0.55 G027 Normalized Frequency − y fS Normalized Frequency − y fS Figure 26.2 0.4 0.6 0.4 0.53 0.0 0. TRANSIENT BAND CHARACTERISTICS FOR QUAD-RATE FILTER 0 −1 fS = 192 kHz 0.1 0.5 0. 14 Copyright © 2012.9 dB at 0.6 G026 −10 0.04 −0.0 0.

and quad rate eliminate the external sample-hold amplifier. The single rate. The oversampled data stream from the delta-sigma modulator is converted to a 1-fS. Copyright © 2012.2 −0. and the HPF output is converted to a time-multiplexed serial signal through the serial interface. a delta-sigma modulator with full-differential architecture for L-channel and R-channel. and it defines the full-scale voltage range of both channels.144 MHz.ti.3 0. Figure 31 illustrates how for each oversampling ratio the PCM1804-Q1 device decimates. and a serial interface circuit. The PCM1804-Q1 device can output the signal directly from the modulators to DSDL (pin 16) and DSDR (pin 15). Texas Instruments Incorporated 15 .5 2.PCM1804-Q1 www. Figure 29. The PCM1804-Q1 device also has a DSD output mode.1 0.com SLES271A – JUNE 2012 – REVISED AUGUST 2012 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) HIGH-PASS FILTER (HPF) FREQUENCY RESPONSE STOP-BAND CHARACTERISTICS 0 −10 −20 −30 Amplitude − dB −40 −50 −60 −70 −80 −90 −100 0.0 3. An on-chip.8 0.0 G029 Normalized Frequency − y fS/1000 Normalized Frequency − y fS/1000 Figure 28. and ×32 oversampling rates according to the overasmpling ratio control.0 0. The input signal is sampled at ×128.0 1. The DC components of the signal are removed by the HPF. a decimation filter with a high-pass filter. PRINCIPLES OF OPERATION THEORY OF OPERATION The PCM1804-Q1 device consists of a band-gap reference.6 −0. Full-differential architecture provides a wide dynamic range and excellent power-supply rejection performance. the modulator outputs down to PCM data when the modulator is running at 6.0 0.5 3. OSR[0:2].4 −0. dual rate.5 4.2 0.0 −1. which provides flexible serial formats as well as master and slave modes. The deltasigma modulation randomizes the modulator outputs and reduces the idle-tone level. Figure 30 illustrates the total architecture of the PCM1804-Q1 device.5 1. 24-bit digital signal.4 G028 0.2 PASS-BAND CHARACTERISTICS −0.0 2. high-precision reference with 10-μF external capacitor(s) provides all the reference voltage needed in the PCM1804-Q1 device. while removing high-frequency noise components using a decimation filter. ×64.0 Amplitude − dB 0.

Spectrum of Modulator Output and Decimation Filter 16 Copyright © 2012.ti. Texas Instruments Incorporated .PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www.com PRINCIPLES OF OPERATION (continued) OSR0 SCKI CLK Control OSR1 OSR2 VINL+ VINL− VCOML AGNDL VREFL Delta-Sigma Modulator (L) Decimation Filter (L) HPF S/M FMT0 FMT1 VREFL Serial Output Interface VREFR LRCK/DSDBCK BCK/DSDL DATA/DSDR VREFR AGNDR VCOMR VINR+ VINR− Delta-Sigma Modulator (R) Decimation Filter (R) HPF OVFL OVFR BYPAS Power Supply RST VCC AGND DGND VDD B0029-01 Figure 30. Total Block Diagram of the PCM1804-Q1 Device 0 Quad-Rate Filter −20 −40 Amplitude − dB Dual-Rate Filter −60 −80 −100 −120 −140 −160 0 48 96 f − Frequency − kHz G030 SingleRate Filter Modulator 144 192 Figure 31.

System Clock Input Timing POWER-ON AND RESET FUNCTIONS The PCM1804-Q1 device has both an internal power-on-reset circuit and RST (pin 19). HIGH System clock pulse duration. The clock(s) must be supplied until the power-down sequence completes. the PCM1804-Q1 device stays in the reset state and the digital output is forced to zero. and OSR0 (pin 9) as shown in Table 1 and Table 2. or RST = low. OSR0 (pin 9). where fS is the audio sampling frequency. RST accepts external forced reset. Because an internal pulldown resistor terminates RST. the system clock must be supplied as soon as power is supplied. and RST = high. OSR1 (pin 10). Figure 35 illustrates the digital output for power-on reset and RST control. OSR1. POWER-DOWN FUNCTION The PCM1804-Q1 device has a power-down feature that is controlled by RST (pin 19). OVERSAMPLING RATIO The oversampling ratio is selected by OSR2 (pin 11). initialization (reset) is performed automatically at the time when the digital power supply exceeds 2 V (typical) and analog power supply exceeds 4 V (typical). and 768 fS as a system clock. Because the system clock is used as a clock signal for the reset circuit. at least three system clocks are required prior to VDD > 2 V. In DSD mode. 192 fS (only in master mode at quad rate). The system clock must be supplied on SCKI (pin 18). and the system clock frequency are fixed as shown in Table 1 and Table 3. In slave mode. The PCM1804-Q1 device needs RST to equal low when logic levels on the OSR2.com SLES271A – JUNE 2012 – REVISED AUGUST 2012 PRINCIPLES OF OPERATION (continued) SYSTEM CLOCK INPUT The PCM1804-Q1 device supports 128 fS. Texas Instruments Incorporated 17 .VCC > 4 V (typical) and RST = high. and a low level on RST initiates the reset sequence.8 V T0005B07 tw(SCKH) tw(SCKL) PARAMETER System clock pulse duration. LRCK. Figure 33 and Figure 34 illustrate the internal power-onreset and external-reset timing. Copyright © 2012. and BCK are changed. In master mode. In the master mode. 256 fS. no connection of RST is equivalent to a low-level input. OSR2 (pin 11). LOW MIN 11 11 UNIT ns ns Figure 32. OSR1 (pin 10). and Figure 32 shows system clock timing. the PCM1804-Q1 device starts the reset-release sequence described in the PowerOn and Reset Functions section. 512 fS. the SCKI (pin 18) is used as the clock signal for the power-down counter. OSR1 (pin 10). While in the slave mode.PCM1804-Q1 www. the system clock rate is automatically detected.ti. tw(SCKH) tw(SCKL) SCKI 2V SCKI 0. Entering the power-down mode is done by keeping the RST input level low for more than 65536 / fS. As soon as RST goes high. and OSR0 pins are changed. The digital output is valid after the reset state is released and the time of 1116 / fS has passed. SCKI (pin 18) and LRCK (pin 17) are used as the clock signal. Table 3 shows the relationship of typical sampling frequency and the system clock frequency. The PCM1804-Q1 needs RST = low when control pins are changed or in slave mode when SCKI. VCC < 4 V (typical). VCC > 4 V. 384 fS. While VDD < 2 V (typical). For internal power-on reset. and OSR0 (pin 9) as shown in Table 1. and 1 / fS (maximum) count after VDD > 2 V (typical). respectively. the system clock rate is selected by OSR2 (pin 11). more specifically.

Sampling Frequency and System Clock Frequency OVERSAMPLING RATIO SAMPLING FREQUENCY (kHz) 32 Single rate (2) 44.288 22.576 – 192 fS – – – – – 33.9344 512 fS 16. Modulator is running at 32 fS.9344 18. Oversampling Ratio in Slave Mode OSR2 Low Low Low Low High High High High (1) OSR1 Low Low High High Low Low High High OSR0 Low High Low High Low High Low High OVERSAMPLING RATIO Single rate (× 128 fS) Dual rate (× 64 fS) Quad rate (× 32 fS) (1) Reserved Reserved Reserved Reserved Reserved SYSTEM CLOCK RATE Automatically detected Automatically detected Automatically detected – – – – – Only at the 128-fS system clock rate Table 3. 18 Copyright © 2012.576 – – – – – 768 fS 24.432 33.384 22.5792 24.ti.8688 36. Modulator is running at 64 fS.1 SYSTEM CLOCK FREQUENCY (MHz) 128 fS – – – – – 22. Oversampling Ratio in Master Mode OSR2 Low Low Low Low High High High High High High OSR1 Low Low High High Low Low High High Low Low OSR0 Low High Low High Low High Low High Low High OVERSAMPLING RATIO Single rate (× 128 fS) Single rate (× 128 fS) Single rate (× 128 fS) Single rate (× 128 fS) Dual rate (× 64 fS) Dual rate (× 64 fS) Quad rate (× 32 fS) Quad rate (× 32 fS) DSD mode (× 64 fS) DSD mode (× 64 fS) SYSTEM CLOCK RATE 768 fS 512 fS 384 fS 256 fS 384 fS 256 fS 192 fS 128 fS 384 fS 256 fS Table 2.864 – (1) 256 fS 8.1 48 Dual rate (3) Quad rate (4) DSD mode (3) (1) (2) (3) (4) 88.864 – – – – – Only available in master mode at the quad rate Modulator is running at 128 fS.5792 24.2896 12. Texas Instruments Incorporated .4 192 44.864 – – 16.8688 36.288 16. 2896 384 fS 12.5792 24.576 33.com Table 1.192 11.2 96 176.PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www.8688 36.576 – – 11.

ADC Digital Output for Power-On-Reset and RST Control Copyright © 2012.ti. VDD 4.4 V / 2. DSDL is also controlled like DSDR. The HPF transient response appears initially. External-Reset Timing Power ON RST ON Reset Removal Internal Reset Reset 1116/fS Ready / Operation Data(1) Zero Data Converted Data(2) T0051-01 (1) (2) In the DSD mode.6 V / 1.PCM1804-Q1 www.2 V 4V/2V 3. Internal Power-On-Reset Timing RST t(RST) RST Pulse Duration (t(RST)) = 40 ns (Min) Reset Internal Reset 1/fS (Max) System Clock T0015-05 Reset Removal Figure 34. Texas Instruments Incorporated 19 . Figure 35.com SLES271A – JUNE 2012 – REVISED AUGUST 2012 VCC.8 V Reset Internal Reset Reset Removal 1024 System Clock + 1/fS (Max) System Clock T0014-07 Figure 33.

PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www. 24-bit PCM. and DATA/DSDR (pin 15).ti. the PCM1804-Q1 device receives the timing for data transfer from an external controller. The PCM1804-Q1 device needs RST to equal low in the interface mode and/or if the data format is changed. Interface Mode S/M Low High MODE Master mode Slave mode DATA FORMAT The PCM1804-Q1 device supports four audio data formats in both master and slave modes. I S. 24-bit DSD MASTER Yes Yes Yes Yes SLAVE Yes Yes Yes – 20 Copyright © 2012. LRCK/DSDBCK (pin 17). While in slave mode. Data Format FMT1 Low Low High High FMT0 Low High Low High 2 FORMAT PCM. standard. Slave mode is not available for DSD. In master mode. 24-bit PCM. which are selected by S/M (pin 8) as shown in Table 4. Table 4. the PCM1804-Q1 device provides the timing of the serial audio data communications between the PCM1804-Q1 device and the digital audio processor or external circuit.com AUDIO DATA INTERFACE The PCM1804-Q1 device interfaces the audio system through BCK/DSDL (pin 16). INTERFACE MODE The PCM1804-Q1 device supports master mode and slave mode as interface modes. and these data formats are selected by FMT0 (pin 6) and FMT1 (pin 7) as shown in Table 5. Texas Instruments Incorporated . Table 5. left-justified.

ti. Audio Data Format for PCM Copyright © 2012.PCM1804-Q1 www. Texas Instruments Incorporated 21 .com SLES271A – JUNE 2012 – REVISED AUGUST 2012 INTERFACE TIMING FOR PCM Figure 36 through Figure 38 show the interface timing for PCM. R-Channel = Low 1/fS LRCK BCK DATA 1 2 3 22 23 24 1 2 3 22 23 24 1 2 L-Channel R-Channel (2) I2S Data Format. L-Channel = Low. Figure 36. L-Channel = High. R-Channel = High 1/fS LRCK BCK DATA 1 2 3 22 23 24 1 2 3 22 23 24 1 2 L-Channel R-Channel (3) Standard Data Format. (1) Left-Justified Data Format. R-Channel = Low 1/fS LRCK BCK DATA 22 23 24 1 2 3 22 23 24 1 2 3 22 23 24 T0009-03 L-Channel R-Channel NOTE: LRCK and BCK work as outputs in master mode and as inputs in slave mode. L-Channel = High.

ti. The load capacitance of all signals is 10 pF.PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www.5 VDD T0018-03 PARAMETERS t(BCKP) tw(BCKH) tw(BCKL) t(CKLR) t(LRCP) t(CKDO) t(LRDO) tr tf (1) (2) (3) BCK period BCK pulse duration.5 VDD BCK t(BCKP) t(CKDO) t(LRDO) 0.com t(LRCP) LRCK tw(BCKL) tw(BCKH) t(CKLR) 0. The t(BCKP) is fixed at 1 / (64 fS) in case of master mode. LOW Delay time.5 VDD DATA 0. Texas Instruments Incorporated . BCK falling edge to LRCK valid LRCK period Delay time. HIGH BCK pulse duration. MIN 32 32 –5 TYP 1 / (64 fS) MAX UNIT ns ns 15 1 / fS 15 15 10 10 ns ns ns ns ns –5 –5 Figure 37. BCK falling edge to DATA valid Delay time. LRCK edge to DATA valid Rising time of all signals Falling time of all signals Rising and falling times are measured from 10% to 90% of IN/OUT signal swing. Audio Data Interface Timing for PCM (Master Mode: LRCK and BCK Work as Outputs) 22 Copyright © 2012.

PCM1804-Q1 www. MIN 1 / (64 fS) 32 32 12 12 TYP MAX 1 / (48 fS) UNIT ns ns ns ns 1 / fS 5 5 25 25 10 10 ns ns ns ns Figure 38. HIGH BCK pulse duration. BCK falling edge to DATA valid Delay time.com SLES271A – JUNE 2012 – REVISED AUGUST 2012 t(LRCP) LRCK tw(BCKL) tw(BCKH) t(LRHD) 1. Audio Data Format Copyright © 2012.ti. LOW LRCK setup time to BCK rising edge LRCK hold time to BCK rising edge LRCK period Delay time. Texas Instruments Incorporated 23 . The load capacitance of the DATA /DSDR signal is 10 pF.4 V t(BCKP) t(CKDO) t(LRDO) t(LRSU) 1. DSDBCK DSDL Dn−3 Dn−2 Dn−1 Dn Dn+1 Dn+2 Dn+3 DSDR Dn−3 Dn−2 Dn−1 Dn Dn+1 Dn+2 Dn+3 T0052−01 Figure 39. Audio Data Interface Timing for PCM (Slave Mode: LRCK and BCK Work as Inputs) INTERFACE TIMING FOR DSD Figure 39 and Figure 40 show the interface timing for DSD.4 V BCK DATA 0. LRCK edge to DATA valid Rising time of all signals Falling time of all signals Rising and falling times are measured from 10% to 90% of IN/OUT signals swing.5 VDD T0017-03 PARAMETERS t(BCKP) tw(BCKH) tw(BCKL) t(LRSU) t(LRHD) t(LRCP) t(CKDO) t(LRDO) tr tf (1) (2) BCK period BCK pulse duration.

synchronization loss never occurs. Figure 41shows the ADC digital output for loss of synchronization and resynchronization. In master mode. LOW Delay time DSDBCK falling edge to DSDL. and DSDR signal is 10 pF. HPF Bypass Control BYPAS PIN Low High HPF MODE Normal (high-pass) mode Bypass (through) mode 24 Copyright © 2012. the PCM1804-Q1 device may generate some noise in the audio signal. the DC component of the input analog signal and the internal DC offset are also converted and output in the digital output data.com tw(BCKH) tw(BCKL) t(CKDO) DSDBCK t(BCKP) 0. The load capacitance of the DSDBCK. Also. In bypass mode. Texas Instruments Incorporated . The PCM1804-Q1 device does not need a specific phase relationship between LRCK and SCKI. the PCM1804-Q1 device operates under LRCK synchronized with the system clock SCKI. HIGH DSDBCK pulse duration.ti. the transition of normal to undefined data and undefined or zero data to normal causes a discontinuity of data on the digital output. Audio Data Interface Timing for DSD (Master Mode Only) SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM FOR PCM In slave mode. HIGH-PASS FILTER (HPF) BYPASS CONTROL FOR PCM The built-in function for DC component rejection can be bypassed by the BYPAS (pin 12) control. For changes less than ±5 BCK. but it does require the synchronization of LRCK and SCKI.5 VDD DSDL DSDR 0.PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www. If the relationship between LRCK and SCKI changes more than ±6 BCK during one sample period due to LRCK or SCKI jitter. DSDR valid Rising time of all signals Falling time of all signals Rising and falling times are measured from 10% to 90% of IN/OUT signal swing. internal operation of the ADC halts within 1 / fS and digital output is forced into BPZ code until resynchronization between LRCK and SCKI is completed.5 VDD T0053−01 PARAMETERS t(BCKP) tw(BCKH) tw(BCKL) t(CKDO) tr tf (1) (2) DSDBCK period DSDBCK pulse duration. resynchronization does not occur and the previously described digital output control and discontinuity do not occur. During undefined data. DSDL. Table 6. MIN TYP 354 177 177 MAX UNIT ns ns ns –5 15 10 10 ns ns ns Figure 40. This can generate noise in the audio signal.

016 s at maximum. ADC Digital Output for Loss of Synchronization and Resynchronization Copyright © 2012.ti. The high level is held for 1.PCM1804-Q1 www. The HPF transient response appears initially.com SLES271A – JUNE 2012 – REVISED AUGUST 2012 OVERFLOW FLAG FOR PCM The PCM1804-Q1 device has two overflow flag pins. Synchronization Lost Resynchronization State of Synchronization Synchronous Asynchronous Synchronous 1/fS DATA(1) Normal Data Undefined Data 90/fS Zero Data Converted Data(2) T0020-06 (1) (2) Applies only for slave mode. Figure 41. OVFR (pin 20) and OVFL (pin 21). Texas Instruments Incorporated 25 . The pins go to high as soon as the analog input goes across the full-scale range. and returns to low if the analog input does not go across the full-scale range for the period. the loss of synchronization never occurs in master mode.

Texas Instruments Incorporated . Typical Circuit Connection Diagram for PCM 26 Copyright © 2012. C4: Bypass capacitor. 0. PCM1804 C1 + 1 2 AGNDL C3 + 3 VCOML 4 + L-Channel In − 6 FMT0 Format [1:0] 7 FMT1 8 Master/Slave 9 Control Oversampling Ratio [2:0] 10 11 12 HPF Bypass 13 3.1-μF ceramic and 10-μF tantalum. and C6: Bypass capacitors. depending on layout and power supply Figure 42. depending on layout and power supply C3.PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www.1-μF tantalum.ti.3 V C5 + 14 VDD DATA/DSDR S/M OSR0 OSR1 OSR2 BYPAS DGND OVFL OVFR RST SCKI LRCK/DSDBCK BCK/DSDL VCC AGND 5 VINL+ VINL− VINR+ VINR− VCOMR AGNDR VREFL VREFR C2 28 + 27 C4 26 + 25 + 24 − 23 C6 22 21 20 19 Reset 18 17 L/R Clock 16 Data Clock 15 Data Out Audio Data Processor System Clock Overflow 5V + R-Channel In S0058-01 A.com TYPICAL CIRCUIT CONNECTION DIAGRAM Figure 42 shows a typical circuit connection diagram in the PCM data format operation. 0. C1. C2. B. C5.

com SLES271A – JUNE 2012 – REVISED AUGUST 2012 Figure 43 shows a typical circuit connection diagram in the DSD data format operation. 0.1-μF ceramic and 10-μF tantalum. depending on layout and power supply Figure 43. 0.PCM1804-Q1 www.1-μF tantalum. C1.3 V C5 + 14 VDD DATA/DSDR S/M OSR0 OSR1 OSR2 BYPAS DGND OVFL OVFR RST SCKI LRCK/DSDBCK BCK/DSDL VCC AGND 5 VINL+ VINL− VINR+ VINR− VCOMR AGNDR VREFL VREFR C2 28 + 27 C4 26 + 25 + 24 − 23 C6 22 21 20 19 Reset 18 17 Data Clock 16 L-Channel Data Out 15 R-Channel Data Out Audio Data Processor System Clock Overflow 5V + R-Channel In S0058-02 A. B. Typical Circuit Connection Diagram for DSD Copyright © 2012. C5. Texas Instruments Incorporated 27 . depending on layout and power supply C3 and C4: Bypass capacitors. and C6: Bypass capacitors. C2. PCM1804 C1 + 1 2 AGNDL C3 + 3 VCOML 4 + L-Channel In − 6 FMT0 Format [1:0] 7 FMT1 8 Master/Slave 9 Control Oversampling Ratio [2:0] 10 11 12 HPF Bypass 13 3.ti.

to ensure low source impedance at ADC references. using one common power supply is recommended to avoid unexpected power-supply trouble like latch-up or the power-supply sequence. Locating the buffer near the PCM1804-Q1 device and minimizing the load capacitance. Texas Instruments Incorporated . VIN Pins Using 0. rightchannel analog common-mode voltage and corresponding analog ground pins to ensure low source impedance of common voltage. APPLICATION CIRCUIT FOR SINGLE-ENDED INPUT An application diagram for a single-ended input circuit is shown in Figure 44. Although the PCM1804-Q1 device has two power lines to maximize the potential of dynamic performance. Also. an external reset control with a delay time corresponding to the left-channel voltage reference output and right-channel voltage reference output response is required.1-μF ceramic and 10-μF tantalum capacitors placed as close to the pins as possible to maximize the dynamic performance of the ADC. it might be necessary to consider the system clock duty. Therefore. it works as a power-down control. System Clock The quality of the system clock can influence dynamic performance because the PCM1804-Q1 device operates based on a system clock. jitter. right-channel voltage reference output. The DC voltage level of these pins is 2. rightchannel voltage reference output.3. BCK/DSDL.1-μF tantalum capacitors between left-channel analog common-mode voltage. minimizes the digitalanalog crosstalk and maximizes the dynamic performance of the ADC. DATA/DSDR.com APPLICATION INFORMATION BOARD DESIGN AND LAYOUT CONSIDERATIONS VCC and VDD Pins The digital and analog power supply lines to the PCM1804-Q1 device should be bypassed to the corresponding ground pins with 0. These capacitors should be located as close as possible to the left-channel voltage reference output. BCK/DSDL. The maximum signal input voltage and differential gain of this circuit is designed as Vin(max) = 8. and the time difference between system clock transition and BCK/DSDL or LRCK/DSDBCK transition in slave mode.1-μF ceramic and 10-μF tantalum capacitors between the left-channel voltage reference output.01-μF film capacitors between the left-channel analog input positive pin and left-channel analog input negative pin.5 V.PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www. Differential gain (Ad) is given by R3 / R1(R4 / R2) in a circuit configured as a normal inverted-gain amplifier. The circuit technique using R5 (R6) is recommended. and corresponding analog ground pins. 28 Copyright © 2012. and LRCK/DSDBCK Pins The DATA/DSDR.ti. Resistor R5 (R6) in the feedback loop gives low-impedance drive operation and noise filtering for the analog input of the PCM1804-Q1 device. VREFX and VCOMX Inputs Use 0. Use 0. Ad = 0. and LRCK/DSDBCK pins in master mode have large load drive capability. and between right-channel analog input positive pin and right-channel analog input negative pin is strongly recommended to remove higher-frequency noise from the delta-sigma input section. left-channel analog common-mode voltage.28 Vpp. and rightchannel analog common-mode voltage pins to reduce dynamic errors on references and common voltage. Reset Control If capacitors larger than 10 μF are used on left-channel voltage reference output and right-channel voltage reference output.

In that case. Application Circuit for Single-Ended Input Circuit (PCM) VIN+ VIN− ∆Σ Modulator _ BGR + VCOM VREF _ + S0060-01 Figure 45. Texas Instruments Incorporated 29 .1 µF R4 = 1 kΩ C(1) 10 µF + + OPA2134 1/2 S0059-01 C(1) PCM1804 R1 = 3.ti.PCM1804-Q1 www.01 µF R2 = 3. Equivalent Circuit of Internal Reference (VCOM.3 kΩ _ R6 = 47 Ω VIN+ (1) A capacitor value of 1800 pF is recommended.com SLES271A – JUNE 2012 – REVISED AUGUST 2012 R3 = 1 kΩ 4. VREF) Copyright © 2012. unless an input signal greater than –6 dBFS at 100 kHz or higher is applied in the DSD mode.7 kΩ 4.3 kΩ _ R5 = 47 Ω VIN− 0. Figure 44.7 kΩ Analog In _ + OPA2134 1/2 10 µF + + OPA2134 1/2 VCOM 0. 3300 pF is recommended.

........................................................... ............................................ti...........................com REVISION HISTORY Changes from Original (June 2012) to Revision A • • Page Changed part number from PCM1804-ME to PCM1804-Q1.. ............ 1 Added table note under recommended operating conditions table............ 4 30 Copyright © 2012.PCM1804-Q1 SLES271A – JUNE 2012 – REVISED AUGUST 2012 www............... Texas Instruments Incorporated ..............

and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.com 5-Nov-2012 PACKAGING INFORMATION Orderable Device PCM1804S1IDBRQ1 (1) Status (1) Package Type Package Pins Package Qty Drawing SSOP DB 28 2000 Eco Plan (2) Lead/Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) ACTIVE TBD Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.please check http://www. and a lifetime-buy period is in effect. -. TI Pb-Free products are suitable for use in specified lead-free processes. Device is in production to support existing customers. LIFEBUY: TI has announced that the device will be discontinued.com/productcontent for the latest availability information and additional product content details. and peak solder temperature. NRND: Not recommended for new designs.ti. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances. Samples may or may not be available. and thus CAS numbers and other limited information may not be available for release.1% by weight in homogeneous materials. and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.1% by weight in homogeneous material) (3) MSL. Peak Temp. Pb-Free (RoHS Exempt). TI and TI suppliers consider certain information to be proprietary.ti. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. including the requirement that lead not exceed 0.The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications. or Green (RoHS & no Sb/Br) . Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible). or 2) lead-based die adhesive used between the die and leadframe. OTHER QUALIFIED VERSIONS OF PCM1804-Q1 : • Catalog: PCM1804 NOTE: Qualified Version Definitions: • Catalog . Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TBD: The Pb-Free/Green conversion plan has not been defined. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. (2) Eco Plan . PREVIEW: Device has been announced but is not in production.PACKAGE OPTION ADDENDUM www. TI bases its knowledge and belief on information provided by third parties.TI's standard catalog product Addendum-Page 1 . Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package. but TI does not recommend using this part in a new design. Where designed to be soldered at high temperatures.The planned eco-friendly classification: Pb-Free (RoHS). OBSOLETE: TI has discontinued the production of the device.

D.90 9. This drawing is subject to change without notice.50 10.50 12.25 0.55 Seating Plane 2.00 8.05 MIN 0.MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN 0. B. C. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS.90 5.65 28 0.15.90 9.00 MAX 0.95 0.90 12.60 5.50 7.30 4040065 /E 12/01 NOTES: A.90 6.15 M PLASTIC SMALL-OUTLINE 0.50 8.38 0.20 7.09 5.90 7.40 Gage Plane 1 A 14 0°–ā8° 0.25 0.50 6.10 PINS ** DIM A MAX 14 16 20 24 28 30 38 6.50 10. All linear dimensions are in millimeters. TEXAS 75265 . Body dimensions do not include mold flash or protrusion not to exceed 0.90 A MIN 5.22 15 0.

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