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DOC/LP/01/21.01.05 LP EC2354 LESSON PLAN LP Rev.

. No: 01 Date: 15/12/11 Sub Code/Name: EC2354-VLSI DESIGN Unit : I Branch : EC Semester: VI Page 01 of 06

UNIT I Syllabus:

CMOS TECHNOLOGY

A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal I-V effects, DC transfer characteristics - CMOS technologies, Layout design Rules, CMOS process enhancements, Technology related CAD issues, Manufacturing issues. Objective: To understand the MOS transistor theory, CMOS technologies and the Layout Session No. 1. 2. 3. 4. 5. Time Topics to be covered Introduction VLSI Design NMOS, PMOS Enhancement transistor MOS transistor-Ideal I-V characteristics MOS transistor-C-V characteristics Non ideal I-V characteristics- velocity saturation and mobility degradation, channel length modulation, sub threshold conduction, Body effect Threshold voltage, Junction leakage, Tunneling, temperature dependence, Geometry dependence CMOS inverter DC characteristics, Beta ratio effects CMOS technology : nwell, P well Twin well, triple well, Layout design rules-NAND,NOR gate CMOS Process enhancement-SOI Process, Interconnects, circuit elements: Resistors Circuit element: capacitor, CAD and manufacturing issues Tutorial CAT-I 50m 50m 50m 50m 50m Page No 1-4 5-7,40 42-45 45-51 51-55 Ref Teaching Method 1 1 1 1 1 BB BB BB BB BB

6. 7. 9. 10. 11. 12. 13.

50m 100m 50m 50m 50m 50m 50m 50m

55-60 60-65 83, 15-21 83-91 91-100 107109,149 -

1 1 1,3 1 1 1,2 1,3 -

BB BB BB, OHP BB,OHP BB BB BB -

DOC/LP/01/21.01.05 LP EC2354 LESSON PLAN LPRev. No: 01 Date: 15/12/11 Sub Code/Name: EC2354-VLSI DESIGN Unit : II Branch : EC Semester: VI Page 02 of 06 UNIT II Syllabus: Delay estimation, Logical effort and Transistor sizing, Power dissipation, Interconnect, Design margin, Reliability, Scaling- SPICE tutorial, Device models, Device characterization, Circuit characterization, Interconnect simulation. Objective: To study the circuit characterization and performance estimation of CMOS technology . Session No. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. Topics to be covered Delay estimation-RC delay model, Linear delay model Logical effort ,Transistor sizing Power dissipation-static and dynamic power Interconnect Estimation of resistance capacitance, delay cross talk delay effects,Design margin Reliability Scaling, SPICE tutorial SPICE tutorial, Device models Device& Circuit characterization Interconnect simulation Tutorial CAT-II Time 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m Page No 111117,245 118,313 129-135 142148,525 145-148 148-159 159,229 181-193 193 -213 193 -213 Ref 1,2 1,2 1 1,2 1 1 1,2 1 1 1 1,3 Teaching Method BB BB BB BB BB BB BB BB BB,OHP BB,OHP BB,OHP CIRCUIT CHARACTERIZATION AND SIMULATION 9

DOC/LP/01/21.01.05 LP EC2354 LESSON PLAN LP Rev. No: 01 Date: 15/12/11 SubCode/Name EC2354 -VLSI DESIGN Unit : III Branch : EC Semester: VI Page 03 of 06

UNIT III 9 Syllabus:

COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN 9

Circuit families Low power logic design comparison of circuit families Sequencing static circuits, circuit design of latches and flip flops, Static sequencing element methodology- sequencing dynamic circuits synchronizers Objective: To Understand the concepts of designing combinational and sequential circuit using CMOS logic configuration Session No. 25. 26. 27. 28. 29. 30. 32. 33. 34. Topics to be covered Circuit families-static CMOS,ratioed circuit Cascode voltage swing logic,Dynamic circuits Pass transistor,Differential circuits BiCMOS,Low power logic design comparison of circuit families Sequencing static circuits Circuit design of latches and flip flops Static sequencing element Sequencing dynamic circuits Synchronizers CAT-III Time 50m 50m 50m 50m 50m 100m 50m 50m 50m 50m Page No 215224,342 225,361 , 353 233-240 241-245 252-265 265-274 275-283 284-289 289-294 Ref 1,2 1,2,3 1 1 1 1 1 1 1 Teaching Method BB BB BB BB BB BB,OHP BB BB BB -

DOC/LP/01/21.01.05
LESSON PLAN Sub Code/Name: EC2354 -VLSI DESIGN Unit : IV Branch : EC Semester: VI LP EC2354 LP Rev. No: 01 Date: 15/12/11 Page 04 of 06

UNIT IV Syllabus:

CMOS TESTING

Need for testing- Testers, Text fixtures and test programs- Logic verificationSilicon debug principles- Manufacturing test Design for testability Boundary scan. Objective: To understand the concepts of CMOS testing

Session No. 35. 36. 37. 38. 39. 41. 42.

Topics to be covered Need for testing Text fixtures and test programs Logic verification-- Silicon debug principle, Manufacturing test Manufacturing test Design for testability-adhoc tesing Scan design Built in self test, IDDQ testing Boundary scan CAT-IV

Time 50m 50m 50m 50m 100m 50m 100m 75m

Page No 531-541 541-547 547549,621,23 9 548-550 550-555 555-558 559-570 -

Ref 1 1 1,2,4 1 1 1 1 -

Teaching Method BB BB BB BB BB BB BB -

DOC/LP/01/21.01.05 LESSON PLAN LP EC2354 SubCode/Name: EC2354 VLSI DESIGN LP Rev. No: 01 Date: 15/12/11 Unit : V Branch : EC Semester: VI Page 05 of 06
UNIT V SPECIFICATION USING VERILOG HDL

Syllabus:Basic concepts- identifiers- gate primitives, gate delays, operators, timing controls,procedural assignments conditional statements, Data flow and RTL, structural gate level,switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches,Structural gate level description of decoder, equality detector, comparator, priorityencoder, half adder, full adder, Ripple carry adder, D latch and D flip flop.
Objective: To understand the concepts of modeling a digital system using Hardware

Description Language.

Session Topics to be covered No. 44. Basic concepts- identifiers- gate primitives,, Design hierarchies 45. Gate delays 46. Operators 47. Chip Timing controls 48. 49. 50. 51. 52. 53. 54. Procedural assignments ,conditional statements Data flow and RTL Structural gate level Switch level modeling Behavioral and RTL modeling, Test benches Gate level verilog code-Decoder, equality detector, comparator, priorityencoder Half adder, full adder, Ripple carry adder, D latch and D flip flop. CAT-V

Time 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m

Page No 4748,72,106,38 8 121 138 171-178 166,179 131 373 383 385 136 452,414 -

Ref 8,2 8 8 8 8 8 8 8 8 8 2,4 -

Teaching Method BB BB BB BB BB BB BB BB BB BB BB -

DOC/LP/01/21.01.05
LESSON PLAN

SubCode/Name: EC2354-VLSI DESIGN Branch : EC Semester: VI Course Delivery Plan: 1 I II 1 1 2 3 4 5 6 7 8 9 10 11 12

LP EC2354 LP Rev. No: 01 Date: 15/12/11 Page 06 of 06

Week

13

14

15

I II I II I II I II I II I II I II I II I II I II I II 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 5 5 2 5
C A T 1 C A T 2 C A T 3 C A T 4

I II I II I II 5 5 5 - - C A T 5

Units

TEXT BOOKS:
1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 2005 2. Uyemura J.P: Introduction to VLSI circuits and systems, Wiley 2002.

REFERENCES:
3. D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 2003 4. Wayne Wolf, Modern VLSI design, Pearson Education, 2003 5. M.J.S.Smith: Application specific integrated circuits, Pearson Education, 1997 6. J.Bhasker: Verilog HDL primer, BS publication,2001 7. Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003 8.Samir palnitkar, Verilog HDL , Pearson Education,second edition

Name Designation Date Signature

Prepared by M.ANUSHYA Asst- professor

Approved by Prof.E.G .Govindan HOD, Department of EC