The purpose of this project is to study the basic functionality of 8085: Take input through DIP switches and produce corresponding output at LEDs using 8085-A, 8255 and EPROM.

Brie f Descri pti on :
The required system offer limited features of 8085 therefore many input pins like SID, TRAP, RST 7.5, RST6.5, RST 5.5, INTR and HOLD are grounded while output pins like INTA,S0, S1, HLDA and SOD are left open. The port A of 8255A is configured as input port so it is connected to the DIP switches from where the input is applied. The port B is configured as output port so connected to LEDs where output is to be displayed. The reset pin of the 8255 is connected to the RESETOUT of the microprocessor. The address pins A0 and A1 of the PPI are connected to the A8 and A9 address pins of the microprocessor because in case of isolated I/O, the address is duplicated on the high order address bus of the microprocessor. The RD and WR signals of the 8255 is connected to the corresponding signals of the microprocessor. Reset circuitry is implemented by using a resistor and a push button. Initially RESETIN pin is grounded i.e. HIGH (because the signal is complemented), so because of this low signal in the beginning microprocessor is reset. As soon as the switch is pressed HIGH will appear on the RESETIN pin.

Components Used:
         8085A microprocessor 8255A Programmable Peripheral Interface EEPROM 2764A 74LS373 (Latch) 7400 (NAND gate) Dip switches LEDs Quartz Crystal (6MHZ) Capacitor (10 micro farad)

Microprocessor Based System

2  Resistors (1 k ohm, 75 k ohm)

Intel 8085 microprocessor is the next generation of Intel 8080. In addition to being faster than the 8080, the 8085 had the following enhancements
• • •

Single 5V power supply. On-chip integrated peripherals: clock oscillator and system controller. New instructions, most of them were undocumented.

INTEL 8085 MICROPROCESSOR’S ARCHITECTURE Program memory - program can be located anywhere in memory. Jump, branch and
call instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB. All jump/branch instructions use absolute addressing.

The processor has 5 interrupts. They are presented below in the order of their priority (from lowest to highest):

One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction).

RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 2Ch (hexadecimal) address.

RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 34h (hexadecimal) address.

RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the
contents of the PC register into stack and branches to 3Ch (hexadecimal) address.

I/O ports
256 Input ports 256 Output ports

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These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need

Microprocessor Based System

4 for inter-face or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM74LS373 are transparent D-type latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the highimpedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.

8255A PPI
The 8255A is a programmable peripheral interface (PPI) device designed for use in Intel microcomputer systems. Its function is that of a general purposes I/O component to Interface peripheral equipment to the microcomputer system bush. The functional configuration of the 8255A is programmed by the systems software so that normally no external logic is necessary to interface peripheral devices or structures.

Pin Configuration:
D0 – D7 RESET CS RD WR A0 , A1 PA0 – PA7 PB0 – PB7 PC0 – PC7 Data Bus Reset Input Chip Select Read Input Write Input Port Address Port A Port B Port C

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Pin Diagram:

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MVI A, 90 OUT 03 IN 00 OUT 01 JMP 0004 3E 90 D3 03 DB 00 D3 01 C3 04 00

When RESET IN pin of the 8085A is made logic ‘0’, the PC is reset to ‘00000000’, when the RESET IN pin is returned to logic ‘1’, the CU transfers the contents of PC to the address latch, providing the address of the first instruction to be executed. Here in this system we have provided push button switch to control the logic. When push button switch is pressed, the program execution in the 8085A begins with the first instruction in memory location 00H; the first instruction is OF, hence opcode is transferred from memory (EPROM 2764) to IR of the microprocessor. During state T1 microprocessor loads the address in (AD0-AD7) and replica at (A8-A15) with the memory address or I/O address, here IO/M=0 hence memory is referenced. Now AD 0-AD7 is loaded with the address of the D0-D7 of EPROM. The first function is MVI A,90, this instruction is concerned to the internal of 8085A, 90 is loaded in accumulator, hence A=10010000. Next instruction is OUT 03; this generate I/O signal 1 which disable the memory and enable the 8255 (IO/M signal makes 8255 CS enable through inverter). Hence 8255 is selected. The port address is 03 i.e. ‘00000011’, this configure the 8255 as: Port A  Input Port B  Output Port C  Don’t care since the control word is 90 i.e. ‘’10010000’.

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7 Once 8085A is configured the microprocessor loads another instruction by placing ‘0’ at IO/M. The next instruction is IN 00, i.e. the data placed at Port A is internally latched at data bus of 8255 and then transferred to 8085A through latch (74573) which is then transferred to accumulator register; refer to Port B of 8255, since it is being configured as output port hence the data is transferred to Port B from accumulator. The sequence of IO/M is same as that of the above instruction. Now the next instruction is JMP which jumps to the instruction IN 00, hence program is executed in the same fashion described above.

Microprocessor Based System


Microprocessor Based System