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Recent developments in power electronics, fast digital signal processors (DSPs) and modern control technologies have significantly influenced the wide spread use of permanent magnet brushless (BLDC) motor  drives in order to meet the competitive worldwide market demands of manufactured goods, devices, products and processors. Large, medium, small as well as micro BLDC motors are extensively sought for applications in all sorts of motion control  apparatus and systems. The availability of smart power electronics devices and their optimal topologies has accelerated unprecedented growth of cost effective and reliable inverter and converter systems. Software controlled online implementation of sophisticated robust controllers has advanced the art of digital control of BLDC motor drives.
In electric traction, like in other applications, a wide range in speed and torque control for the electric motor is desired. The DC machine fulfils these requirements but these machines needs periodic maintenance. The AC machines like induction motors and brushless DC  motor does not have brushes, and their rotors are robust because commutator and or rings do not exist. That means very low maintenance. This also increases the power to weight ratio and efficiency. For induction motors flux control has been developed, which offers a high dynamic performance for electric traction application however this control type is complex and sophisticated.
The development of BLDC has permitted an important simplification in the hardware for electric traction control. The term Brushless DC motor  is used to identify the combination of AC machine, solid state inverter and rotor position sensor that results in a drive system having a linear torque – speed characteristic as in an conventional DC machine High efficiency due to reduced losses, low maintenance and low rotor inertia of the BLDC motor have increased the demand of BLDC motors in high power servo and robotic applications.
AMC Engineering College | Dept. of EEE
CONTROL OF BLDC MOTOR USING dsPIC30F2010
The invention of modern solid state devices like MOSFET, IGBT and high energy have widely enhanced the applications of BLDC motors in variable speed drives. In this work, a digital controller is developed for this drive which uses minimum number of components employing a recently introduced DSP (dsPIC0F2010) by Microchip for power electronics applications. First the control scheme of the drive is analysed and its simulated results are validated with test results obtained from developed digital controller.
AMC Engineering College | Dept. of EEE
CONTROL OF BLDC MOTOR USING dsPIC30F2010
BRUSHLESS DC MOTOR FUNDAMENTALS
Brushless Direct Current (BLDC) motors are one of the motor types rapidly gaining popularity. BLDC motors are used in industries such as Appliances, Automotive, Aerospace, Consumer, Medical, Industrial Automation Equipment and Instrumentation.
As the name implies, BLDC motors do not use brushes for commutation; instead, they are electronically commutated. BLDC motors have many advantages over brushed DC motors and induction motors. A few of these are:
• • • • • •
Better speed versus torque characteristics High dynamic response High efficiency Long operating life Noiseless operation Higher speed ranges
In addition, the ratio of torque delivered to the size of the motor is higher, making it useful in applications where space and weight are critical factors. In this application note, we will discuss in detail the construction, working principle, characteristics and typical applications of BLDC motors.
2.2 Construction and Operating Principle
BLDC motors are a type of synchronous motor. This means the magnetic field generated by the stator and the magnetic field generated by the rotor rotates at the same frequency. BLDC motors do not experience the “slip” that is normally seen in induction motors.
AMC Engineering College | Dept. of EEE
CONTROL OF BLDC MOTOR USING dsPIC30F2010
BLDC motors come in single-phase, 2-phase and 3-phase configurations. Corresponding to its type, the stator has the same number of windings. Out of these, 3-phase motors are the most popular and widely used. This application note focuses on 3-phase motors
The stator of a BLDC motor consists of stacked steel laminations with windings placed in the slots that are axially cut along the inner periphery. Traditionally, the stator resembles that of an induction motor; however, the windings are distributed in a different manner. Most BLDC motors have three stator windings connected in star fashion. Each of these windings is constructed with numerous coils interconnected to form a winding. One or more coils are placed in the slots and they are interconnected to make a winding. Each of these windings is distributed over the stator periphery to form an even numbers of poles.
FIGURE 1: STATOR OF A TYPICAL BLDC MOTOR
There are two types of stator windings variants: Trapezoidal motors Sinusoidal motors
This differentiation is made on the basis of the interconnection of coils in the stator windings to give the different types of back Electromotive Force (EMF). As their names
AMC Engineering College | Dept. of EEE Page 4
CONTROL OF BLDC MOTOR USING dsPIC30F2010
indicate, the trapezoidal motor gives a back EMF in trapezoidal fashion and the sinusoidal motor’s back EMF is sinusoidal, as shown in Figure 1 and Figure 2. In addition to the back EMF, the phase current also has trapezoidal and sinusoidal variations in the respective types of motor. This makes the torque output by a sinusoidal motor smoother than that of a trapezoidal motor. However, this comes with an extra cost, as the sinusoidal motors take extra winding interconnections because of the coils distribution on the stator periphery, thereby increasing the copper intake by the stator windings. Depending upon the control power supply capability, the motor with the correct voltage rating of the stator can be chosen. Forty-eight volts, or less voltage rated motors are used in automotive, robotics, small arm movements and so on. Motors with 100 volts, or higher ratings, are used in appliances, automation and in industrial applications.
TRAPEZOIDAL BACK EMF
AMC Engineering College | Dept. of EEE
the proper magnetic material is chosen to make the rotor.CONTROL OF BLDC MOTOR USING dsPIC30F2010 SINUSOIDAL BACK EMF 2. rare earth alloy magnets are gaining popularity.2. Ferrite magnets are traditionally used to make permanent magnets. The ferrite magnets are less expensive but they AMC Engineering College | Dept. of EEE Page 6 .2 Rotor FIGURE 2: ROTOR OF A TYPICAL BLDC MOTOR The rotor is made of permanent magnet and can vary from two to eight pole pairs with alternate North (N) and South (S) poles. As the technology advances. Based on the required magnetic field density in the rotor.
CONTROL OF BLDC MOTOR USING dsPIC30F2010 have the disadvantage of low flux density for a given volume.3 Hall Sensors Unlike a brushed DC motor. the stator windings should be energized in a sequence. indicating the N or S pole is passing near the sensors. Rotor position is sensed using Hall Effect sensors embedded into the stator. In contrast. the commutation of a BLDC motor is controlled electronically. they give a high or low signal. Ferrite and Boron (NdFeB) are some examples of rare earth alloy magnets. the exact sequence of commutation can be determined. the alloy material has high magnetic density per volume and enables the rotor to compress further for the same torque. these alloy magnets improve the size-to-weight ratio and give higher torque for the same size motor using ferrite magnets. FIGURE  ROTOR VARIANTS 2. Neodymium (Nd). Continuous research is going on to improve the flux density to compress the rotor further. Whenever the rotor magnetic poles pass near the Hall sensors. Also. AMC Engineering College | Dept. Samarium Cobalt (SmCo) and the alloy of Neodymium. of EEE Page 7 . Most BLDC motors have three Hall sensors embedded into the stator on the non-driving end of the motor. It is important to know the rotor position in order to understand which winding will be energized following the energizing sequence. Figure below shows cross sections of different arrangements of magnets in a rotor. To rotate the BLDC motor. Based on the combination of these three Hall sensor signals.
there are two versions of output. Hall sensors are embedded into the stationary part of the motor. These are a scaled down replica version of the rotor. to align with the rotor magnets. whenever the rotor rotates. with respect to the rotor magnets. The Hall sensors may be at 60° or 120° phase shift to each other. the motor manufacturer defines the commutation sequence. AMC Engineering College | Dept. in addition to the main rotor magnets. the Hall sensor magnets give the same effect as the main magnets. Embedding the Hall sensors into the stator is a complex process because any misalignment in these Hall sensors. which should be followed when controlling the motor.CONTROL OF BLDC MOTOR USING dsPIC30F2010 FIGURE 4: HALL SENSORS Above figure shows a transverse section of a BLDC motor with a rotor that has alternate N and S permanent magnets. This enables users to adjust the complete assembly of Hall sensors. Based on this. some motors may have the Hall sensor magnets on the rotor. Based on the physical position of the Hall sensors. The Hall sensors are normally mounted on a PC board and fixed to the enclosure cap on the non-driving end. To simplify the process of mtounting the Hall sensors onto the stator. in order to achieve the best performance. Therefore. will generate an error in determination of the rotor position. of EEE Page 8 .
AMC Engineering College | Dept. The motor can deliver a higher torque. as long as it follows the speed torque curve. During this period. the torque remains constant for a speed range up to the rated speed. maximum up to peak torque. peak torque (TP) and rated torque (TR).1 Torque/Speed Characteristics Figure shows an example of torque/speed characteristics. which can be up to 150% of the rated speed. During continuous operations. 2. As discussed earlier. in a BLDC motor. The motor can be run up to the maximum speed. the motor can be loaded up to the rated torque. extra torque is required to overcome the inertia of the load and the rotor itself. In order to keep the motor running. but the torque starts dropping.CONTROL OF BLDC MOTOR USING dsPIC30F2010 2. especially when the motor starts from a standstill and during acceleration. the peak torque occurs when these two fields are at 90° to each other and falls off as the fields move together. as the rotor moves to catch up with the stator field.4. the second winding is negative (current exits the winding) and the third is in a non-energized condition. Applications that have frequent starts and stops and frequent reversals of rotation with load on the motor. demand more torque than the rated torque. of EEE Page 9 . There are two torque parameters used to define a BLDC motor. Torque is produced because of the interaction between the magnetic field generated by the stator coils and the permanent magnets. the magnetic field produced by the windings should shift position. This requirement comes for a brief period. Ideally.4 Theory of Operation Each commutation sequence has one of the windings energized to positive power (current enters into the winding).
However. it takes six steps to complete an electrical cycle.2 Commutation Sequence FIGURE 6: AN EXAMPLE OF HALL SENSOR SIGNALS WITH RESPECT TO BACK EMF Every 60 electrical degrees of rotation. of EEE Page 10 . the phase current switching should be updated. one of the Hall sensors changes the state. In synchronous. one electrical cycle may not correspond to a complete mechanical revolution of the rotor.CONTROL OF BLDC MOTOR USING dsPIC30F2010 FIGURE 5: TYPICAL TORQUE – SPEED CHARACTERISTICS OF BLDC MOTOR 2.4. Given this. The number of electrical cycles to be repeated to complete a mechanical rotation is AMC Engineering College | Dept. with every 60 electrical degrees.
the number of electrical cycles/rotations equals the rotor pole pairs. Table 3 is for clockwise rotation of the motor and Table 4 is for counter clockwise motor rotation. B and C. one electrical cycle is completed. For each rotor pole pairs.CONTROL OF BLDC MOTOR USING dsPIC30F2010 determined by the rotor pole pairs. FIGURE 7: TYPICAL COMMUATION CIRCUIT Table 3 and Table 4 show the sequence in which these power switches should be switched based on the Hall sensor inputs. AMC Engineering College | Dept. So. of EEE Page 11 . This is an example of Hall sensor signals having a 60 degree phase shift with respect to each other. A.
CONTROL OF BLDC MOTOR USING dsPIC30F2010 FIGURE 8: HALL SENSOR OUTPUT AMC Engineering College | Dept. of EEE Page 12 .
16x) 27 interrupt sources Three external interrupt sources 8 user selectable priority levels for each interrupt 4 processor exceptions and software traps AMC Engineering College | Dept. Brushless DC (BLDC) and DC are some typical motor types for which the dsPIC30F2010 has been specifically designed. 16-bit wide data path 12 Kbytes on-chip Flash program space 512 bytes on-chip data RAM 1 Kbyte non-volatile data EEPROM 16 x 16-bit working register array Up to 30 MIPs operation o DC to 40 MHz external clock input o 4 MHz-10 MHz oscillator input with PLL active (4x.1 Introduction The dsPIC30F2010  is a 28-pin 16-bit MCU specifically designed for embedded motor control applications. 3.CONTROL OF BLDC MOTOR USING dsPIC30F2010 Chapter 3 dsPIC30F2010 3. AC Induction Motors (ACIM).2 Features Modified Harvard architecture C compiler optimized instruction set architecture 84 base instructions with flexible addressing modes 24-bit wide instructions. 8x. of EEE Page 13 .
2.CONTROL OF BLDC MOTOR USING dsPIC30F2010 3.2 Peripheral Features High current sink/source I/O pins: 25 Ma/25 Ma Three 16-bit timers/counters.1 DSP Engine Features Modulo and Bit-Reversed modes Two. of EEE Page 14 .2.2. optionally pair up 16-bit timers into 32-bit timer modules Four 16-bit Capture input functions Two 16-bit Compare/PWM output functions o Dual Compare mode available 3-wire SPITM modules (supports 4 Frame modes) I2CTM module supports Multi-Master/Slave mode and 7-bit/10-bit addressing Addressable UART modules with FIFO buffers 3.3 Motor Control PWM Module Features 6 PWM output channels o Complementary or Independent Output modes o Edge and Center Aligned modes 4 duty cycle generators Dedicated time base with 4 modes Programmable output polarity Dead time control for Complementary mode Manual output control Trigger for synchronized A/D conversions AMC Engineering College | Dept. 40-bit wide accumulators with optional saturation logic 17-bit x 17-bit single cycle hardware fractional/ integer multiplier Single cycle Multiply-Accumulate (MAC) operation 40-stage Barrel Shifter Dual data fetch 3.
) for industrial temperature range.4 Quadrature Encoder Interface Module Features • • • • • • • Phase A.2.5 Analog Features • 10-bit Analog-to-Digital Converter (A/D) with: o 500 Ksps (for 10-bit A/D) conversion rate o Six input channels o Conversion available during Sleep and Idle • Programmable Brown-out Detection and Reset generation 3. 100K (typical) • Data EEPROM memory: o 100. 1M (typical) • • • Self-reprogrammable under software control Power-on Reset (POR).) for industrial temperature range.000 erase/write cycle (min.CONTROL OF BLDC MOTOR USING dsPIC30F2010 3. Phase B and Index Pulse input 16-bit up/down position counter Count direction status Position Measurement (x2 and x4) mode Programmable digital noise filters on inputs Alternate 16-bit Timer/Counter mode Interrupt on position counter rollover/underflow 3. of EEE .6 Special Microcontroller Features • Enhanced Flash program memory: o 10.2.2.000 erase/write cycle (min. Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation • • Fail-Safe clock monitor operation Detects clock failure and switches to on-chip low power RC oscillator Page 15 AMC Engineering College | Dept.
5V to 5.3 Pin Diagram FIGURE 9: PIN DIAGRAM OF dsPIC30F2010 AMC Engineering College | Dept.2. of EEE Page 16 . Idle and Alternate Clock modes 3.CONTROL OF BLDC MOTOR USING dsPIC30F2010 • • • Programmable code protection In-Circuit Serial Programming™ (ICSP™) Selectable Power Management modes o Sleep.7 CMOS Technology • • • • Low power.5V) Industrial and Extended temperature ranges Low power consumption 3. high speed Flash technology Wide operating voltage range (2.
of EEE Page 17 .CONTROL OF BLDC MOTOR USING dsPIC30F2010 FIGURE 10: dsPIC30f2010 BLOCK DIAGRAM AMC Engineering College | Dept.
Always associated with OSC2 pin function. Input change notification inputs. IC8 INDX QEA QEB I I/O I/O I/O I/O I/O I/O I/O I/O I ST ST ST ST ST ST ST ST ST ST I I I ST ST ST INT0 INT1 INT2 FLTA PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H MCLR I I I I O O O O O O I/P ST ST ST ST — — — — — — ST ST — OCFA I OC1 – O OC2 AMC Engineering College | Dept. Compare Fault A input (for Compare channels 1. Oscillator crystal output. IC2. Quadrature Encoder Phase A input in QEI mode. Quadrature Encoder Index Pulse input. ICD Tertiary Communication Channel clock input/output pin.1 Explanation of each pin Pin Pin Name Type AN0 – I AN5 AVDD P AVSS P CLKI I CLKO O Buffer Type Analog P P ST/ CMOS — Description Analog input channels. 2. ICD Quaternary Communication Channel data input/output pin. ICD Primary Communication Channel clock input/output pin. External clock source input. CN0 – CN7 EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2 EMUD3 EMUC3 IC1.3. Ground reference for analog module. Auxiliary Timer External Clock/Gate input in Timer mode. 3 and 4). This pin is an active low Reset to the device. Compare outputs. ICD Secondary Communication Channel data input/output pin ICD Secondary Communication Channel clock input/output pin. The dsPIC30F2010 has 4 capture inputs. The inputs are numbered for consistency with the inputs on larger device variants. Optionally functions as CLKO in RC and EC modes. Quadrature Encoder Phase A input in QEI mode.CONTROL OF BLDC MOTOR USING dsPIC30F2010 3. Connects to crystal or resonator in Crystal Oscillator mode. ICD Tertiary Communication Channel data input/output pin. Positive supply for analog module. ICD Quaternary Communication Channel clock input/output pin. Auxiliary Timer External Clock/Gate input in Timer mode. Can be software programmed for internal weak pull-ups on all inputs. of EEE Page 18 . Always associated with OSC1 pin function. Capture inputs. ICD Primary Communication Channel data input/output pin. IC7. External interrupt 0 External interrupt 1 External interrupt 2 PWM Fault A input PWM 1 Low output PWM 1 High output PWM 2 Low output PWM 2 High output PWM 3 Low output PWM 3 High output Master Clear (Reset) input or programming voltage input.
Synchronous serial clock input/output for SPI™ #1. UART1 Transmit. PORTF is a bidirectional I/O port. Analog Voltage Reference (Low) input. of EEE . UART1 Alternate Receive. ST ST ST ST ST — ST ST ST — ST/CMOS ST ST ST — ST — — — Analog Analog PORTD is a bidirectional I/O port. Synchronous serial clock input/output for I2CTM Synchronous serial data input/output for I2CTM. 32 kHz low power oscillator crystal input. ST buffer when configured in RC mode. 32 kHz low power oscillator crystal output. — CMOS otherwise. Positive supply for logic and I/O pins. SPI #1 Data In. UART1 Receive. RF3 SCK1 SDI1 SDO1 SS1 SCL SDA SOSCO SOSCI T1CK T2CK U1RX U1TX U1ARX U1ATX VDD VSS VREF+ VREFLegend CMOS Analog ST O I P I/O I I/O I/O I/O I/O I/O I/O I O I I/O I/O O I I I I O I O P P I I Buffer Description Type ST/CMOS Oscillator crystal input. UART1 Alternate Transmit. ST buffer when configured in RC mode. Connects to crystal or resonator in Crystal Oscillator mode.CONTROL OF BLDC MOTOR USING dsPIC30F2010 Pin Name OSC1 OSC2 Pin Type I I/O PGD PGC RB0-RB5 RC13RC14 RD0RD1 RE0-RE5. ST PORTB is a bidirectional I/O port. ST PORTC is a bidirectional I/O port. ST In-Circuit Serial Programming clock input pin. Analog Voltage Reference (High) input. Timer1 external clock input. CMOS compatible input or output Analog input Schmitt Trigger input with CMOS levels Output Input Power Page 19 AMC Engineering College | Dept. Ground reference for logic and I/O pins. RE8 RF2. Timer2 external clock input. Oscillator crystal output. Optionally functions as CLKO in RC and EC modes. CMOS otherwise. SPI #1 Data Out. PORTE is a bidirectional I/O port. SPI #1 Slave Synchronization. ST In-Circuit Serial Programming data input/output pin.
free from loop count management overhead. both of which are interruptible at any point. The MultiplyAccumulate (MAC) class of dual source DSP instructions operate through both the X and Y AGUs. and most instructions can address data either as words or bytes. Each block has its own independent Address Generation Unit (AGU). AMC Engineering College | Dept. Thus. An instruction pre-fetch mechanism is used to help maintain throughput. There are two methods of accessing data stored in program memory: • The upper 32 Kbytes of data space memory can be mapped into the lower half (user space) of program space at any 16K program word boundary. This lets any instruction access program space as if it were data space. and the Most Significant (MS) bit is ignored during normal program execution. splitting the data address space into two parts (see Section 3. The data space is 64 Kbytes (32K words) and is split into two blocks.CONTROL OF BLDC MOTOR USING dsPIC30F2010 3.2).4 CPU Architecture Overview The core has a 24-bit instruction word. The Program Counter (PC) is 23 bits wide with the Least Significant (LS) bit always clear (see Section 3. address or offset registers. The working register array consists of 16x16-bit registers. only the lower 16 bits of each instruction word can be accessed using this method.1). Program loop constructs. Each data word consists of 2 bytes. each of which can act as data. which provides the appearance of a single unified data space. Table read and write instructions can be used to access all 24 bits of an instruction word. Most instructions operate solely through the X memory AGU. of EEE Page 20 . defined by the 8-bit Program Space Visibility Page (PSVPAG) register. • Linear indirect access of 32K word pages within program space is also possible using any working register. the PC can address up to 4M instruction words of user program space. via table read and write instructions. One working register (W15) operates as a software stack pointer for interrupts and calls. Moreover. except for certain specialized instructions. The X and Y data space boundary is device specific and cannot be altered by the user. with a limitation that the access requires an additional cycle. are supported using the DO and REPEAT instructions. referred to as X and Y data memory.
a working register (data) read. However. Memory Direct. This is primarily intended to remove the loop overhead for DSP algorithms. a single stage instruction pre-fetch mechanism is used. The X AGU also supports bit-reversed addressing on destination effective addresses. a data memory write and a program (instruction) memory read per instruction cycle. The MAC class of instructions can concurrently fetch two data operands from memory. The core supports Inherent (no operand). Register Indirect. of EEE Page 21 . to greatly simplify input or output data reordering for radix-2 FFT algorithms. 3-operand instructions are supported. the core is capable of executing a data (or program data) memory read. A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. To enable this concurrent fetching of data operands. depending upon their functional requirements. Register Offset and Literal Offset Addressing modes. As a result. Register Direct. It features a high speed 17-bit by 17-bit multiplier. Instructions are associated with predefined Addressing modes. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. Most instructions execute in a single cycle. while multiplying two W registers. in order to maximize available execution time. with certain exceptions.0 for details on modulo and bit-reversed addressing. a 40-bit ALU. This has been achieved in a transparent and flexible manner.CONTROL OF BLDC MOTOR USING dsPIC30F2010 Overhead-free circular buffers (modulo addressing) are supported in both X and Y address spaces. Relative. The core does not support a multi-stage instruction pipeline. AMC Engineering College | Dept. which accesses and partially decodes instructions a cycle ahead of execution. Data in the accumulator or any working register can be shifted up to 15 bits right or 16 bits left in a single cycle. by dedicating certain working registers to each address space for the MAC class of instructions. Refer to Section 4. allowing C = A+B operations to be executed in a single cycle. Literal. the data space has been split for these instructions and linear for all others. For most instructions.
DOEND. N. W2. Data Table Page register (TBLPAG).S and POP. W1. • PUSH. When a byte operation is performed on a working register. However. OV. All registers are memory mapped. only the Least Significant Byte of the target register is affected. Each interrupt is prioritized based on a user assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest) in conjunction with a predetermined ‘natural order’. 2x40-bit accumulators (AccA and AccB). a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses. address or offset registers. of EEE Page 22 . 3. W3. AMC Engineering College | Dept. ranging from 8 to 15. None of the shadow registers are accessible directly. Traps have fixed priorities. The shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. Some of these registers have a shadow register associated with each of them. Z and C bits only) are transferred. DOEND. The following rules apply for transfer of registers into and out of shadows. DCOUNT and RCOUNT). The working registers can act as data. and Program Counter (PC).CONTROL OF BLDC MOTOR USING dsPIC30F2010 The core features a vectored exception processing structure for traps and interrupts.S W0. STATUS register (SR). as shown in Figure 2-1. • DO instruction DOSTART. W0 acts as the W register for file register addressing. DO and REPEAT registers (DOSTART. Program Space Visibility Page register (PSVPAG). The exceptions consist of up to 8 traps (of which 4 are reserved) and 54 interrupts. DCOUNT shadows are pushed on loop start. SR (DC. and popped on loop end. with 62 independent vectors.5 Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists of 16x16-bit working registers (W0 through W15).
W15 is the dedicated software stack pointer (SP).5. the LS Byte of which is referred to as the SR Low Byte (SRL) and the MS Byte as the SR High Byte (SRH). of EEE Page 23 .1 Software Stack Pointer/FRAMe pointer The dsPIC® devices contain a software stack. See Figure 2-1 for SR layout.2 Status Register The dsPIC core has a 16-bit status register (SR). writing and manipulation of the stack pointer (e. Therefore. However. W15 is initialized to 0x0800 during a Reset. 3.5. The user may reprogram the SP during initialization to any location within data space. During exception processing. AMC Engineering College | Dept. However. W14 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading. the DO Loop Active bit (DA) and the Digit Carry (DC) status bit.3 Program Counter The Program Counter is 23 bits wide. The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits. the PC can address up to 4M instruction words. as well as the CPU Interrupt Priority Level status bits. IPL<2:0>.. SRL is concatenated with the MS Byte of the PC to form a complete word value which is then stacked. and will be automatically modified by exception processing and subroutine calls and returns. Bit 0 is always clear. and the REPEAT active status bit. RA. W15 can be referenced by any instruction in the same manner as all other W registers. SRL contains all the MCU ALU operation status flags (including the Z bit). creating stack frames).CONTROL OF BLDC MOTOR USING dsPIC30F2010 3.5.g. W14 has been dedicated as a stack frame pointer as defined by the LNK and ULNK instructions. 3.
CONTROL OF BLDC MOTOR USING dsPIC30F2010 FIGURE 11: PROGRAMMER’S MODEL AMC Engineering College | Dept. of EEE Page 24 .
as listed below: • • • • • • • Fractional or integer DSP multiply (IF). These instructions are ADD. round and saturation logic). Signed or unsigned DSP multiply (US). and a 40-bit adder/ subtractor (with two target accumulators. of EEE Page 25 . SUB and NEG. a barrel shifter.6 DSP Engine The DSP engine consists of a high speed 17-bit x 17-bit multiplier. AMC Engineering College | Dept. Automatic saturation on/off for AccB (SATB). Automatic saturation on/off for writes to data memory (SATDW). which require no additional data.CONTROL OF BLDC MOTOR USING dsPIC30F2010 3. The DSP engine has various options selected through various bits in the CPU Core Configuration Register (CORCON). The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations. Accumulator Saturation mode selection (ACCSAT). Conventional or convergent rounding (RND). Automatic saturation on/off for AccA (SATA).
1 Introduction The Change Notification (CN)  pins provide dsPIC30F devices the ability to generate interrupt requests to the processor in response to a change of state on selected input pins. The CNEN1 and CNEN2 registers contain the CNxIE control bits. FIGURE 12: INPUT CHANGE NOTIFICATION BLOCK DIAGRAM 4. Each CN pin has a weak pull-up device connected to the pin. where ‘x’ denotes the number of the CN input pin.CONTROL OF BLDC MOTOR USING dsPIC30F2010 Chapter 4 CHANGE NOTIFICATION 4. The CNPU1 and CNPU2 registers contain the CNxPUE control bits. The CNxIE bit must be set for a CN input pin to interrupt the CPU. which can be enabled or disabled using the CNxPUE control bits.1. The weak pull-up devices act as a current source that is connected AMC Engineering College | Dept. of EEE Page 26 . Up to 24 input pins may be selected (enabled) for generating CN interrupts.1 CN Control Registers There are four control registers associated with the CN module. The total number of available CN inputs is dependent on the selected dsPIC30F device.
Select the desired interrupt priority for CN interrupts using the CNIP<2:0> control bits (IPC3<14:12>). 6. 5. Enable CN interrupts using the CNIE (IEC0<15>) control bit. Clear the CNIF (IFS0<15>) interrupt flag. AMC Engineering College | Dept. Enable interrupts for the selected CN pins by setting the appropriate bits in the CNEN1 and CNEN2 registers. 4. 2. 4. the user should read the PORT register associated with the CN pin(s). Ensure that the CN pin is configured as a digital input by setting the associated bit in the TRISx register. 3. When a CN interrupt occurs.1.2 CN Configuration and Operation The CN pins are configured as follows: 1.CONTROL OF BLDC MOTOR USING dsPIC30F2010 to the pin and eliminate the need for external resistors when push button or keypad devices are connected. of EEE Page 27 . This will clear the mismatch condition and setup the CN logic to detect the next pin change. Turn on the weak pull-up devices (if desired) for the selected CN pins by setting the appropriate bits in the CNPU1 and CNPU2 registers. The current PORT value can be compared to the PORT read value obtained at the last CN interrupt to determine the pin that changed.
the device will wake from Sleep or Idle mode and resume operation. If one of the enabled CN pins changes states. device execution will continue from the instruction immediately following the SLEEP or IDLE instruction. the CNIF (IFS0<15>) status bit will be set. If the CNIE bit (IEC0<15>) is set.3 CN Operation in Sleep and Idle Modes The CN module continues to operate during Sleep or Idle modes.1. AMC Engineering College | Dept. of EEE Page 28 .CONTROL OF BLDC MOTOR USING dsPIC30F2010 4. If the assigned priority level of the CN interrupt is greater than the current CPU priority level. If the assigned priority level of the CN interrupt is equal to or less than the current CPU priority level. device execution will continue from the CN interrupt vector address.
of EEE Page 29 . the following power and motion control applications are supported • • • • Three-Phase AC Induction Motor Switched Reluctance (SR) Motor Brushless DC (BLDC) Motor Uninterruptable Power Supply (UPS) The PWM module has the following features: • • • • • • Dedicated time base supports TCY/2 PWM edge resolution Two output pins for each PWM generator Complementary or independent operation for each output pin pair Hardware dead time generators for complementary mode Output pin polarity programmed by device configuration bits Multiple output modes: o Edge aligned mode o Center aligned mode o Center aligned mode with double updates o Single event mode • • • • • Manual override register for PWM output pins Duty cycle updates are configurable to be immediate or synchronized to the PWM Hardware fault input pins with programmable function Special Event Trigger for synchronizing A/D conversions Each output pin associated with the PWM can be individually enabled AMC Engineering College | Dept. In particular.CONTROL OF BLDC MOTOR USING dsPIC30F2010 Chapter 5 GENERATION OF PWM SIGNALS 5.1 Introduction The motor control PWM (MCPWM)  module simplifies the task of generating multiple. synchronized pulse width modulated outputs.
This has the same effect as having a PWM signal on the high side and connecting the low side to VSS or GND. FIGURE 13: PWM MODULE PWM is provided by the dsPIC30F2010’s dedicated Motor Control (MC) PWM. When there is a match. IGBTs or MOSFETs. of EEE Page 30 . The MCPWM module has been designed specifically for motor control applications. the three windings can be driven ON High. As shown in Figure 2. which can be as low as TCY. When driving the PWM signal.) The MCPWM has a dedicated 16-bit PTMR time base register. The user also decides the period required for the PWM by selecting a value and loading it in the PTPER registers. low side drivers are preferred over high side drivers. the variable duty cycle signal PWM can be injected on the low side driver. (Please refer to Figure 3 as you follow this discussion of the MCPWM module. This timer is incremented by a user defined clock tick. a new period is started. The PTMR is compared to the PTPER value at every TCY. AMC Engineering College | Dept. to the high side. When one leg of the winding is connected for example.2 Motor Control PWM Module The dsPIC30F2010 has six PWM outputs that can be driven with the PWM signal. driven ON Low or not driven at all by using six switches.CONTROL OF BLDC MOTOR USING dsPIC30F2010 5.
. then the corresponding duty cycle output is driven low or high as dictated by the PWM mode selected. and vice versa. a dead time can be inserted between the time the high level goes low and the low level goes high. the value in the duty cycle register is compared at every TCY/2 interval (i. When driven as complementary outputs. Dead time insertion prevents inadvertent shoot-thru in output drivers. of EEE Page 31 . The two outputs can also be configured as independent outputs. Unlike the period compare. twice as fast as the period compare).e. The three outputs from the duty cycle compare are channelled to a complementary output pair where one output is high while the other is low. AMC Engineering College | Dept. by loading a value in the three duty cycle registers. This dead time is hardware configured and has a minimum value of TCY.CONTROL OF BLDC MOTOR USING dsPIC30F2010 FIGURE 14: EDGE CONTROLLED PWM The duty cycle is controlled similarly. If there is a match between the PTMR value and the PDCx value.
of EEE Page 32 . The PTMR match with AMC Engineering College | Dept. Edge aligned output is probably the most common mode. the outputs are all driven high. a match with the duty cycle registers causes the corresponding duty cycle output to go low thereby marking the end of the duty cycle.CONTROL OF BLDC MOTOR USING dsPIC30F2010 FIGURE 15: MOTOR CONTROL PWM MODULE BLOCK DIAGRAM There are several modes in which the MCPWM module can be configured. Figure 4 depicts the operation of an edge aligned PWM. At the start of the period. As the PTMR increments.
The high byte portion of the OVDCON register. The Override Control is the last stage of the MCPWM module. When controlling the BLDC sensored motor it is necessary to excite two winding pairs depending on where the rotor is located and dictated by the value of the hall sensors. Depending on the value in the OVDCON register. The important feature of the MCPWM used in this application is the Override Control. The OVDCON register has two 6 bit fields in it. at all output stages of the pins. the same value is written to all PDCx registers. determines if the corresponding output pin is driven by a PWM signal (when set to 1) or (when set to 0) driven Active/Inactive by the corresponding bit field in the low byte portion of the OVDCON register. but not driving. the user can select which pin gets the PWM signal and which pin is driven active or inactive. Each of the six bit fields corresponds to an output pin. This feature allows the user to have PWM signals available. It allows the user to directly write to the OVDCON register and control the output pins.CONTROL OF BLDC MOTOR USING dsPIC30F2010 PTPER register caused a new period to start and all outputs go high to start a whole new cycle. Table 1 and Figure 5 show how different values are loaded in the OVDCON register depending on which sector the rotor is located in and thereby which windings need to be excited. In the CN Interrupt Service routine the hall sensors are read and then the value of the sensors is used as an offset in a lookup table which corresponds to the value which will be loaded in the OVDCON register. For BLDC motors. AMC Engineering College | Dept. of EEE Page 33 .
CONTROL OF BLDC MOTOR USING dsPIC30F2010 Chapter 6 MOSFET MOTOR DRIVER 6. MOSFET or an Insulated Gate Bipolar Transistor (IGBT). MOSFET. IGBT) is used. we are going to assume that a little more voltage and power capability is needed than what the MOSFET drivers can handle. For this application note. In some small Brushless DC motor or stepper motor applications. This can be a bipolar transistor. AMC Engineering College | Dept. This requires that the voltage applied to the motor is modulated in some manner. The purpose of motor speed control is to control the speed. the MOSFET driver can be used to directly drive the motor. By turning the power-switching elements on and off in a controlled manner. of EEE Page 34 . direction of rotation or position of the motor shaft.1 Introduction The bridging element between the motor and MOSFET driver is normally in the form of a power transistor. though. This is where the power-switching element (bipolar transistor. the voltage applied to the motor can be varied in order to vary the speed or position of the motor shaft.
These MOSFETs are connected in a three-phase bridge format to the three BLDC motor windings.2 Hardware Description FIGURE 16: BLOCK DIAGRAM The three pairs of Motor Control PWM outputs are connected to three MOSFET driver pairs (BC547). In the current implementation. of EEE Page 35 . 6. and the maximum MOSFET current is 18 Amps. In this circuit MOSFET Driver comprises of BJTs (BC547) which is biased as emitter to base bias for high side switching and collector bias technique for low side switching. which in turn are connected to six MOSFETs (IRF547 and IRF9540). the maximum MOSFET voltage is 70Volts. AMC Engineering College | Dept.3 MOSFET Driver MOSFET Driver along with three phase half bridge driver sends the PWM switching pulses to the BLDC Motor.CONTROL OF BLDC MOTOR USING dsPIC30F2010 6. It is biased for switching operation which consists of high side switching and low side switching.
AMC Engineering College | Dept.1 MOSFET Driver Circuit for high side switching The base resistor RB and collector RC values are found using the formulae.CONTROL OF BLDC MOTOR USING dsPIC30F2010 6. of EEE Page 36 .3.
AMC Engineering College | Dept.CONTROL OF BLDC MOTOR USING dsPIC30F2010 6.3.2 MOSFET Driver Circuit for low side switching The emitter resistor RE and collector RC values are found using the formulae. of EEE Page 37 .
CONTROL OF BLDC MOTOR USING dsPIC30F2010 6. MOSFET is used as switch for producing the PWM Signals.1 Three phase half bridge circuit with driver AMC Engineering College | Dept.4. Switching circuit consists of Low side switching and high side switching • • IRF540 is used for low side switching IRF9540 is used for high side switching 6.4 Three phase half bridge It produces PWM signals required for controlling of the BLDC Motor. of EEE Page 38 .
while the motor speed depends only on the amplitude of the applied voltage.1 Introduction Commutation ensures proper rotor rotation of the BLDC motor. The amplitude of the applied voltage is adjusted by using the PWM technique. The difference between the actual and required speed is input to the PI controller and. 7. the PI controller controls the duty cycle of PWM pulses. The speed controller is implemented as a conventional PI controller. of EEE Page 39 . which corresponds to the voltage amplitude required to keep the required speed.2 Mathematical Model FIGURE 16: BLOCK DIAGRAM OF PI CONTROLLER The speed controller calculates a Proportional-Integral (PI)  algorithm according to the following equations: ( ) [ ( ) ∫ ( ) ] Transformation to a discrete time domain using an integral approximation by a Backward Euler method yields the following equations for the numerical PI controller calculation: AMC Engineering College | Dept. The required speed is controlled by a speed controller. based on this difference.CONTROL OF BLDC MOTOR USING dsPIC30F2010 Chapter 7 PI CONTROLLER 7.
of EEE Page 40 . e(k) w(k) m(k) u(k) up(k) uI(k) uI(k-1) TI T Kc = = = = = = = = = = Input error in step k Desired value in step k Measured value in step k Controller output in step k ) ( ) Proportional output portion in step k Integral output portion in step k Integral output portion in step k-1 Integral time constant Sampling time Controller gain AMC Engineering College | Dept.CONTROL OF BLDC MOTOR USING dsPIC30F2010 ( ) ( ) ( ) ( ) ( ) ( Where.
of EEE Page 41 .CONTROL OF BLDC MOTOR USING dsPIC30F2010 7.3 Flowchart for speed control of BLDC Motor FIGURE 17: FLOWCHART AMC Engineering College | Dept.
of EEE Page 42 . The primary features of the UART module are: • • • • • • • • • • • Full-duplex 8.1 Introduction The Universal Asynchronous Receiver Transmitter (UART)  module is one of the serial I/O modules available in the dsPIC30F device family.875 Mbps at FCY = 30 MHz 4-deep First-In-First-Out (FIFO) transmit data buffer 4-deep FIFO receive data buffer Parity.or 9-bit data transmission through the UxTX and UxRX pins Even. RS-232 and RS-485 interfaces. Odd or No Parity options (for 8-bit data) One or two Stop bits Fully integrated Baud Rate Generator with 16-bit prescaler Baud rates ranging from 29 bps to 1. such as personal computers.CONTROL OF BLDC MOTOR USING dsPIC30F2010 Chapter 8 UART 8. Framing and Buffer Overrun error detection Support for 9-bit mode with Address Detect (9th bit = 1) Transmit and Receive Interrupts Loopback mode for diagnostic support AMC Engineering College | Dept. The UART is a full-duplex asynchronous system that can communicate with peripheral devices.
The UART’s transmitter and receiver are functionally independent. eight or nine data bits. An on-chip dedicated 16-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. are specified in the PDSEL<1:0> (UxMODE<2:1>) and STSEL (UxMODE<0>) bits.3 UART Configuration The UART uses standard non-return-to-zero (NRZ) format (one Start bit. and the parity. The most common data format is 8 bits. 1). of EEE Page 43 . and one or two Stop bits). Parity is supported by the hardware. The UART transmits and receives the LSb first. odd or no parity. no parity and one Stop bit (denoted as 8. and may be configured by the user as even.2 Block Diagram FIGURE 18: BLOCK DIAGRAM OF UART A simplified block diagram of the UART is shown in Figure 18. The number of data bits and Stop bits. AMC Engineering College | Dept. N.CONTROL OF BLDC MOTOR USING dsPIC30F2010 8. but use the same data format and baud rate. The UART module consists of the key important hardware elements: • • • Baud Rate Generator Asynchronous Transmitter Asynchronous Receiver 8. which is the default (POR) setting.
the UxTSR is loaded with new data from the UxTXREG register. The Shift register obtains its data from the transmit FIFO buffer. so a transfer to the UxTXREG register will result in an immediate transfer to UxTSR. Clearing the UTXEN bit during a transmission will cause the transmission to be AMC Engineering College | Dept. Normally when transmission is first started. FIGURE 19: UART TRANSMITTER Transmission is enabled by setting the UTXEN enable bit (UxSTA<10>). The UxTSR register is not loaded until the Stop bit has been transmitted from the previous load. UxTXREG. of EEE Page 44 . The actual transmission will not occur until the UxTXREG register has been loaded with data and the Baud Rate Generator (UxBRG) has produced a shift clock (Figure 19-2). The transmission can also be started by first loading the UxTXREG register and then setting the UTXEN enable bit. The UxTXREG register is loaded with data in software.CONTROL OF BLDC MOTOR USING dsPIC30F2010 8.4 UART Transmitter The UART transmitter block diagram is shown in Figure 19-2. As soon as the Stop bit is transmitted. the UxTSR register is empty. The heart of the transmitter is the Transmit Shift register (UxTSR).
8. the current buffer location becomes available for new data to be written and the next buffer location is sourced to the UxTSR register. The FIFO is reset during any device Reset.CONTROL OF BLDC MOTOR USING dsPIC30F2010 aborted and will reset the transmitter. the PDSEL<1:0> bits (UxMODE<2:1>) should be set to ‘11’ and the ninth bit should be written to the UTX9 bit (UxTXREG<8>). of EEE Page 45 .2 Transmit Interrupt The transmit interrupt flag (UxTXIF) is located in the corresponding interrupt flag status (IFS) register.1 Transmit Buffer Each UART has a 4-deep. AMC Engineering College | Dept. If a user attempts to write to a full buffer. The user may write up to 4 words in the buffer. the new data will not be accepted into the FIFO.4. an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) and the transmit buffer is empty. the ISR is completed before the transmission of the next word). If UTXISEL = 0. Since an interrupt is generated only after all 4 words have been transmitted.. but is not affected when the device enters a Power saving mode or wakes up from a Power saving mode.4. 2. the UxTX pin will revert to a highimpedance state. 1. Since an interrupt is generated after the transfer of each individual word. 9-bit wide FIFO transmit data buffer. If UTXISEL = 1. The UTXBF (UxSTA<9>) status bit is set whenever the buffer is full. As a result. this mode is useful if interrupts can be handled frequently (i. The UxTXREG register provides user access to the next available buffer location. In order to select 9-bit transmission. The UTXISEL control bit (UxSTA<15>) determines when the UART will generate a transmit interrupt. an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR). 8. Once the UxTXREG contents are transferred to the UxTSR register. This implies that the transmit buffer has at least one empty word. A word write should be performed to UxTXREG so that all nine bits are written at the same time.e.
Enable the UART module by setting the UARTEN (UxMODE<15>) bit. set the UxTXIE control bit in the corresponding Interrupt Enable Control register (IEC). Initialize the UxBRG register for the appropriate baud rate 2. If 8-bit transmission is used. Specify the interrupt priority for the transmit interrupt using the UxTXIP<2:0> control bits in the corresponding Interrupt Priority Control register (IPC). 3. select the Transmit Interrupt mode by writing the UTXISEL (UxSTA<15>) bit. While the UxTXIF flag bit indicates the status of the UxTXREG register. Also. the TRMT bit (UxSTA<8>) shows the status of the UxTSR register. AMC Engineering College | Dept. Data can be loaded into the buffer until the UxTXBF status bit (UxSTA<9>) is set. which is set when the UxTSR register is empty. Switching between the two Interrupt modes during operation is possible. which will also set the UxTXIF bit. 4. The TRMT status bit is a read only bit. If 9-bit transmission has been selected. No interrupt logic is tied to this bit. and parity selection by writing to the PDSEL<1:0> (UxMODE<2:1>) and STSEL (UxMODE<0>) bits. load a byte.e. load a word. The UxTXIF bit should be cleared in the software routine that services the UART transmit interrupt.3 Steps for UART Transmit Steps to follow when setting up a transmission 1. The user should clear the UxTXIF bit in the ISR. 6. The UxTXIF bit will be set when the module is first enabled. Set the number of data bits. The operation of the UxTXIF bit is controlled by the UTXISEL control bit. of EEE Page 46 . so the user has to poll this bit in order to determine if the UxTSR register is empty. If transmit interrupts are desired.4. number of Stop bits. Enable the transmission by setting the UTXEN (UxSTA<10>) bit..CONTROL OF BLDC MOTOR USING dsPIC30F2010 this ‘Block Transmit’ mode is useful if the user’s code cannot handle interrupts quickly enough (i. the ISR is completed before the transmission of the next word). Load data to the UxTXREG register (starts transmission). 5. 8.
Refer to the device data sheet for further details. The 10-bit A/D converter can have up to 16 analog input pins. The actual number of analog input pins and external voltage reference input configuration will depend on the specific dsPIC30F device. there are two analog input pins for external voltage reference connections. One. or four of the S/H amplifiers may be enabled for acquiring input data. two.CONTROL OF BLDC MOTOR USING dsPIC30F2010 Chapter 9 ANALOG TO DIGITAL CONVERTOR 9.1 Introduction The dsPIC30F2010 10-bit A/D converter has the following key features: • • • • • • • • • • • • Successive Approximation (SAR) conversion Up to 1 Msps conversion speed Up to 16 analog input pins External voltage reference input pins Four unipolar differential S/H amplifiers Simultaneous sampling of up to four analog input pins Automatic Channel Scan mode Selectable conversion trigger source 16 word conversion result buffer Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes 9. These voltage reference inputs may be shared with other analog input pins. The analog input multiplexers can be switched between two sets of analog inputs during conversions. designated CH0CH3. The analog inputs are connected via multiplexers to four S/H amplifiers.2 Block Diagram A block diagram of the 10-bit A/D is shown in Figure 17-1. AMC Engineering College | Dept. of EEE Page 47 . Unipolar differential conversions are possible on all channels using certain input pins. In addition. designated AN0-AN15.
of EEE Page 48 . The 10-bit A/D is connected to a 16-word result buffer. Each 10-bit result is converted to one of four 16-bit output formats when it is read from the buffer.CONTROL OF BLDC MOTOR USING dsPIC30F2010 An Analog Input Scan mode may be enabled for the CH0 S/H amplifier. AMC Engineering College | Dept. A Control register specifies which analog input channels will be included in the scanning sequence.
of EEE Page 49 .CONTROL OF BLDC MOTOR USING dsPIC30F2010 FIGURE 20: BLOCK DIAGRAM OF ADC AMC Engineering College | Dept.
The ADPCFG register configures the analog input pins as analog inputs or as digital I/O. AMC Engineering College | Dept. The ADCSSL register selects inputs to be sequentially scanned. The ADCHS register selects the input pins to be connected to the S/H amplifiers. These registers are: • • • • • • ADCON1: A/D Control Register 1 ADCON2: A/D Control Register 2 ADCON3: A/D Control Register 3 ADCHS: A/D Input Channel Select Register ADPCFG: A/D Port Configuration Register ADCSSL: A/D Input Scan Selection Register The ADCON1.3 Control Registers The A/D module has six Control and Status registers. ADCON2 and ADCON3 registers control the operation of the A/D module. of EEE Page 50 .CONTROL OF BLDC MOTOR USING dsPIC30F2010 9.
of EEE Page 51 .CONTROL OF BLDC MOTOR USING dsPIC30F2010 Chapter 10 CONCLUSION The dsPIC30F2010 is well suited for closed – loop control of a sensored BLDC motor. The peripherals and DSP engine provide an excellent bandwidth for sensored BLDC applications with sufficient code space available for the customer’s application program. AMC Engineering College | Dept.
AMC Engineering College | Dept. 11. thus complicating the controller. gyroscope controls and so on.1 Applications with constant loads These are the types of applications where a variable speed is more important than keeping the accuracy of the speed at a set speed. appliance. fuel pump control. These applications demand low-cost controllers. In home appliances. Automotive. These applications may demand high-speed control accuracy and good dynamic responses. engine control and electric vehicle control are good examples of these. of EEE Page 52 . These applications may use speed feedback devices and may run in semi-closed loop or in total closed loop.1. mostly operating in open-loop. dryers and compressors are good examples.CONTROL OF BLDC MOTOR USING dsPIC30F2010 Chapter 11 SCOPE OF THE PROJECT 11. washers. like centrifuges. In addition. this increases the price of the complete system. Out of these. In these types of applications. the acceleration and deceleration rates are not dynamically changing.1 Typical BLDC Applications BLDC motors find applications in every segment of the market. electronic steering control. the load is directly coupled to the motor shaft. For example. fans. automation. In automotive.2 Applications with Varying Loads These are the types of applications where the load on the motor varies over a speed range. pumps. These applications use advanced control algorithms. aviation and so on. industrial controls.1. there are a number of applications. we can categorize the type of BLDC motor control into three major types: • • • Constant load  Varying loads  Positioning applications  11. have applications for BLDC motors. In aerospace. robotic arm controls. Also. pumps and blowers come under these types of applications.
AMC Engineering College | Dept. the dynamic response of speed and torque are important. which could be mechanical gears or timer belts. Process controls. these applications may have frequent reversal of rotation direction. a constant speed phase and a deceleration and positioning phase. of EEE Page 53 . These systems mostly operate in closed loop. separate position sensors may be used to get absolute positions. The applications in this category have some kind of power transmission. the same sensors are used to get relative position information.1. Optical encoder or synchronous resolvers are used for measuring the actual speed of the motor. The load on the motor may vary during all of these phases. machinery controls and conveyer controls have plenty of applications in this category.3 Positioning Applications Most of the industrial and automation types of application come under this category. or a simple belt driven system. Speed Control Loop and Position Control Loop. Otherwise. A typical cycle will have an accelerating phase. causing the controller to be complex. In some cases.CONTROL OF BLDC MOTOR USING dsPIC30F2010 11. Computer Numeric Controlled (CNC) machines are a good example of this. Also. There could be three control loops functioning simultaneously: Torque Control Loop. In these applications.
R. Cliffs.CONTROL OF BLDC MOTOR USING dsPIC30F2010 Chapter 12 REFERENCES  N. 13–17. (APEC’94). New Jersey. “A complete model characterization of brushless dc motors. ‘Servo Motor and Motion Control using Digital Signal Processors’ Prentice Hall. 351–355. pp.   dsPIC30F reference manual A. Jan./Feb. 1990. C. 1994. Ind. Feb. AMC Engineering College | Dept. Eagle Wood. 1992. Millner.” IEEE Trans. “Multi-hundred horsepower permanent magnet brushless disc motors. IEEE Appl.” in Proc. Leu.   dsPIC30F2010 datasheet Yasuhiko Dote. of EEE Page 54 . Applicat. Power Electron.. Conf. pp. vol. Hemati and M. 172–180. 28.
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