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A 500 MHz GaAs Digital RF'Memory Modulator IC

Gary McMilliari, William Hallidy, Marty Hood, George Phan, Tan Chu, IGm Lau, Mike Lawrence, Bryan Thrailkill, Jimmy Phan, Andy Lee, Clark Musgrove, Mike Sanders, AI Morgan, Gary Schmidt, Gary Zreet
Systems & Processes Engineering Corporation (SPEC) 401 Camp Craft Road, Austin, TX 78746-6558 USA Phone 512-306-1 100, Fax 512-306-1 122,

Abstract - A single chip Digital Radio Frequency Memory (DRFM) Modulator provides time delay, Doppler shifting, ;and phaselamplitude modulation of RF signals. The digital IC lhas been implemented in Vitesse Semiconductor's H-GaAs III technology for operation up to 500 MHz, and was designed with COMPASS Design* Automation's CAE tools and SPEC'S standard cell libraries.


RF Frontend (Downconverter)

INTRODUCTION Digital RF Memories (DRFMs) are used to provide time delay of RF signals. DRFMs have been integrated into electronic countermeasures systems to spoof enemy radar systems, in radar simulators to synthesize a real-time targetclutter environment, and to simulate satellite or mobile communications networks.[ 1-31 A typical DRFM (see Fig. 1) consists of an RF frontend which downconverts an RF signal to a lower intermediate frequency (IF), an analog-to-digital converter (ADC) which samples the IF waveform, a memory to store the digitized waveform for a programmable time delay, modulators to apply i i Doppler shift and phase/amplitude scaling, a digital-toiinalog converter (DAC) to reconstruct the intermediate frequency waveform, and an RF backend to upconvert the IF i o the original RF carrier frequency. The RF frontend and backend is constructed of MMICs operating at microwave to millimeterwave frequencies. The IF is chosen to fit within the capabilities of available ADCs and IDACs used for sampling and reconstruction of the IF waveform. Narrowband DRFMs employ high resolution ADCs and DACs, while wideband DRFMs utilize high performance 6- to 8-bit ADCs operating in the GHz range. 'Wideband, high fidelity DRFMs operating with IFS in the 100 MHz to 500 MHz range with 12-bits of accuracy are desired for use in radar and communication system simulators and electronic countermeasure systerns, but are currently limited by the state-of-the-art in ADC technology. SPEC has developed a highly integrated DRFM chip which implements the two functions outlined in bold in IFig. 1, and operates up to 500 MHz at 12-bits of accuracy. 'The IC imparts a programmable tirne delay on the R F waveform using a large external memory and a small internal memory, and uses digital signal processing techniques to iipply a Doppler shift and phase and arnplitude modulation to {he RF waveform. The outputs from multiple DRFM IModulators can be digitally summed together to form a complete target/clutter signal environment.

ADCs VQ Memory (Time Delay)




Modulator (Doppler + Phase/Amplitude)

IF RF Backend (Upconverter)

Digital Clock

Local Oscillator
Fig. 1 . Digital RF Memory


This work was supported by the U S . Air Force Wright Laboratory under contract number F33615-93-C-1290 and the US. Army Missile Command under contract number DAAHOl-92-C-R 112.

ARCHITECTURE A block diagram of the DRFM Modulator architecture is shown in Fig. 2. The IC captures in-phase and quadrature (VQ) components from the high speed ADCs., buffers the VQ data into a 192-bit word and writes the word into an external memory. The DRFM operates in a continuous acquisition (wrap around) mode. Data words are written and read on alternating cycles, and the address range separating the write and subsequent read determines the coarse time delay imparted on the sampled waveform. An internal memory is used in a similar fashion for fine time delay.

0-7803-3504-XI96 $5.00 0 1996 IEEE

GaAs IC Symposium 73


starting with high level schematics entered in COMPASS' Logic Assistant tool.and 14-bit data. Transistors 492.5 ns at 25 " 16-bits. The IC includes IEEE 1149.1 Hz 74 . COMPASS Design Automation's CAE tools and internally developed GaAs libraries are used to develop high performance GaAs ICs following the same design methodology used in submicron CMOS design. Alternatively. Internal datapaths range from 12. Doppler shifted VQ components are then fed into two independent phase/amplitude modulators. SPEC follows a top-down design methodology. a designer draws a schematic containing all of the 1/0pads and a single logic block for the core logic. High current open-drain drivers are used to drive the SRAM address bus.000 transistors. which are set by an external source through the data port. which multiplies the VQ components by the sine and cosine outputs of a Direct Digital Synthesizer (DDS). static timing analysis indicates a critical path of 2. Fig. 2.1 Hz steps. Design specifications are listed in Table 1.External SRAM (Coarse Delay) Fine Delay - Direct Digital Synthesizer Doppler Modulator --b Dual PhasdAmp Modulators H The DRFM Modulator IC datapaths and statemachines were designed to operate at a clock frequency of 500 MHz. datapath specifications. the tools can create complete VHDL specifications for simulation from a combination of Logic Assistant schematics. 3.GaAs IC Symposium . The time delayed. DRFM MODULATOR DESIGN SPECIFICATIONS Sample Rate V Q Data Sample Size Maximum Time Delay ~~ ~~ I 5500MSPS 1 .128 ms b e Delay Resolution Signal Latency I 2ns 4 ns without modulation 1 Maximum Doppler Shift Doppler Resolution k250 MHz (Nyquist limit) 0.000 600 96. Many GaAs designs done at SPEC contain datapaths captured as graphical bit-slice specifications and control logic or decoders captured as VHDL specifications. and embedded VHDL specifications. Additional component specifications are given in Table 2. SPICE analysis predicts a power dissipation of 65 W at a 25 "C junction temperature. Table 1. Inside the core logic block additional levels of schematic hierarchy are captured to specify the complete IC design. The VQ and H N data ports are ECL compatible. which is compatible with VHDL produced by the COMPASS tools. DESIGN SPECIFICATIONS The DRFM Modulator provides programmable time delay out to 128 ms in 2 ns increments. The tools provide support for automatic generation of VHDL code from templates. or a 400 MHz clock The 15 mm x 15 mm die contains 492.6 pm YO & Power Pads Die Pad Pitch I Die Size Power Supply I 15mmx15mm I I Power Dissipation Package I 5V (referenced to -2V) -2v 65 W @ 25 "C Junction Modified 557 pin PGA DESIGN METHODOLOGY SPEC'S IC development flow is shown in Fig. Doppler frequency shifting of +250 MHz in 0. The modulators operate on signed 12. DRFM Modulator Architecture The time delayed VQ data is fed into a Doppler Modulator. and produce signed 14bit results. the outputs can be combined to form I/Q inputs to an external analog vector modulator. which in combination can be used to implement polarization modulation. with boundary scan on all ECL and TTL UOs. After block place and route. In addition. The DDS generates signed 14-bit values on each clock cycle using an algorithmic approach developed at SPEC. The DDS frequency is set by an external controller through a 16-bit data port. while the external SRAM data ports are 5V TTL compatible. and require external pull-up resistors. A VHDL Test Bench can be output to aid in test development. The outputs of the single-sideband modulators represent horizontal (H) and vertical (V) polarization signals.1 support. The DDS uses unsigned 16-bit compiled datapath elements to calculate signed 14-bit sinekosine components. Each modulator multiplies the VQ components by modulation coefficients. Typically. and phase/amplitude modulation over a 14-bit dynamic range. SPEC uses Model Technology's V-Systeflorkstation for VHDL simulation. A positive or negative Doppler frequency shift can be applied to the I and Q components by the DDS.12 bits 0 .

Air Force and Mr. REFERENCES [ 1J “Digital RF Memories” J. John Cole of the US. 4). was done with COMPASS’S Chipcompiler (see Fig. SPEC is currently developing standard cell libraries for Vitesse’s H-GaAs IV process and Motorola’s CGaAsTM process. Data busses crossing the 15 mm square die were also pipelined to meet the 2 ns delay goal. Datapath bit-slice specifications were compiled with COMPASS’ Datapath Compiler to optimized layout using SPEC’s datapath cell library. [2] Proceedings “Digital RF Memory Workshop ‘95” Atlanta. GaAs IC Symposium 75 - . These values are used to compute interconnect delays in the Delay Calculator. 27-28. including floorplanning and place and route. which implement a majority of the digital signal processing functions. 3.S. Calvin Kasadate of the U.LVS Tapeout SrrCompare Fig. PathFinder. targeted to SPEC’s GaAs cell libraries. The ASIC Synthesizer has been modified to support GaAs Direct Current FET Logic (DCFL) static current requirements in addition to optimization for maximum dynamic performance. SPEC is in the process of qualifying COMPASS’S new nlevel metal place and route tool. 1994 Supplement. SPEC uses COMPASS’ Design Ride Checker and Netcompare tools to verify the design prior to final tapeout. 1995. Chipcompiler places and routes standard cell blocks then routes the standard cell and complied datapath blocks in channels between the blocks. Compiled datapaths. U 0 and datapath compiler libraries for Vitesse’s H-GaAs E l process. VHDL Simulator QSIM Simulator QTV Static Timing Analyzer GAASLIBRARIES SPEC has developed commercially available standard cell. 131Marvin Potts “Digital Single Sideband Modulator Baldwidth Study” Wright Laboratory Tech Brief WL-TR-92-1032. metal 3 for VDD (and some clock networks). Jan. The libraries have been characterized using Vitesse’s HSPICE model for the H-GaAs I11 process.I Enter Design using Logic Assistant Generate Netlist using HDL Assistant Generate he-Route SDF Timing Estimates Generate Test Bench using. the netlist is extracted with COMPASS’ Interconnect Extractor. Sept. were highly pipelined to meet the 2 ns cycle time goal. ACKNOWLEDGMENT The authors wish to thank our contract monitors. Design Kule Checker (DRC) Screcncr & S P K CRC Tool I DRC.Army.ERC. These highly optimized layout designs provide maximum density and highest performance for multi-bit datapaths. for GaAs design. SPEC’s GaAs ASIC Design Flow The behaviorauRTL VHDL specifications in the design were synthesized with COMPASS’ Synthesizer. In the H-GaAs 111 technology. for their support. A photo of the DRFM die is shown in Fig. Electronic Defense. Finally. Capt. and metal 4 for VSS. Georgia. 5. and their performance has been proven in a number of GaAs ASICs. D. which computes net resistance and capacitance from a physical model of the metal interconnects. Final chip assembly. SPEC uses metal 1 and metal 2 for all signal routing. The delays are back-annotated in the structural VHDL specification for simulation in the VHDL simulator. After place and route. The timing delays computed by the Delay Calculator are used in QTV (COMPASS’ static timing analyzer) to analyze the critical paths throughout the chip and in QSIM for gate level simulation. Regular datapath structures also significantly aid in reducing clock skew within the chip. 19. HDL Assistant Model Technology’s V-System/ Workstation J Logic Synthesis Datapath Compilation Placement &Routing Extraction ASIC Synthesizer Datapath Compiler Chipcompiler Interconnect Extractor The DRFM Modulator required significant pipelining to achieve 500 MHz performance.

4. DRFM Modulator Place and Route Results in COMPASS Design Automation’s ChipCompileI Fig.GaAs I C Symposium .Fig. 5. DRFM Modulator Die Photo 76 .