You are on page 1of 4

A HIGH-SPEED

MAGNITUDE COMPARATOR WITH SMALL TRANSISTOR COUNT

Shun-Wen Cheng
Tamkang Univ., Taipei, TAIWAN

swcheng@ieee.org

ABSTRACT The comparator is a very basic and useful arithmetic component of digital systems. An individual, compact, high-performance, good cost-benefit ratio comparator core plays an important role on almost all hardware sorters. The study proposes a tine cost-performance ratio comparator design. Based on modified 1’s complement principle and conditional sum adder scheme, the proposed design has small transistor count and short propagation delay. Post-layout simulations based on TSMC 0.6um lP3M CMOS process has completed. It shown a 64-b static CMOS comparator of the proposed architecture only needs 1,556 transistors and 4.211s.
Index Term - magnitude comparator, digital comparator, sorter, 1’s complement, conditional sum adder, CMOS, digital IC and VLSI.

h a

max(a,b) min(a,h)

h a#;

;#b a Pb
a <b

a

a b

a
, ,

min(a, b) max(a,b)

a#; b a<b

;#;
a 2b

Figure 1. Compare & swap elements are vital for sorting

Level-1 stage 1

stage . 1

Level-2 stage2

Level -3 sub-soner
, ,
stage 1

stage2

stage3

1 . INTRODUCTION
Sorting is one of the most important problems in computer science. Many fundamental processes in computing and communication systems require sorting of data. Sorting network play a key role in the areas of parallel computing, multi-access memories and multiprocessing [I], [2], [SI. As depicted in Fig. 1, compare and swap elements of data are vital for sorting. In conventional computer systems, instruction COMPARE and instruction SUBTRACT often share the hardware. This can reduce cost. And the time complexity is limited on O(n) of radix sort or O(n log n) of quick sort in average cases [SI. Figure 2 displays an eight number three-level hitonic sorter. It uses 24 comparators to attain a higher performance target. The time complexity of n (log n)‘ comparator bitonic sorter is O((log n)‘), far better than common software solutions [I], [2]. But if someone needs to process long digit integer sorting, then directly design a corresponding hardware sorter, the comparators array will become very large. At this time, a compact, high-performance comparator core is very important.

.
Figure 2. A three-level bitonic sorter

.....

Ancient magnitude comparators are shown in Fig. 3 [41. The circuit compares two binary number A and B, and produces three output: A>B, A=B, A<B. In many applications, two output is enough: A t B and A<B. Due to the limitation of CMOS logic [XI, 4-bit comparator is the basic constructive unit. The example just reveals circuit costlcomplexity of a (2k)-bit comparator are often not only twice than a k-bit comparator. Implement a long bit-length comparator by the old scheme is uneconomical. This paper is organized as follows. In Section 2, it shows the feasibility of modified 1’s complement for comparator design. Then the proposed comparator architecture is presented in Section 3. Finally conclude the major findings and outline the future work.

0-7803-8163-7/03/$17.00 B 2003 IEEE 1168

ICECS-2003

the scheme always adds a fixed carry." B.@-around cany_bilJ = t 0 ~0 1 o 0 0 0 0 +'.. In common discussions. X . 1169 . At this time make the fixed cam-in bit = 0 always. = 67. bit Comp =O. If X > Y . is ineffective. bit Cout =O.. For comparator design. and the condition is solved. directly compare the sign bit and then the answer is obtained. X -X =01010100 ... After modificalion. bit Cout = 1.. thi: cany out bit information is only concerned.- 0 0 1 0 0 0 1 CarrectAnswer: 17..mplementofX = m ~ o u t m I 1 I 0 I I 1 0 I + ~ C a m p = E < e d cany-in bit I ~ I l O l1 I 1 I - (c) 4-bit comparator.. Modified l'c compkment for comparator design.. Figure 4. bit Comp = 1... The classic designs in Fig. then the output signal Comp = Comp Cl? Sign-hit. both ONO numbers are positive.. =Campm0 Sum .* BfY (d) 16-bitcomparator. A. 3. o I n o o n I I . . A.. 4 A>=B (a) I-bit magnitude comparator.--.. Thus the status of hit Comp fits the convention of comparison. 0 1 0 1 0 1 0 0 =x = + I 0 I 0 1 0 K= 1's wmplementofX Cclrrecthswer. Figure 3.x=0 Y = 1 0 I O 1 0 o.= 84.. they need two hits to express the same information. The classic circuit of magnitude comparators.....01010100 (84= 84) (b) %bit comparator.X =01000011 -01010100 (67 < 84) 0 1 0 0 0 0 1 1 = Y CiirrectAnswer:-l7. If X $Y. MODIFIED 1's COMPLEMIENT FOR COIMPARATOR DESIGN Figure 4 displays a modified 1's complement scheme.. If X < Y .-... I = . If both two numbers are negative.... 1 I C a m p r n l 1 1 I 1 1 1 1 + ~ C a m p =Ed carry-in bit 1 0~ 0 O 0 0 0 0 0 C.0 lOOOOll (84 > 67) O l O l O l D O =x = + ~ c o u 1 0 1 1 1 I Do= 1's CUmplementofY ... then if X L Y .. -. 2.. I . + I 0 I 0 1 0 E= I'r.Y = 01010100 . If two numbers have different signs.. the answer is just oonosite. Y .

and eleven 2-10-1 multiolexers. eight two-input OR gates. k=1 where M = l o g . AS BS A3 E3 A2 B2 AI BI A0 BO Figure 5.Stage0 A7 i Stage 1 Stage 2 Stage 3 B7 Comp = 1 . Comp = 0. They can provide for the use of stage-l multiplexers.. The schematic need eight inverters to generate complementary values of input B. Figure 5 shows an %bit comparator example of the proposed comparator architecture. A>=B. the proposed architecture is improved from Conditional Sum Adder 161. so this reduces the requirements of inverter. THEPROPOSED COMPARATOR ARCHITECTURE For high-performance demand. 1170 . Now if C=O. The total transistor count is eight inverters. Cany =AB. 2(2k-1). The static CMOS AND gate and OR gate internally generate their complementary signals [SI. high-performance. A < B. An 8-b brief schematic example of the proposed comparator architecture. Cany = AB + (A+B) = A + B. good cost-benefit ratio comparator core plays an important role on almost all hardware sorters. and seven two-input AND gates. The 8-b comparator needs 11(=1+3+7) 240-1 multiplexers. Originally Cany = AB + AC + BC = AB + (A + B) C. . 3. If C=l. N . The sum of MUX gates of N-bit comparator is. An individual.

and now he joins Dept. Feb. 2003. So the total transistor count of the 8-b static CMOS comparator is (lp+ln)x8 + (3p+3n)x8 + (3p+3n)x7 + (2p+2n)x7 + (3p+3n)x(ll-7) = 79p + 7911. “A 1. ASP-DAC‘03. E:ihraghian. 1171 . [4] Kai Hwang. AFIPS 1968 Spring Joinr Computer Conference. IEEE J. Tamsui. C.120 p2) I I Table 2.522n 375p+742n 742p+742n 400~x380~ ACKNOWLE!DGEMENT The author. Chung-Li. Complementary Pass-transistor Logic (CPL) can reduce the data skew problem and power dissipation. Nov. pp.I REFERENCES [I] K. 307-314. pp.. Asia and South Pacific Design Auromarion Conj. The total transistor count of N-bit static CMOS comparator is. No. 6.-C. of EE. “Conditional-Sum Addition Logic. Post-layout simulation results are summarized in Table 2. We can use CPL to replace static CMOS logic gates in low-power low-voltage applications. 1973. 1968.0 GHz 64-bit High-speed Comparator Using ANT Dynamic Logic with Two-Phase Clocking. 2.” in Proc. Cheng has already left Dept. Under the proposed comparator architecture.” in Proc. Shun-Wen ‘Cheng.rhniques. Reading: AddisonWesley.x l z C 2 * -l)l-(N-l) *. (4p+4n)N +(5p+5n)(N . Weste and K. i * I where M = log N. Architecture andDesign. Tamkang University. 1 M 1 [3] Chung-Hsun Huang and Jinn-Shyan Wang. will have the fewest transistor count but large power dissipation and slow operation speed. If N = M-hit. Tsai.1 ) + ( 3 p + 3 n ) [ x ( 2 * -l)I-(N -I) .. x(N . E. 433436. Apr. The transistor count and layout area of the proposed comparator are both less than 1998 Chua-Chin Wang’s Comparator [71 and 2003 Chung-Hsun Huang’s Comparator [31.522p+1. comparator. Reading: Addison-Wesley. Computer Arithmetic-Principles.172 w’) 576pmx120pm (= 69. June 1960. therefore the total transistor count is 742x2 + 18x4 = 1.b7~rz. Soning and Searching. 254-262. Jan. *.. 38. 2003. Reading: John Wiley & Sans. Transistor count and simulation comparisons of 64-b comparator designs. INV x N + ANDZx N + OR2x(N . Knuth. 226-231. [8] N. Kuo-Hsing Cheng. implement AND gate and OR gate by NMOS logic. . (using static CMOS) I I (= 72. Vol. Principle of CMOS VLSIDesign. (All are based on TSMC 0.-F. 32 64 1.” IEE Proceedings Compurers and Digital Te.I) + Mux2fols. 1979. 1998. and use pure NMOS multiplexer networks. TAIWAN.6um CMOS prncess.Bit Number Cornoarator Of 2 II design static [41 oseudo-NMOS 8p+13n 38p+38n II The Proposed design with lI The Proposed design with static CMOS 13p+I3n I l I 4. would like to thank his advisor Prof. H.I where M = log N. for his previous teaching on IC design. One of the stars of Tamkang has gone. The circuit easily partitions to several stage pipelines for increasing the hardware sharing and data throughput. National Central University.I)+ M~2~~Lzb~. Prof. no.6um Single-layer Polysilicon Triple-layer Metal (1P3M) CMOS Process Technology. The Proposed Comparator.. [51 D . The author found the transistor count of the new design is less than that required in the conventional design. 1993. Solid-state Circuii’s. and K. 1 I pp. and eighteen buffers are used for increasing driving capability. E. “Arbitrtuy Long Digit Sorter HWISW Co-Design. TAIWAN. EC-9. “Sorting Networks and Their Applications.” IRE Transncrions on Elecrronic Computers. while the transistor count of the new design with static CMOS is only approximately half of the conventional design. pp. vol. E. And the worst propagation delay is shorter than their designs. Wu. 2nd Ed. Batcher. [6] J.556. pp. CONCLUSmIG REMARKS The complexity informarion is listed in Table 1. 538-543.) The total gate count of N-hit comparator is. Vol.. Sklansky.. 145. “HighPerformance and Power-Efficient ChllOS Comparators”. of EE. [2] Shun-Wen Cheng. [7] Chua-Chin Wang. The comparisons of a:omparator design are based upon TSMC 0.