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Verilog HDL Basics

Presenter: Dr. Abhijit Asati Abhijit asati@bits-pilani Abhijit_asati@bits ac in

What is an HDL?
• An HDL is NOT a software programming language Software Programming Language

– Language which can be translated into machine instructions
and d then h executed d on a computer Eg. C, Perl, Python Hardware Description Language – Language g g with syntactic y and semantic support pp for modeling g the temporal behavior and spatial structure of hardware • VHDL: (Very High Speed Integrated Circuit (VHSIC) H d Hardware D Description i ti Language L • Verilog: Verifying Logic HDL

Abstraction levels in Digital IC Design:

Application of HDLs :

Why HDLs? .

3 • In larger and more complex designs. designers began using gate-level models described in a HDL for verification.1 • For designs with just a few gates. these gate-level models are at too low-level for the initial specification . it was possible to verify these circuits on paper or with breadboards 2 • As designs grew. for early highlevel design exploration.

D Prabhu P bh Goel G l -1983 1983 •Cadence’s ownership of verilog HDL made it more essential for EDA companies. •GDA was privately i t l h held ld by b Dr.VERILOG HDL •Verilog HDL was the intellectual property of gateway design automation. •IEEE Standards: IEEE 1364 – 1995 IEEE 1364 – 2001 IEEE 1364 – 2005 .

and b h i l models behavioral d l – mix i ‘n’ ‘ ’ match! t h! . codes are written using a mix of gate-level. dataflow.Ab t ti Levels Abstraction L l in i Verilog V il •Gate Level Modeling •Data Flow Modeling g •Behavioral Modeling g •Switch Level Modeling Usually.

NOR NOR. •Dataflow modeling gp provides:  shielding from this excessive attention to details  shows how data flows between blocks. XOR XOR. NOT and their interconnections. NAND NAND. •Behavioral modeling: Similar to programming in C Little concern as to actual hardware implementation . OR OR.Why levels? •Gate level Modeling offers control over hardware gates like : AND .

. •Identifiers start with an alphabetic character or an underscore only. the underscore or the dollar sign ($)  other characters like ~. ) etc. (.!. •They y can’t start with number or a $ sign. g •Keywords can’t be used as identifiers. input clk. *. reg value.IDENTIFIERS: •Identifiers are made of: alphanumeric character. %. // where reg is keywords and value is an identifiers . are not allowed •Identifiers are case sensitive. #. KEYWORDS: Keywords are in lowercase.

.1.c. wire d=1’b0. wire [7:0] bus. wand b.Data Types: Nets • Can be thought as hardware wires driven by logic • Value set for wire: { 0.X.g: e g: wire a. wire [31:0] bus A.Z } • Various types of nets – wire – wand d – wor (wired-AND) (wired AND) (wired-OR) • e. . . bus C. wire b. bus B. wor x.

automatically. every time A or B changes A B A Y B Y wire Y. // declaration assign Y = A & B. // declaration assign Y = A. . .Nets •In following g example: p Y is evaluated. wand Y. assign Y = B.

the default is scalar ( 1-bit ). A. 0. 1. • ‘reg’ eg assignments ss g e s are e always w ys do done e inside s de a always w ys o or initial b block oc reg A = C = A = C = A. 0. // C gets the logical value 1 // C is still 1 // C is now 0 • Register values are updated explicitly!! .Registers • R Registers i retain i value l until il another h value l is i placed l d on them. C. h • ‘reg’ data type can be declared as: – vectors (multiple bit widths) – If bit width is not specified.

real delta.•INTEGER: -(231-1) to +(231-1) e. initial begin delta = 4e10.g. •REAL: REAL e. g integer counter.13. end . initial counter=-1.g. delta = 2.

parameter port_id=5. integer & time e.•TIME : A special time register data type is used in verilog to store simulation time.g. time save_sim_time. save sim time. //bool[31] to bool[0] time chk_point chk point [1:100].// count[0] to count[7] reg bool [31:0].g. parameter cache_line_width = 256.g. eg e. g e. g integer count [0:7]. // //Save the h current simulation i l i time i •ARRAYS: Allowed for reg. . // chk_point[1] to chk_point[100] •PARAMETERS: PARAMETERS Constants C can be b defined d fi d in i a module d l by b the h keyword parameter. initial save_sim_time = $time.

g. Full Adder Half Adder Half Adder .Hierarchical Design g Top Level Module Sub-Module 1 Sub-Module 2 Basic Module 1 Basic Module 2 Basic Module 3 e.

Gate Primitives •and •nand •or •nor •xor •xnor •not •buf b f Properties of these gates are: Execute E t in i parallel ll l Order independent Continuously active .

b).a. output s.b). and g2(c.b.a.c.b). xor g1(s.a.c. endmodule A B S Half Adder C .Gate Level A B C S HALF ADDER module halfadder(s. input a.

Hierarchical design: Full Adder in1 in2 A B Half Adder 1 ha1 S C I1 I2 A B Half Adder ha2 S C I3 sum cout cin .

halfadder ha1(s1.c2.c2. halfadder ha2(s.c1). output s. input a. or o1(cout.c1.cin).a.b).module fulladder(s.cin. fulladder(s cout a b cin).b.s1. endmodule d d l a b A B Half Adder 1 ha1 s1 c1 A B Half Adder ha2 s c2 01 sum cout cin i .cin).b. c2.s1. wire c1.a.cout.cout.

Other Full Adder .

B=0. not (x5 (x5. B=0. #3 A= 0. xor (Sum. #3 A= 1.B).A. B=1. nor (x4.x1.A. ( 2 ) not (x3. #3 A= 1.x2). ). A=0.Cin=1.x1.B). nand d (x2. . end endmodule .B.x3). #3 A= 0. reg A. B=1.x5).Cin=0.module FA (Sum. #3 A= 1. .Cin=1.x6). ). Cin).x6. B=0.Cin=1. output Sum. B=1.A. or (x6. wire x1. #3 $finish. # #3 A= 1. .x5.B.Cout). initial begin $monitor("A = %b B = %b Cin = %b Sum = %b Carry = %b".x2.Cin=0.Cin).Cin=1. B=1.Cin.Cin.x3. . nand(Cout. nor (x1.x4. Cin=0.Sum.Cin).x4. #3 A= 0.Cout). .Cout. B=0. ( .Cin=0.x2.

exe Highest level modules: FA Compile Complete . A = 0 B = 0 Cin = 0 Sum = 0 Carry = 0 A = 0 B = 0 Cin = 1 Sum = 1 Carry = 0 A = 0 B = 1 Cin = 0 Sum = 1 Carry = 0 A = 0 B = 1 Cin = 1 Sum = 0 Carry = 1 A = 1 B = 0 Cin = 0 Sum = 1 Carry = 0 A = 1 B = 0 Cin = 1 Sum = 0 Carry = 1 A = 1 B = 1 Cin = 0 Sum = 0 Carry = 1 A = 1 B = 1 Cin = 1 Sum = 1 Carry y=1 Exiting VeriLogger Command Line at simulation time 24000 0 Errors. . Execution time = 0..06300 Normal exit Process exited with code 0.00300.00000. Load time = 0.. i C1> . R Running. 0 Warnings Compile time = 0.Working directory: E:\ARA_Synapticad\ Executable file: C:\SynaptiCAD\bin\vlogcmd.

Circuit1_with delay: Module D (out . b. input a.c. wire d.c). // out @ T = 4 endmodule d d l . and #(5) a1 (d. // d @ T = 5 or #(4) O1 (out .a.b) .b. a.d. output out. c).

and #(30) g1(e.y. endmodule .B. output x.B. or #(20) g3 (x.Circuit #1 with delay // Description of circuit module circuit_bln (A. C). input A. y). wire e.x. e.y).C.C).C. not #(10) g2 (y (y.A.B).

C=1'b1 C=1 b1 . B. C.B.y. x. initial b i begin A = 1'b0.// stimulus for simple circuit module stimcrct. wire x. B = 1'b1. end endmodule Note: observe Glitch in output X . 1 b1. reg A. #100 A = 1'b1. 1 b1. circuit_bln cwd( A. B = 1'b0. C = 1'b0.C. #100 $finish. y).

b1. #3 A = 1'b0. #3 A = 1'b0. (Y A).A). not #(10) n1 (Y. output Y. #15 A = 1'b0. A). #3 A = 1'b1. #15 A = 1'b1. t t b h module reg A. initial begin A = 1'b0. #20 $finish.A).Circuit #2 with delay module gate_delay gate delay (Y. end endmodule . gate_delay gd (Y. endmodule d l test_bench. input A. #10 A = 1 1'b1.


Data Flow Modeling • Continuous Assignements • Syntax: assign #delay <id> = <expr>. • Where h to write i them: h – inside a module – outside t id procedures d (i iti l and (initial d always l block) bl k) • Properties of these statements are: – Execute in parallel – Order independent – Continuously active .

cout. input a. assign sum=T1^cin.T3.b.cin. wire T1. assign T2=a&b.cout. assign cout cout= a&b | b&cin | cin&a .a. assign cout=T2|T3|T4.cout.cin). assign T3=b&cin. assign T1=a^b. endmodule module FA_dataflow (a. input a.b.cin.b.T4.module fa1(s.b.sum. output s. endmodule .cout).cin. output sum. assign s=a^b^cin. assign T4=cin&a.T2.

.Behavioral Modeling • Can be b expressed di in two types of f procedures/blocks: d /bl k – initial  they execute only once – always  they execute for ever (until simulation finishes) • Modules can contain any number of procedures • Procedures can p Execute in parallel Order independent It can miss events if procedure evaluation is not complete l for f previous i event and d it i gets another h event.

. 2-to-1 mux implementation: b i begin if (sel == 0) Execution Y = B.g.e. Flow else Y = A. end Procedural assignments .Procedural Statements • Procedural statements i. statements inside a procedure – Execute sequentially q y – Order dependent – Continuously not active • e..

“Initial” Initial Blocks • Start execution at sim time zero and finish when their last statement executes module nothing. $display(“Really?”). initial begin #50. initial $display(“I’m first”). end d endmodule Will be displayed at sim time 0 Will be displayed at sim time 50 .

“Always” Always Blocks • Start execution at sim time zero and continue until sim finishes .

) begin .Events • @ always @(signal1 or signal2 or .. execution ti triggers ti every end time any signal changes always @(posedge clk) begin ... end execution triggers every time clk changes from 0 to 1 execution i triggers i every time clk changes from 1 to 0 always @(negedge clk) begin . end ..

output S S. always @(A or B) begin S = A ^ B.Examples • B Behavioral h i l implementation i l i of f half h lf adder dd module half_adder(S. reg S. C. B). B. wire A. end endmodule . C. A. B. C = A & B.C. input A.

always @(a or b or cin) #1 {s. s cout.cout.b.cout. reg s. b i output s. endmodule .a. { .cin).cin. i input a.cout}=a+b+cin.b.cout.•Behavioral implementation p of full adder module fab(s. } .

Clk. Level L l triggered ti d DFF ? . Clk. Clk).• Behavioral edge-triggered DFF implementation module dff(Q dff(Q. . wire D. endmodule e. D D. reg Q. output Q. always @(posedge Clk) Q = D. input p D. .g.

end c b 0 5 10 15 Time Each assignment g is blocked by its previous one . #5 b = 0. #5 d = c.Behavioral Timing Blocking assignments: Sequential Block d initial begin g #5 c = 1.

Blocking assignments: Parallel Block initial fork #5 c = 1. . #5 d = c. •Order Od i is important i t t only l if no delay d l clause l is i used d or execution ti is i at t same time. #5 b = 0. join //gets updated value d c b Assignments are parallel blocked here 0 5 10 15 Time •Order of execution is controlled by delay.

always @ (posedge CLK) begin c <= #5 1. #5 d <= c. posedge of CLK at T=0 Let next posedge of CLK at T=9 Let. d < <= #5 c. end Assignments are not blocked here initial begin/fork #5 c <= 1. b <= #5 0.Non-blocking assignments: Let. #5 b <= 0. here! . end/join But they are are.

Thank You! ????? .