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Preface, Contents Bit Logic Instructions

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SIMATIC Ladder Logic (LAD) for S7-300 and S7-400 Programming
Reference Manual

Comparison Instructions Conversion Instructions Counter Instructions Data Block Instructions Logic Control Instructions Integer Math Instructions Floating Point Math Instructions Move Instructions Program Control Instructions Shift and Rotate Instructions Status Bit Instructions Timer Instructions Word Logic Instructions Appendix Overview of All LAD Instructions Programming Examples Working with Ladder Logic

This manual is part of the documentation package with the order number: 6ES7810-4CA07-8BW1

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Edition 01/2004
A5E00261407-01

Index

Safety Guidelines
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Qualified Personnel
Only qualified personnel should be allowed to install and work on this equipment. Qualified persons are defined as persons who are authorized to commission, to ground and to tag circuits, equipment, and systems in accordance with established safety practices and standards.

Correct Usage
Note the following:

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Warning
This device and its components may only be used for the applications described in the catalog or the technical description, and only in connection with devices or components from other manufacturers which have been approved or recommended by Siemens. This product can only function correctly and safely if it is transported, stored, set up, and installed correctly, and operated and maintained as recommended.

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SIMATIC®, SIMATIC HMI® and SIMATIC NET® are registered trademarks of SIEMENS AG. Third parties using for their own purposes any other names in this document which refer to trademarks might infringe upon the rights of the trademark owners. Copyright © Siemens AG 2004 All rights reserved
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A5E00261407-01

Preface
Purpose
This manual is your guide to creating user programs in the Ladder Logic (LAD) programming language. This manual also includes a reference section that describes the syntax and functions of the language elements of Ladder Logic.

Basic Knowledge Required
The manual is intended for S7 programmers, operators, and maintenance/service personnel. In order to understand this manual, general knowledge of automation technology is required. In addition to, computer literacy and the knowledge of other working equipment similar to the PC (e.g. programming devices) under the operating systems MS Windows 2000 Professional or MS Windows XP Professional are required.

Scope of the Manual
This manual is valid for release 5.3 of the STEP 7 programming software package.

Compliance with IEC 1131-3
LAD corresponds to the “Ladder Logic” language defined in the International Electrotechnical Commission's standard IEC 1131-3. For further details, refer to the table of standards in the STEP 7 file NORM_TBL.WRI.

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

iii

Preface

Requirements
To use this Ladder Logic manual effectively, you should already be familiar with the theory behind S7 programs which is documented in the online help for STEP 7. The language packages also use the STEP 7 standard software, so you should be familiar with handling this software and have read the accompanying documentation. This manual is part of the documentation package "STEP 7 Reference". The following table displays an overview of the STEP 7 documentation:
Documentation STEP 7 Basic Information with • • • Working with STEP 7 V5.3, Getting Started Manual Programming with STEP 7 V5.3 Configuring Hardware and Communication Connections, STEP 7 V5.3 From S5 to S7, Converter Manual Ladder Logic (LAD) / Function Block Diagram (FDB) / Statement List (STL) for S7-300/400 manuals Standard and System Function for S7-300/400 Provides reference information 6ES7810-4CA07-8BW1 and describes the programming languages LAD, FBD and STL, and standard and system function extending the scope of the STEP 7 basic information. Purpose Order Number

Basic information for technical 6ES7810-4CA07-8BW0 personnel describing the methods of implementing control tasks with STEP 7 and the S7-300/400 programmable controllers.

• •

STEP 7 Reference with

Online Helps Help on STEP 7

Purpose

Order Number

Basic information on Part of the STEP 7 programming and configuring Standard software. hardware with STEP 7 in the form of an online help. Context-sensitive reference information. Part of the STEP 7 Standard software.

Reference helps on AWL/KOP/FUP Reference help on SFBs/SFCs Reference help on Organization Blocks

iv

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

an open dialog box or an active window. You will find your contact person at: http://www.siemens. You can open the contextsensitive help via the menu command Help > Context-Sensitive Help.sitrain. This online help is intended to provide you with detailed support when using the software. Internet: http://www. Please contact your regional training center or our central training center in D 90327 Nuremberg. for example. please get in touch with your Siemens representative or agent responsible. Further Support If you have any technical questions. This manual is an extract from the "Help on Ladder Logic". The help system is integrated in the software via a number of interfaces: • The context-sensitive help offers information on the current context. Germany for details: Telephone: +49 (911) 895-3200. it is easy to switch between the manual and the online help. • You can call the general Help on STEP 7 using the menu command Help > Contents or the "Help on STEP 7" button in the context-sensitive help window.com Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 v .com/automation/partner Training Centers Siemens offers a number of training courses to familiarize you with the SIMATIC S7 automation system. by pressing F1 or by using the question mark symbol in the toolbar. As the manual and the online help share an identical structure.Preface Online Help The manual is complemented by an online help which is integrated in the software. • You can call the glossary for all STEP 7 applications via the "Glossary" button.

365 days a year Phone: Fax: E-Mail: GMT: +49 (180) 5050-222 +49 (180) 5050-223 adsupport@ siemens. 8:00 to 5:00 PM Phone: Fax: E-Mail: +86 10 64 75 75 75 +86 10 64 74 74 74 adsupport.Preface A&D Technical Support Worldwide.com +1:00 United States (Johnson City) Technical Support and Authorization Local time: Mon. vi Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . 8:00 to 5:00 PM Phone: Fax: E-Mail: +1 (423) 262 2522 +1 (423) 262 2289 simatic.-Fri.siemens.hotline@ sea.-Fri.-Fri.asia@ siemens.com GMT: +8:00 The languages of the SIMATIC Hotlines and the authorization hotline are generally German and English. 8:00 to 5:00 PM Phone: Fax: E-Mail: GMT: +49 (180) 5050-222 +49 (180) 5050-223 adsupport@ siemens.com GMT: -5:00 Asia / Australia (Beijing) Technical Support and Authorization Local time: Mon.com +1:00 Europe / Africa (Nuernberg) Authorization Local time: Mon. available 24 hours a day: Nure nbe rg Jo hns o n City Be ijing Pe king Worldwide (Nuernberg) Technical Support 24 hours a day.

• A forum.Preface Service & Support on the Internet In addition to our documentation. we offer our Know-how online on the internet at: http://www. where users and experts from all over the world exchange their experiences. • Your local representative for Automation & Drives. repairs.com/automation/service&support where you will find the following: • The newsletter. spare parts and more under "Services". Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 vii . which constantly provides you with up-to-date information on your products.siemens. • Information on field service. • The right documents via our Search function in Service & Support.

Preface viii Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

................................................................12 3..4 Overview of Comparison Instructions .....9 1..............1-4 --|NOT|-...................3-7 INV_I Ones Complement Integer ...........1-9 ---( S ) Set Coil .........................12 1...............................2-1 CMP ? I Compare Integer .....................................1-18 NEG Address Negative Edge Detection ..............................................4 1..........................................................................................1-14 ---( N )--..................................1-12 SR Set-Reset Flip Flop .......Normally Open Contact (Address) ..8 1.................................................................................................................................................................1-23 2-1 Comparison Instructions 2....................................................3-3 I_DINT Integer to Double Integer ..............................................................1 3..15 1..3-12 ROUND Round to Double Integer...14 3........................................................................................................1-17 ---(SAVE) Save RLO into BR Memory .3-6 DI_REAL Double Integer to Floating-Point .........................18 2 1-1 Overview of Bit Logic Instructions ........................................................................................................................................................Midline Output ..........8 3..............1-21 Immediate Write ...........................2 1.......1-20 Immediate Read .1-3 XOR Bit Exclusive OR............................................................2-2 CMP ? D Compare Double Integer ..........................9 3..........................7 1...13 3............................1-16 ---( P )--.3 2.......3-5 DI_BCD Double Integer to BCD....5 1....................Invert Power Flow ..................................................1-1 ---| |--........................................................11 1...............................2-3 CMP ? R Compare Real ....................................3-2 I_BCD Integer to BCD..................................3-10 NEG_DI Twos Complement Double Integer ...........................Contents 1 Bit Logic Instructions 1..........................................1 1.................6 3..............1-6 ---( # )--..............3-1 BCD_I BCD to Integer..............................................................16 Overview of Conversion Instructions ................10 1....1-19 POS Address Positive Edge Detection ....................7 3..............................3 1......................................................2 2...........................5 3................1 2............1-2 ---| / |--........................10 3..............................................3 3.........3-11 NEG_R Negate Floating-Point Number ...................................3-9 NEG_I Twos Complement Integer ...................................................................................3-15 FLOOR Floor.........................3-4 BCD_DI BCD to Double Integer.................2 3....................17 1...................................................................................2-4 3-1 3 Conversion Instructions 3.....Negative RLO Edge Detection................Positive RLO Edge Detection ..........................................11 3.....................................................Normally Closed Contact (Address) .....................................1-5 ---( ) Output Coil .................................3-16 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 ix .......................................................................................14 1................................................................................................1-11 RS Reset-Set Flip Flop ............4 3.....................1-8 ---( R ) Reset Coil ..................3-8 INV_DI Ones Complement Double Integer.............................16 1..................................................................................3-13 TRUNC Truncate Double Integer Part ...................................13 1..............................................................15 3...........6 1...........................................................3-14 CEIL Ceiling .......

..8-9 EXP Establish the Exponential Value ..................................3.................7-10 MOD_DI Return Fraction Double Integer.8-17 x Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 ..................................8-12 COS Establish the Cosine Value .........................3.................3 8.....................................4....6-3 ---( JMPN ) Jump-If-Not........................................7-9 DIV_DI Divide Double Integer .8-3 SUB_R Subtract Real ........3 8...........................................4..7-3 SUB_I Subtract Integer ......................2 8............................1 ---(OPN) Open Data Block: DB or DI ...4 8.........................................8-10 LN Establish the Natural Logarithm .....................................................7-5 DIV_I Divide Integer .............4 6.......................................................................5-1 6-1 6 Logic Control Instructions 6.7 4-1 Overview of Counter Instructions ..............1 8............................................8 7...............5 8...............1 8.....2 8............................8-2 Basic Instructions ................................................................................................................4-3 S_CU Up Counter ..................................6-5 7-1 7 Integer Math Instructions 7......................8-5 DIV_R Divide Real ..................................................1 7............................4-10 ---( CD ) Down Counter Coil.......................................................................................................................................4 8.........................3 6...........................4.........................................................8-8 SQRT Establish the Square Root ......................3 4............6 7...5 Overview of Logic Control Instructions ....Unconditional Jump.....................................................7 7...4..............................................4 7.........................................2 6.................................2 8.......................8-6 ABS Establish the Absolute Value of a Floating-Point Number................3 7.........8-11 SIN Establish the Sine Value ..................................................4.....................3 8.......11 Overview of Integer Math Instructions ...4-12 5-1 5 Data Block Instructions 5................................................................................................................................6-4 LABEL Label ...........................3...................1 4..7-11 8-1 8 Floating Point Math Instructions 8......................................................8-14 ASIN Establish the Arc Sine Value ..............................3.............................Conditional Jump..................................7-8 MUL_DI Multiply Double Integer ........4.....8-7 Extended Instructions.......8-3 ADD_R Add Real ........7-2 ADD_I Add Integer ........8-1 Evaluating the Bits of the Status Word with Floating-Point Math Instructions ........4-1 S_CUD Up-Down Counter ..........................8-15 ACOS Establish the Arc Cosine Value ...........................................................8-13 TAN Establish the Tangent Value ..........................................................................................................................................1 8......6-1 ---(JMP)--.................................3.............Contents 4 Counter Instructions 4....................................................................10 Overview of Floating-Point Math Instruction ..........8-4 MUL_R Multiply Real .10 7........4 4.......................................7-1 Evaluating the Bits of the Status Word with Integer Math Instructions ..4-7 ---( SC ) Set Counter Value..................................................................................................7-7 SUB_DI Subtract Double Integer ..7 8...4...............................................8 8...5 4.....................................................................................2 4...............................................................................4-5 S_CD Down Counter..........................................................................4 8.....................6 4..5 8.........2 7...........1 6....4.......................................6-2 ---(JMP)--....8-16 ATAN Establish the Arc Tangent Value ................................................................7-6 ADD_DI Add Double Integer ....................................................9 8.5 7...................................................4...................................................................................8-8 SQR Establish the Square .......................................7-4 MUL_I Multiply Integer ...4-9 ---( CU ) Up Counter Coil .............................................9 7....4...................................................................6 8..

.......................1.......4 11.........Result Bit Equal 0 ...................................................13 10..........1 12....................6 11.......................1..............Result Bit Greater Than 0 ..................................1 9-1 MOVE Assign a Value................................................................................................12-9 <0 ---| |--...................6 10..............................................................11 10...........................................................................11 Overview of Statusbit Instructions...............11-7 SHR_DW Shift Right Double Word...........10 10...........12-5 BR ---| |--.......14 Overview of Program Control Instructions .............................11-11 Overview of Rotate Instructions .....................12-6 ==0 ---| |--.................10-6 CALL_SFB Call System FB from Box.........................................10-2 CALL_FB Call FB from Box ...........12-8 >0 ---| |--........2 11......................................................................................................................................................................................................10-18 ---(MCRD) Master Control Relay Deactivate ..............1 11...................................................5 11...............11-9 Rotate Instructions ..................................5 10............12-3 UO ---| |--.................2 11...................................................10-19 ---(RET) Return ..2.1 10....................Contents 9 Move Instructions 9..............Result Bit Not Equal 0........10-12 Important Notes on Using MCR Functions ........1.........Exception Bit Binary Result...........................11-11 ROR_DW Rotate Right Double Word .9 10..........Result Bit Greater Equal 0 ................Exception Bit Overflow......7 12.......................................11-3 SHL_W Shift Left Word ..12-1 OV ---| |--..........................7 10..........................Result Bit Less Than 0.................................10-1 ---(Call) Call FC SFC from Coil (without Parameters)....6 12.............................................2 10.....................3 11........4 10..........................................1..........................................................2 11.............................................................12-11 <=0 ---| |--.......................8 12.......................1..........................................................10-13 ---(MCR<) Master Control Relay On ..........................................................................................10 12.......1...............................12-2 OS ---| |--...................2 12.......11-13 12-1 12 Status Bit Instructions 12............12 10...5 12...........10-20 11-1 11 Shift and Rotate Instructions 11...........................1 11.......10-12 Call Block from a Library .............Result Bit Less Equal 0..............................................................1 11...........................12-10 >=0 ---| |--............10-16 ---(MCRA) Master Control Relay Activate.....................................11-5 SHR_W Shift Right Word ......11-6 SHL_DW Shift Left Double Word................11-11 ROL_DW Rotate Left Double Word ................4 12......................Exception Bit Unordered.........................................................11-2 SHR_DI Shift Right Double Integer...........................10-4 CALL_FC Call FC from Box .................10-14 ---(MCR>) Master Control Relay Off ........................................8 10......................................2..3 10.............11-1 Overview of Shift Instructions.............................................12-12 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 xI ...10-8 CALL_SFC Call System FC from Box .......7 11..............................9 12.........................11-1 SHR_I Shift Right Integer...................3 Shift Instructions...........10-10 Call Multiple Instance .......3 12....Exception Bit Overflow Stored ...................................2........12-7 <>0 ---| |--.......................................................................1......................................9-1 10-1 10 Program Control Instructions 10...........................................................

............... A-1 LAD Instructions Sorted According to German Mnemonics (SIMATIC) ................................... B-13 C-1 C Working with Ladder Logic C.............................................. B-10 Example: Integer Math Instructions.5 14.........................14-6 WXOR_DW (Word) Exclusive OR Double Word .................................................................................................. B-6 Example: Counter and Comparison Instructions ...............14-5 WXOR_W (Word) Exclusive OR Word .........................2 13.....................14-3 WAND_DW (Word) AND Double Word ................................................................2 B................13-9 S_ODTS Retentive On-Delay S5 Timer.....................................................11 13...................................................................................7 13.................. C-1 Adder with EN and with ENO Connected ..............14-7 A-1 A Overview of All LAD Instructions A...8 13..................................1 14..9 13......................................................................................................................................... B-1 Example: Bit Logic Instructions ..............13-7 S_ODT On-Delay S5 Timer .................................................5 B.............3 C....... C-4 Index xii Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 ......14-1 WAND_W (Word) AND Word.13-2 S_PULSE Pulse S5 Timer ...................3 B......4 B.13-23 14-1 14 Word Logic Instructions 14............................ C-4 Parameter Transfer ......1........................................................................................................................................................1 C....2 EN/ENO Mechanism ...............................................13-13 ---( SP ) Pulse Timer Coil ......................13-1 Location of a Timer in Memory and Components of a Timer........................................................13-5 S_PEXT Extended Pulse S5 Timer ........................................... C-2 Adder with EN and without ENO Connected ....................................... C-3 Adder without EN and with ENO Connected .....2 C.......................................13-19 ---( SS ) Retentive On-Delay Timer Coil ....................................... A-5 B-1 B Programming Examples B...1 A........12 13-1 Overview of Timer Instructions....................10 13.....6 13...............................1 C......5 13.6 14...............................................................1...............................................................6 Overview of Programming Examples....1 B.1.........3 13.14-4 WOR_DW (Word) OR Double Word....................... C-3 Adder without EN and without ENO Connected ... B-2 Example: Timer Instructions..........3 14. B-12 Example: Word Logic Instructions............4 C......................................2 LAD Instructions Sorted According to English Mnemonics (International) ...............13-11 S_OFFDT Off-Delay S5 Timer ............................................13-21 ---( SF ) Off-Delay Timer Coil ..................2 14.............14-2 WOR_W (Word) OR Word ...................................1 13...........4 13.........................................................13-15 ---( SE ) Extended Pulse Timer Coil.....................................13-17 ---( SD ) On-Delay Timer Coil....1...........4 14....................7 Overview of Word logic instructions .......................................................Contents 13 Timer Instructions 13.......................................................................................................

1 1. These two digits form the base of a number system called the binary system. These combinations produce a result of 1 or 0 that is called the “result of logic operation” (RLO). In the world of contacts and coils. a 1 indicates activated or energized. The logic operations that are triggered by the bit logic instructions perform a variety of functions.1 Bit Logic Instructions Overview of Bit Logic Instructions Description Bit logic instructions work with two digits.Invert Power Flow The following instructions react to an RLO of 1: • • • • ---( S ) ---( R ) SR RS Set Coil Reset Coil Set-Reset Flip Flop Reset-Set Flip Flop Other instructions react to a positive or negative edge transition to perform the following functions: • • • • • • ---(N)-----(P)--NEG POS Negative RLO Edge Detection Positive RLO Edge Detection Address Negative Edge Detection Address Positive Edge Detection Immediate Read Immediate Write Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 1-1 . The two digits 1 and 0 are called binary digits or bits. 1 and 0. There are bit logic instructions to perform the following functions: • • • • • • • ---| |-----| / |--XOR ---( ) ---( # )--Normally Open Contact (Address) Normally Closed Contact (Address) Bit Exclusive OR Output Coil Midline Output ---(SAVE) Save RLO into BR Memory ---|NOT|--. and a 0 indicates not activated or not energized. The bit logic instructions interpret signal states of 1 and 0 and combine them according to Boolean logic.

0 and I0. T. it is linked to the RLO by OR logic.2 Symbol ---| |--. C Description Checked bit Description ---| |--. Otherwise. the contact is open.2 1-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .(Normally Open Contact) is closed when the bit value stored at the specified <address> is equal to "1".Bit Logic Instructions 1. M.0 I 0. Q. power does not flow across the contact and the result of logic operation (RLO) = "0".1 I 0.Normally Open Contact (Address) <address> ---| |--Parameter <address> Data Type BOOL Memory Area I. When used in series.1 Or the signal state is "1" at input I0. ---| |--.is linked to the RLO bit by AND logic. D. When used in parallel. When the contact is closed. When the contact is open. L. Status word BR writes: CC 1 CC 0 OV OS OR X STA X RLO X /FC 1 Example I 0. ladder rail power flows across the contact and the result of logic operation (RLO) = "1".2 Power flows if one of the following conditions exists: The signal state is "1" at inputs I0. if the signal state at the specified <address> is "0".

Q. When the contact is closed.1 Power flows if one of the following conditions exists: The signal state is "1" at inputs I0.2 I 0.Normally Closed Contact (Address) <address> ---| / |--Parameter <address> Data Type BOOL Memory Area I.2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 1-3 . M. When used in parallel. C Description Checked bit Description ---| / |--. power does not flow across the contact and the result of logic operation (RLO) = "0". L.is linked to the RLO bit by AND logic.Bit Logic Instructions 1. T.0 I 0. the contact is opened. if the signal state at the specified <address> is "1".3 Symbol ---| / |--. When used in series. Status word BR writes: CC 1 CC 0 OV OS OR X STA X RLO X /FC 1 Example I 0. ---| / |--. it is linked to the RLO by OR logic.(Normally Closed Contact) is closed when the bit value stored at the specified <address> is equal to "0". When the contact is opened.1 Or the signal state is "1" at input I0.0 and I0. ladder rail power flows across the contact and the result of logic operation (RLO) = "1". Otherwise. D.

Q.Bit Logic Instructions 1.0 I 0.0 I 0.0 = "1" AND I0. C Scanned bit Description XOR (Bit Exclusive OR) creates an RLO of "1" if the signal state of the two specified bits is different. L.0 = "0" AND I0.1 Q 4.0 I 0. D. 1-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . Symbols <address1> <address2> <address1> <address2> Parameter <address1> <address2 Data Type BOOL BOOL Memory Area Description I. M.1 The output Q4. Example I 0. L. C Scanned bit I. Q. T. T.0 is "1" if (I0. a network of normally open and normally closed contacts must be created as shown below. M.4 XOR Bit Exclusive OR For the XOR function.1 = "1") OR (I0.1 = "0"). D.

2.0 I 0.Bit Logic Instructions 1.0 is "0" if one of the following conditions exists: The signal state is "1" at input I0.5 Symbol --|NOT|-.0 NOT Q 4.1 and I0.1 The signal state of output Q4. Status word BR writes: CC 1 CC 0 OV OS OR STA 1 RLO X /FC - Example I 0.Invert Power Flow ---|NOT|--- Description ---|NOT|--.2 I 0. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 1-5 .0 Or the signal state is "1" at inputs I0.(Invert Power Flow) negates the RLO bit.

the addressed bit is set to the current status of power flow. Within an activated MCR zone. the bit at location <address> is set to "0". M. 16) are possible (see example). A negated output can be created by using the --|NOT|--. Status word BR writes: CC 1 CC 0 OV OS OR 0 STA X RLO /FC 0 1-6 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . if the MCR is on and there is power flow to an output coil. If there is no power flow to the coil (RLO = 0). If there is power flow to the coil (RLO = 1).6 Symbol ---( ) Output Coil <address> ---( ) Data Type BOOL Memory Area I. Q. L. MCR (Master Control Relay) dependency MCR dependency is activated only if an output coil is placed inside an active MCR zone. the bit at location <address> is set to "1". a logic "0" is written to the specified address regardless of power flow status.Bit Logic Instructions 1. D Description Assigned bit Parameter <address> Description ---( ) (Output Coil) works like a coil in a relay logic diagram.(invert power flow) element. Multiple output elements (max. If the MCR is off. An output coil can only be placed at the right end of a ladder rung.

When MCR is off (=0).3 Q 4.1 Q 4.0 AND I0. Q4. Q4.1 OR the signal state is "0" at input I0. The signal state of output Q4.Bit Logic Instructions Example I 0.2.1 The signal state of output Q4.1 OR the signal state is "0" at input I0.0 AND I0.0 and Q4.0 is "1" if one of the following conditions exists: The signal state is "1" at inputs I0.3 If the example rungs are within an activated MCR zone: When MCR is on.2 I 0.0 I 0.0 I 0.2 AND "1" at input I0.1 are set according to power flow status as described above.1 is "1" if one of the following conditions exists: The signal state is "1" at inputs I0.1 are reset to 0 regardless of power flow. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 1-7 .0 and Q4.

The midline output element saves the logical result of the preceding branch elements. FB. if the MCR is on and there is power flow to a midline output coil. In series with other contacts.Midline Output <address> ---( # )--Parameter <address> Data Type BOOL Memory Area I.(invert power flow) element. A ---( # )--. Within an activated MCR zone. OB).(Midline Output) is an intermediate assigning element which saves the RLO bit (power flow status) to a specified <address>. MCR (Master Control Relay) dependency MCR dependency is activated only if a midline output coil is placed inside an active MCR zone.is inserted like a contact. A negated ---( # )--. Q.7 Symbol ---( # )--.Bit Logic Instructions 1. *L. ---( # )--. If the MCR is off.element may never be connected to the power rail or directly after a branch connection or at the end of a branch. M. D Description Assigned bit * An L area address can only be used if it is declared TEMP in the variable declaration table of a logic block (FC. Description ---( # )--. a logic "0" is written to the specified address regardless of power flow status. the addressed bit is set to the current status of power flow.can be created by using the ---|NOT|--. Status word BR writes: CC 1 CC 0 OV OS OR 0 STA X RLO /FC 1 1-8 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

A RLO of "0" (no power flow to the coil) has no effect and the state of the element’s specified address remains unchanged.1 M 0.0 I 2.1 M 0.2 I 1. If power flows to the coil (RLO is "1").Bit Logic Instructions Example I 1.1 I 2.8 Symbol ---( R ) Reset Coil <address> ---( R ) Parameter <address> Data Type BOOL Memory Area I. the specified <address> of the element is reset to "0".3 NOT M 1.0 (#) (#) (#) ( ) I 1. Q.3 M 1. M.0 I 1. T. if the MCR is on and there is power flow to a reset coil. the current state of the element’s specified address remains unchanged regardless of power flow status. L. the addressed bit is reset to the "0" state. C Description Reset bit Description ---( R ) (Reset Coil) is executed only if the RLO of the preceding instructions is "1" (power flows to the coil).1 NOT M 2. The <address> may also be a timer (T no.2 has the RLO of the entire bit logic combination 1. Within an activated MCR zone.) whose counter value is reset to "0".0 I 1.2 I 1. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 1-9 .) whose timer value is reset to "0" or a counter (C no.1 has the RLO M 2. MCR (Master Control Relay) dependency MCR dependency is activated only if a reset coil is placed inside an active MCR zone.0 I 1.2 NOT Q 4. D. If the MCR is off.0 has the RLO I 1.

2 Network 2 I 0.Bit Logic Instructions Status word BR writes: CC 1 CC 0 OV OS OR 0 STA X RLO /FC 0 Example Network 1 I 0. 1-10 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . Q4. If the RLO is "0".3 T1 R Network 3 I 0. Q4.4. and C1 are left unchanged regardless of RLO state (power flow status).4 C1 R The signal state of output Q4.1 Or the signal state is "0" at input I0. and C1 are reset as described above. the signal state of output Q4. T1.0 I 0. If the example rungs are within an activated MCR zone: When MCR is on. When MCR is off. T1.0.0 remains unchanged.1 Q 4.0 and I0.3. The signal state of timer T1 is only reset if: the signal state is "1" at input I0.2.0. The signal state of counter C1 is only reset if: the signal state is "1" at input I0.0 R I 0.0 is reset to "0" if one of the following conditions exists: The signal state is "1" at inputs I0.

If the RLO is "1" the specified <address> of the element is set to "1".Bit Logic Instructions 1.9 Symbol ---( S ) Set Coil <address> ---( S ) Parameter <address> Data Type BOOL Memory Area I. D Description Set bit Description ---( S ) (Set Coil) is executed only if the RLO of the preceding instructions is "1" (power flows to the coil). Q. Status word BR writes: CC 1 CC 0 OV OS OR 0 STA X RLO /FC 0 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 1-11 . the current state of the element’s specified address remains unchanged regardless of power flow status. Within an activated MCR zone. L. If the MCR is off. An RLO = 0 has no effect and the current state of the element’s specified address remains unchanged. MCR (Master Control Relay) dependency MCR dependency is activated only if a set coil is placed inside an active MCR zone. if the MCR is on and there is power flow to a set coil. M. the addressed bit is set to the "1" state.

Q4. D I.1 Q 4. L. M. D I. the signal state of output Q4. M.0 remains unchanged.2 The signal state of output Q4.10 Symbol RS Reset-Set Flip Flop <address> RS S R Q Parameter <address> S R Q Data Type BOOL BOOL BOOL BOOL Memory Area I.0 and I0. M. Q. Q.0 is left unchanged regardless of RLO state (power flow status). 1. When MCR is off.2. L. Q. If the RLO is "0". D I.0 I 0. L. M. Q. L. If the example rungs are within an activated MCR zone: When MCR is on.Bit Logic Instructions Example I 0.0 is "1" if one of the following conditions exists: The signal state is "1" at inputs I0.0 is set as described above.0 S I 0. Q4.1 Or the signal state is "0" at input I0. D Description Set or reset bit Enabled reset instruction Enabled reset instruction Signal state of <address> 1-12 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

0 and "0" at I0. Within an activated MCR zone. Otherwise. Q4. Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Example I 0. the set instruction dominates because of the order. The S (Set) and R (Reset) instructions are executed only when the RLO is "1". RLO "0" has no effect on these instructions and the address specified in the instruction remains unchanged. If the MCR is off.Bit Logic Instructions Description RS (Reset-Set Flip Flop) is reset if the signal state is "1" at the R input.0 is set and output Q4. When MCR is off.1 S M 0. nothing is changed. MCR (Master Control Relay) dependency MCR dependency is activated only if a RS flip flop is placed inside an active MCR zone. if the signal state is "0" at the R input and "1" at the S input.0 is "1". If both signal states are "1". Otherwise. the order is of primary importance. memory bit M0. Q4. the current state of the specified address remains unchanged regardless of input states. If the RLO is "1" at both inputs. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 1-13 .0 is left unchanged regardless of input states.1. so that this address remains set for the remainder of program scanning. If the example is within an activated MCR zone: When MCR is on. M0. if the signal state at input I0. the flip flop is set.0 I 0. and "0" at the S input. If both signal states are "0". The RS flip flop executes first the reset instruction then the set instruction at the specified <address>.0 is "0".0 is reset and output Q4.0 If the signal state is "1" at input I0.0 is set and Q4.0 is "1".0 RS Q R Q 4. if the MCR is on.1 is "1". memory bit M0. the addressed bit is reset to "0" or set to "1" as described above.0 is "0" and at I0.0 is reset or set as described above.

If the MCR is off. M. and "0" at the R input. Q. M. The S (Set) and R (Reset) instructions are executed only when the RLO is "1". MCR (Master Control Relay) dependency MCR dependency is activated only if a SR flip flop is placed inside an active MCR zone. Q. the flip flop is reset. If the RLO is "1" at both inputs. D I. RLO "0" has no effect on these instructions and the address specified in the instruction remains unchanged. D I. L. D I. Q. if the signal state is "0" at the S input and "1" at the R input. The SR flip flop executes first the set instruction then the reset instruction at the specified <address>. M. the addressed bit is set to "1" or reset to "0" as described above. Otherwise. D Description Set or reset bit Enable set instruction Enable reset instruction Signal state of <address> Description SR (Set-Reset Flip Flop) is set if the signal state is "1" at the S input.Bit Logic Instructions 1. Q. so that this address remains reset for the remainder of program scanning. the order is of primary importance. if the MCR is on . Status word BR writes: CC1 CC0 OV OS OR x STA x RLO x /FC 1 1-14 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . Within an activated MCR zone. the current state of the specified address remains unchanged regardless of input states. L.11 Symbol SR Set-Reset Flip Flop <address> SR S R Q Parameter <address> S R Q Data Type BOOL BOOL BOOL BOOL Memory Area I. L. L. M.

Q4. If the example is within an activated MCR zone: When MCR is on. If both signal states are "1". memory bit M0.0 I 0. When MCR is off.1.0 is "0" and at I0.0 If the signal state is "1" at input I0. nothing is changed. the reset instruction dominates because of the order. if the signal state at input I0. If both signal states are "0".1 is "1".0 is "0".0 is left unchanged regardless of input states. Otherwise.0 is reset and output Q4.0 is set and output Q4.0 is reset and Q4.1 R M 0.0 is set or reset as described above. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 1-15 .Bit Logic Instructions Example I 0. Q4.0 SR Q S Q 4. M0.0 is "1". memory bit M0.0 is "0".0 and "0" at I0.

and "0" in all other cases. storing the previous signal state of RLO Description ---( N )--.Bit Logic Instructions 1.2 The edge memory bit M0. When there is a signal change at the RLO from "1" to "0".0 saves the old RLO state. the RLO will be "1" (pulse) after this instruction. If the signal state of the address is "1" and the RLO was "0" before the instruction. the edge memory bit.0 N CAS1 JMP I 0. L. Q.(Negative RLO Edge Detection) detects a signal change in the address from "1" to "0" and displays it as RLO = "1" after the instruction.1 M 0. the program jumps to label CAS1.0 I 0.12 Symbol ---( N )--. The current signal state in the RLO is compared with the signal state of the address. M. The RLO prior to the instruction is stored in the address.Negative RLO Edge Detection <address> ---( N ) Parameter <address> Data Type BOOL Memory Area I. Status word BR writes: CC 1 CC 0 OV OS OR 0 STA x RLO x /FC 1 Example I 0. D Description Edge memory bit. 1-16 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

The RLO prior to the instruction is stored in the address. Q. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 1-17 . the RLO will be "1" (pulse) after this instruction.2 I 0. Status word BR writes: CC1 CC0 OV OS OR 0 STA X RLO X /FC 1 Example I 0. storing the previous signal state of RLO Description ---( P )--. D Description Edge memory bit.(Positive RLO Edge Detection) detects a signal change in the address from "0" to "1" and displays it as RLO = "1" after the instruction.0 saves the old RLO state. When there is a signal change at the RLO from "0" to "1".13 Symbol ---( P )--. the program jumps to label CAS1. L. and "0" in all other cases. the edge memory bit.1 M 0.0 I 0. The current signal state in the RLO is compared with the signal state of the address. If the signal state of the address is "0" and the RLO was "1" before the instruction.Bit Logic Instructions 1.0 CAS1 P JMP The edge memory bit M0. M.Positive RLO Edge Detection <address> ---( P )--Parameter <address> Data Type BOOL Memory Area I.

0 I 0. STL). Status word BR writes: X CC 1 CC 0 OV OS OR STA RLO /FC - Example I 0. For the instruction "SAVE" (LAD. 1-18 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . For this reason.2 I 0. since the ENO output (= BR bit) is then set to the value of the RLO bit and you can then check for errors in the block. the following applies and not the recommended use specified in the manual and online help: We do not recommend that you use SAVE and then check the BR bit in the same block or in subordinate blocks.Bit Logic Instructions 1.14 Symbol ---(SAVE) Save RLO into BR Memory ---( SAVE ) Description ---(SAVE) (Save RLO into BR Memory) saves the RLO to the BR bit of the status word.1 SAVE The status of the rung (=RLO) is saved to the BR bit. FBD. It is advisable to use the SAVE instruction before exiting a block. The first check bit /FC is not reset. the status of the BR bit is included in the AND logic operation in the next network. because the BR bit can be modified by many instructions occurring inbetween.

2 M 0. M. D Description Scanned signal M_BIT edge memory bit. L. M. Q. L. If the current RLO state is "1" and the previous state was "0" (detection of rising edge).4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 1-19 . D I. storing the previous signal state of <address1> One shot output Q BOOL I.15 Symbol NEG Address Negative Edge Detection <address1> NEG <address2> M_BIT Q Parameter <address1> <address2> Data Type BOOL BOOL Memory Area I.0 is "1" if the following conditions exist: • • • The signal state is "1" at inputs I0. Q.0 and I0.1 and I0.3 And the signal state is "1" at input I0.2 And there is a negative edge at input I0.0 I 0.0 I 0. Status word BR writes: x CC 1 CC 0 OV OS OR x STA 1 RLO x /FC 1 Example I 0.1 I 0. which is stored in <address2>. L. the RLO bit will be "1" after this instruction. Q.0 Q ( ) The signal state at output Q4.4 Q 4.Bit Logic Instructions 1. M. D Description NEG (Address Negative Edge Detection) compares the signal state of <address1> with the signal state from the previous scan.3 NEG M_BIT I 0.

D Description Scanned signal M_BIT edge memory bit. storing the previous signal state of <address1> One shot output Q BOOL I.3 And the signal state is "1" at input I0. D Description POS (Address Positive Edge Detection) compares the signal state of <address1> with the signal state from the previous scan.0 is "1" if the following conditions exist: • • • The signal state is "1" at inputs I0. Q. Q. L.3 POS M_BIT I 0.Bit Logic Instructions 1.0 and I0.4 1-20 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . If the current RLO state is "1" and the previous state was "0" (detection of rising edge).0 I 0. D I. which is stored in <address2>. L.0 I 0. M.1 and I0. the RLO bit will be "1" after this instruction.4 Q 4. Status word BR writes: x CC 1 CC 0 OV OS OR x STA 1 RLO x /FC 1 Example I 0.1 I 0.2 And there is a positive edge at input I0. Q.0 Q ( ) The signal state at output Q4.2 M 0. M. L. M.16 Symbol POS Address Positive Edge Detection <address1> POS <address2> M_BIT Q Parameter <address1> <address2> Data Type BOOL BOOL Memory Area I.

a single digital input cannot be read via a contact (bit) element.17 Immediate Read Description For the Immediate Read function. The peripheral input memory area can be read as a byte.Bit Logic Instructions 1. use the peripheral input (PI) memory area instead of the input (I) memory area. a network of symbols must be created as shown in the example below. Therefore. For time-critical applications. Otherwise. you must wait for the end of the next OB1 scan cycle when the I memory area is updated with the P memory state. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 1-21 . To conditionally pass voltage depending on the status of an immediate input: 1. An Immediate Read gets the state of a digital input from an input module at the time the Immediate Read rung is scanned. 2. A word of PI memory that contains the input data of concern is read by the CPU. or a double word. the current state of a digital input may be read faster than the normal case of once per OB1 scan cycle. The accumulator is tested for non-zero condition. a word. The word of PI memory is then ANDed with a constant that yields a non-zero result if the input bit is on ("1"). 3. To perform an immediate read of an input (or inputs) from an input module.

5 MWx * * MWx has to be specified in order to be able to store the network.1 I 4. The word PIW1 contains the immediate status of I1.1.5.1 and I4. x may be any permitted number.1 is in series with I4.1 PIW1 16#0002 WAND_W ENO EN IN1 OUT IN2 <>0 I 4.Bit Logic Instructions Example Ladder Network with Immediate Read of Peripheral Input I1. The contact A<>0 passes voltage if the result of the WAND_W instruction is not equal to zero. 1-22 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . The result is not equal to zero if I1. Description of WAND_W instruction: PIW1 W#16#0002 Result 0000000000101010 0000000000000010 0000000000000010 In this example immediate input I1.1 (second bit) in PB1 is true ("1"). PIW1 is ANDed with W#16#0002.

18 Immediate Write Description For the Immediate Write function. or a double word. For time-critical applications. a single digital output cannot be updated via a coil element. a word. a byte. the current state of a digital output may have to be sent to an output module faster than the normal case of once at the end of the OB1 scan cycle. you must wait for the end of the next OB1 scan cycle when the Q memory area is updated with the P memory state. The peripheral output memory area can be read as a byte. an external output module should only be referenced once in a program as a coil. Immediate Writes could cause dangerous conditions (transient pulses at outputs) to occur. ! Caution • • Since the entire byte of Q memory is written to an output module. As a general design rule. Therefore. most potential problems with immediate outputs can be avoided. word. use the peripheral output (PQ) memory area instead of the output (Q) memory area. all outputs bits in that byte are updated when the immediate output is performed. • Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 1-23 . If you follow this design rule. If an output bit has intermediate states (1/0) occurring throughout the program that should not be sent to the output module. To perform an immediate write of an output (or outputs) to an output module. or double word of Q memory that contains the relevant bit is conditionally copied to the corresponding PQ memory (direct output module addresses). Otherwise. To write the state of a digital output to an output module immediately.Bit Logic Instructions 1. An Immediate Write writes to a digital output to a input module at the time the Immediate Write rung is scanned. a network of symbols must be created as shown in the example below.

The result is not equal to zero if I1. The contact A<>0 passes voltage if the result of the WAND_W instruction is not equal to zero. channel 1. Q5. The byte PQB5 contains the immediate output status of the bit Q5. QB5 is copied to the corresponding direct peripheral output memory area (PQB5). 1-24 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .1. Network 1 I 0.1 (second bit) in PB1 is true ("1").Bit Logic Instructions Example Ladder network equivalent of Immediate Write to peripheral digital output module 5.1 in network 1. The bit states of the addressed output Q byte (QB5) are either modified or left unchanged.1. The other 7 bits in PQB5 are also updated by the MOVE (copy) instruction. PIW1 is ANDed with W#16#0002. The word PIW1 contains the immediate status of I1.1 is the desired immediate output bit.1 is assigned the signal state of I0.1 Network 2 MOVE ENO EN QB5 IN OUT PQB5 In this example Q5.1 Q 5.

1 Overview of Comparison Instructions Description IN1 and IN2 are compared according to the type of comparison you choose: == <> > < >= <= IN1 IN1 IN1 IN1 IN1 IN1 is equal to IN2 is not equal to IN2 is greater than IN2 is less than IN2 is greater than or equal to IN2 is less than or equal to IN2 If the comparison is true. It is linked to the RLO of a rung network by AND if the compare element is used in series. the RLO of the function is "1". or by OR if the box is used in parallel.2 Comparison Instructions 2. The following comparison instructions are available: • • • CMP ? I Compare Integer CMP ? D Compare Double Integer CMP ? R Compare Real Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 2-1 .

Q. M. If the comparison is true. Q. L. Q.1 AND MW0 >= MW2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 2-2 . L. Status word BR writes: x CC 1 x CC 0 x OV 0 OS OR 0 STA x RLO x /FC 1 Example I 0. D I. M.2 CMP ? I Compare Integer Symbols CMP == I IN1 IN2 CMP >I IN1 IN2 CMP >= I IN1 IN2 CMP <> I IN1 IN2 CMP <I IN1 IN2 CMP <= I IN1 IN2 Parameter box input box output Data Type BOOL BOOL Memory Area I. L. or by OR if the box is used in parallel. is only processed further if the RLO at the box input = 1 First value to compare Second value to compare IN1 IN2 INT INT I.0 S MW0 MW2 Output Q4. L.0 and at I0. IN1 and IN2 are compared according to the type of comparison you choose. D or constant I.1 CMP >= I IN1 IN2 Q 4.Comparison Instructions 2. the RLO of the function is "1". Q. It can be located at any position where a normal contact could be placed.0 is set if the following conditions exist: • • There is a signal state of "1" at inputs I0. M.0 I 0. It is linked to the RLO of the whole rung by AND if the box is used in series. M. D Description Result of the previous logic operation Result of the comparison. D or constant Description CMP ? I (Compare Integer) can be used like a normal contact.

Q. Q.0 is set if the following conditions exist: • • • There is a signal state of "1" at inputs I0. If the comparison is true. M. the RLO of the function is "1". IN1 and IN2 are compared according to the type of comparison you choose. D I. L. Status word BR writes: x CC 1 x CC 0 x OV 0 OS OR 0 STA x RLO x /FC 1 Example I 0.1 CMP >= D IN1 IN2 I 0. M. M.2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 2-3 . It can be located at any position where a normal contact could be placed. L.1 And MD0 >= MD4 And there is a signal state of"1" at input I0.2 Q 4. or by OR if the box is used in parallel.0 I 0.3 CMP ? D Compare Double Integer Symbols CMP == D IN1 IN2 CMP >D IN1 IN2 CMP >= D IN1 IN2 CMP <> D IN1 IN2 CMP <D IN1 IN2 CMP <= D IN1 IN2 Parameter box input box output IN1 IN2 Data Type BOOL BOOL DINT DINT Memory Area I.Comparison Instructions 2. D I. is only processed further if the RLO at the box input = 1 First value to compare Second value to compare Description CMP ? D (Compare Double Integer) can be used like a normal contact. L. Q. It is linked to the RLO of a rung network by AND if the compare element is used in series. D or constant I.0 S MD0 MD4 Output Q4.0 and at I0. Q. M. L. D or constant Description Result of the previous logic operation Result of the comparison.

M. M. L. M. D or constant Description Result of the previous logic operation Result of the comparison. D I. IN1 and IN2 are compared according to the type of comparison you choose.1 CMP >= R IN1 IN2 I 0. D or constant I. It can be located at any position where a normal contact could be placed. the RLO of the function is "1". Q.Comparison Instructions 2. L. If the comparison is true.4 CMP ? R Compare Real Symbols CMP == R IN1 IN2 CMP >R IN1 IN2 CMP >= R IN1 IN2 CMP <> R IN1 IN2 CMP <R IN1 IN2 CMP <= R IN1 IN2 Parameter box input box output IN1 IN2 Data Type BOOL BOOL REAL REAL Memory Area I. M. Q. Q.2 Q 4.0 S MD0 MD4 Output Q4.2 2-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . or by OR if the box is used in parallel. L. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Example I 0.1 And MD0 >= MD4 And there is a signal state of"1" at input I0. L.0 is set if the following conditions exist: • • • There is a signal state of "1" at inputs I0. It is linked to the RLO of the whole rung by AND if the box is used in series.0 I 0. is only processed further if the RLO at the box input = 1 First value to compare Second value to compare Description CMP ? R (Compare Real) can be used like a normal contact. Q.0 and at I0. D I.

The result can be queried at the parameter OUT. The following conversion instructions are available: • • • • • • • • • • • • • • • BCD_I I_BCD BCD_DI I_DINT DI_BCD DI_REAL BCD to Integer Integer to BCD BCD to Double Integer Integer to Double Integer Double Integer to BCD Double Integer to Floating-Point INV_I INV_DI NEG_I NEG_DI Ones Complement Integer Ones Complement Double Integer Twos Complement Integer Twos Complement Double Integer NEG_R ROUND TRUNC CEIL FLOOR Negate Floating-Point Number Round to Double Integer Truncate Double Integer Part Ceiling Floor Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 3-1 .3 Conversion Instructions 3.1 Overview of Conversion Instructions Description The conversion instructions read the contents of the parameters IN and convert these or change the sign.

Q. D I.0 is "1" . L. ENO always has the same signal state as EN.0 is "1" if the conversion is not executed (ENO = EN = 0). Q. D Description Enable input Enable output BCD number Integer value of BCD number Description BCD_I (Convert BCD to Integer) reads the contents of the IN parameter as a threedigit. 3-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . Status word BR writes: 1 CC 1 CC 0 OV OS OR 0 STA 1 RLO 1 /FC 1 Example I 0. Q.0 NOT MW12 If input I0. The output Q4. M. M. Q. M. D I. M.999) and converts it to an integer value (16-bit). The integer result is output by the parameter OUT. then the content of MW10 is read as a three-digit BCD coded number and converted to an integer. L.Conversion Instructions 3.2 Symbol BCD_I BCD to Integer BCD_I EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL WORD INT Memory Area I.0 MW10 BCD_I EN ENO IN OUT Q 4. BCD coded number (+/. The result is stored in MW12. L. D I. L.

L. M. Q. M.3 Symbol I_BCD Integer to BCD I_BCD EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL INT WORD Memory Area I. M. or the instruction was not executed (I0. D I. D I. M. If an overflow occurred. ENO will be "0". D I. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 3-3 . Status word BR writes: x CC 1 CC 0 OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. then the content of MW10 is read as an integer and converted to a three-digit BCD coded number. Q. L.0 is "1" if there was an overflow.0 is "1".0 NOT MW12 If I0.999). Q. The result is output by the parameter OUT. D Description Enable input Enable output Integer number BCD value of integer number Description I_BCD (Convert Integer to BCD) reads the content of the IN parameter as an integer value (16-bit) and converts it to a three-digit BCD coded number (+/.0 = 0). The output Q4. Q. L. L.Conversion Instructions 3. The result is stored in MW12.0 MW10 I_BCD EN ENO IN OUT Q 4.

4 Symbol I_DINT Integer to Double Integer I_DINT EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL INT DINT Memory Area I. The result is stored in MD12. L.0 NOT MD12 If I0. Q. then the content of MW10 is read as an integer and converted to a double integer. D I. L.Conversion Instructions 3. D I. The output Q4. Q. M. M. L. M. The result is output by the parameter OUT. Status word BR writes: 1 CC 1 CC 0 OV OS OR 0 STA 1 RLO 1 /FC 1 Example I 0. Q. M.0 is "1". ENO always has the same signal state as EN. 3-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . D I. Q.0 MW10 I_DINT EN ENO IN OUT Q 4.0 is "1" if the conversion is not executed (ENO = EN = 0). D Description Enable input Enable output Integer value to convert Double integer result Description I_DINT (Convert Integer to Double Integer) reads the content of the IN parameter as an integer (16-bit) and converts it to a double integer (32-bit). L.

M.0 NOT MD12 If I0. Status word BR writes: 1 CC 1 CC 0 OV OS OR 0 STA 1 RLO 1 /FC 1 Example I 0. then the content of MD8 is read as a seven-digit BCD coded number and converted to a double integer. L.0 is "1" . Q. L. M. L. D I. Q. D I.0 MD8 BCD_DI EN ENO IN OUT Q 4. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 3-5 .5 Symbol BCD_DI BCD to Double Integer BCD_DI EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL DWORD DINT Memory Area I. The output Q4.9999999) and converts it to a double integer value (32-bit). D Description Enable input Enable output BCD number Double integer value of BCD number Description BCD_DI (Convert BCD to Double Integer) reads the content of the IN parameter as a seven-digit. L.0 is "1" if the conversion is not executed (ENO = EN = 0). D I. Q. Q. BCD coded number (+/. The result is stored in MD12. M. M.Conversion Instructions 3. ENO always has the same signal state as EN. The double integer result is output by the parameter OUT.

M. M. D I.0 is "1". If an overflow occurred. D I. D Description Enable input Enable output Double integer number BCD value of a double integer number Description DI_BCD (Convert Double Integer to BCD) reads the content of the IN parameter as a double integer (32-bit) and converts it to a seven-digit BCD coded number (+/9999999). L. 3-6 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . Q. The result is output by the parameter OUT. ENO will be "0". Status word BR writes: x CC 1 CC 0 OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. or the instruction was not executed (I0. The output Q4.Conversion Instructions 3. Q. M. The result is stored in MD12.0 = 0). then the content of MD8 is read as a double integer and converted to a seven-digit BCD number. L.0 is "1" if an overflow occurred. L. D I. M. Q. Q.0 MD8 DI_BCD EN ENO IN OUT Q 4.0 NOT MD12 If I0. L.6 Symbol DI_BCD Double Integer to BCD DI_BCD EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL DINT DWORD Memory Area I.

7 Symbol DI_REAL Double Integer to Floating-Point DI_REAL EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL DINT REAL Memory Area I. L. Q. M. The output Q4. M. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 3-7 .0 is "1". D I. Q. The result is output by the parameter OUT. Status word BR writes: 1 CC 1 CC 0 OV OS OR 0 STA 1 RLO 1 /FC 1 Example I 0. D I. D I. then the content of MD8 is read as an double integer and converted to a floating-point number.0 NOT MD12 If I0. The result is stored in MD12.Conversion Instructions 3. D Description Enable input Enable output Double integer value to convert Floating-point number result Description DI_REAL (Convert Double Integer to Floating-Point) reads the content of the IN parameter as a double integer and converts it to a floating-point number. L.0 MD8 DI_REAL EN ENO IN OUT Q 4.0 is "1" if the conversion is not executed (ENO = EN = 0). M. L. M. Q. Q. ENO always has the same signal state as EN. L.

The output Q4. L. L. M.0 is "1". ENO always has the same signal state as EN. Q. D I.8 Symbol INV_I Ones Complement Integer INV_I EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL INT INT Memory Area I. This instruction changes every bit to its opposite state. Q. Status word BR writes: 1 CC 1 CC 0 OV OS OR 0 STA 1 RLO 1 /FC 1 Example I 0. Q. then every bit of MW8 is reversed.Conversion Instructions 3. L. 3-8 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . for example: MW8 = 01000001 10000001 results in MW10 = 10111110 01111110. M. M. D Description Enable input Enable output Integer input value Ones complement of the integer IN Description INV_I (Ones Complement Integer) reads the content of the IN parameter and performs a Boolean XOR function with the hexadecimal mask W#16#FFFF. D I. Q.0 NOT MW10 If I0. M.0 is "1" if the conversion is not executed (ENO = EN = 0). L. D I.0 MW8 INV_I EN ENO IN OUT Q 4.

0 is "1" if the conversion is not executed (ENO = EN = 0). for example: MD8 = F0FF FFF0 results in MD12 = 0F00 000F. M. then every bit of MD8 is reversed. L.0 NOT MD12 If I0. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 3-9 . M. D I. L. D I.Conversion Instructions 3.0 MD8 INV_DI EN ENO IN OUT Q 4. ENO always has the same signal state as EN. The output Q4. M. Q.0 is "1". Q. Q.This instruction changes every bit to its opposite state. D I. Status word BR writes: 1 CC 1 CC 0 OV OS OR 0 STA 1 RLO 1 /FC 1 Example I 0. Q. L. M. D Description Enable input Enable output Double integer input value Ones complement of the double integer IN Description INV_DI (Ones Complement Double Integer) reads the content of the IN parameter and performs a Boolean XOR function with the hexadecimal mask W#16#FFFF FFFF .9 Symbol INV_DI Ones Complement Double Integer INV_DI EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL DINT DINT Memory Area I. L.

M. the signal state of ENO = 0. M. D I.0 NOT MW10 If I0. The twos complement instruction is equivalent to multiplication by (-1) and changes the sign (for example: from a positive to a negative value).0 is "1" if the conversion is not executed (ENO = EN = 0). then the value of MW8 with the opposite sign is output by the OUT parameter to MW10. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. Q.10 Symbol NEG_I Twos Complement Integer NEG_I EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL INT INT Memory Area I.0 is "1". L. L. D I.10. D I. Q. 3-10 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .Conversion Instructions 3. The output Q4. Q. Q. L. D Description Enable input Enable output Integer input value Twos complement of integer IN Description NEG_I (Twos Complement Integer) reads the content of the IN parameter and performs a twos complement instruction. L. ENO always has the same signal state as EN with the following exception: if the signal state of EN = 1 and an overflow occurs. the signal state of ENO = 0. MW8 = + 10 results in MW10 = . If the signal state of EN = 1 and an overflow occurs. M. M.0 MW8 NEG_I EN ENO IN OUT Q 4.

M.1000. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. D Description Enable input Enable output Double integer input value Twos complement of IN value Description NEG_DI (Twos Complement Double Integer) reads the content of the IN parameter and performs a twos complement instruction. then the value of MD8 with the opposite sign is output by the OUT parameter to MD12. ENO always has the same signal state as EN with the following exception: if the signal state of EN = 1 and an overflow occurs. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 3-11 . The twos complement instruction is equivalent to multiplication by (-1) and changes the sign (for example: from a positive to a negative value). D I. L. D I. the signal state of ENO = 0. M. M. Q.0 is "1". If the signal state of EN = 1 and an overflow occurs. D I.Conversion Instructions 3. The output Q4. Q. L. the signal state of ENO = 0. M.0 is "1" if the conversion is not executed (ENO = EN = 0). Q.0 MD8 NEG_DI EN ENO IN OUT Q 4. L. Q. L.0 NOT MD12 If I0. MD8 = + 1000 results in MD12 = .11 Symbol NEG_DI Twos Complement Double Integer NEG_DI EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL DINT DINT Memory Area I.

Status word BR writes: x CC 1 CC 0 OV OS OR 0 STA x RLO x /FC 1 Example I 0. Q. then the value of MD8 with the opposite sign is output by the OUT parameter to MD12. L. 3-12 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . D I. Q. D I.0 MD8 NEG_R EN ENO IN OUT Q 4.0 is "1" if the conversion is not executed (ENO = EN = 0).234. M.0 NOT MD12 If I0. The output Q4. ENO always has the same signal state as EN. D Description Enable input Enable output Floating-point number input value Floating-point number IN with negative sign Description NEG_R (Negate Floating-Point) reads the contents of the IN parameter and changes the sign. M. L.234 results in MD12 = . M. Q. L. D I.12 Symbol NEG_R Negate Floating-Point Number NEG_R EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL REAL Memory Area I. L.0 is "1". M. The instruction is equivalent to multiplication by (-1) and changes the sign (for example: from a positive to a negative value).Conversion Instructions 3. MD8 = + 6. Q.6.

L. If the floating-point number lies between two integers. Q. D I. Q. L. The result is output by the parameter OUT. L. Status word BR writes: x CC 1 CC 0 OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 3-13 . D Description Enable input Enable output Value to round IN rounded to nearest whole number Description ROUND (Round Double Integer) reads the content of the IN parameter as a floating-point number and converts it to a double integer (32-bit). the even number is returned. M. M.0 is "1" if an overflow occurred or the instruction was not executed (I0. then the content of MD8 is read as a floating-point number and converted to the closest double integer.13 Symbol ROUND Round to Double Integer ROUND EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL DINT Memory Area I. D I.0 MD8 ROUND EN ENO IN OUT Q 4. L. M.0 is "1". If an overflow occurred ENO will be "0".Conversion Instructions 3. Q. Q.0 = 0). The result of this "Round to nearest" function is stored in MD12. D I. The output Q4.0 NOT MD12 If I0. M. The result is the closest integer number ("Round to nearest").

L. then the content of MD8 is read as a real number and converted to a double integer.0 MD8 TRUNC EN ENO IN OUT Q 4. The integer part of the floating-point number is the result and is stored in MD12. Q.0 NOT MD12 If I0. M. ENO will be "0". D I. Status word BR writes: x CC 1 CC 0 OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. D I. The double integer result of the ("Round to zero mode") is output by the parameter OUT. Q. 3-14 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . Q. D I.0 is "1" if an overflow occurred. If an overflow occurred. L. M.Conversion Instructions 3. D Description Enable input Enable output Floating-point value to convert Whole number part of IN value Description TRUNC (Truncate Double Integer) reads the content of the IN parameter as a floating-point number and converts it to a double integer (32-bit). The output Q4. L. or the instruction was not executed (I0.0 = 0).14 Symbol TRUNC Truncate Double Integer Part TRUNC EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL DINT Memory Area I. M. M. Q. L.0 is "1".

0 = 0). L. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 3-15 . M.15 Symbol CEIL Ceiling CEIL EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL DINT Memory Area I. D I.0 NOT MD12 If I0. M. The result is stored in MD12.Conversion Instructions 3. L. If an overflow occurs. Status word BR writes *: X writes **: 0 CC 1 CC 0 OV X OS X OR 0 0 STA X 0 RLO X 0 /FC 1 1 * Function is executed (EN = 1) ** Function is not executed (EN = 0) Example I 0.0 is "1" if an overflow occured or the instruction was not processed (I0. D Description Enable input Enable output Floating-point value to convert Lowest greater double integer Description CEIL (Ceiling) reads the contents of the IN parameter as a floating-point number and converts it to a double integer (32-bit). M. Q. The output Q4. Q. the contents of MD8 are read as a floating-point number which is converted into a double integer using the function Round.0 MD8 CEIL EN ENO IN OUT Q 4. Q. ENO will be "0". L. The result is the lowest integer which is greater than the floating-point number ("Round to + infinity"). M. D I. L. D I. Q.0 is 1.

0 NOT MD12 If I0. D I. The result is the greatest integer component which is lower than the floating-point number ("Round to .0 MD8 FLOOR EN ENO IN OUT Q 4. 3-16 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . Status word BR writes: x CC 1 CC 0 OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. L. The output Q4. D I. The result is stored in MD12.0 is "1" if an overflow occurred.Conversion Instructions 3. L. Q. Q.0 = 0).infinity mode. M. Q. M. or the instruction was not executed (I0. D I. then the content of MD8 is read as a floating-point number and converted to a double integer by the round to .0 is "1". D Description Enable input Enable output Floating-point value to convert Greatest lower double integer Description FLOOR (Floor) reads the content of the IN parameter as a floating-point number and converts it to a double integer (32-bit). L.infinity"). If an overflow occurred ENO will be "0". M. M.16 Symbol FLOOR Floor FLOOR EN IN ENO OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL DINT Memory Area I. L. Q.

You can vary the count value within this range by using the following counter instructions: • • • • • • S_CUD S_CD S_CU ---( SC ) ---( CU ) ---( CD ) Up-Down Counter Down Counter Up Counter Set Counter Coil Up Counter Coil Down Counter Coil Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 4-1 . The ladder logic instruction set supports 256 counters.4 Counter Instructions 4. This memory area reserves one 16-bit word for each counter address. The count value is moved to the counter word when a counter is set. The counter instructions are the only functions that have access to the counter memory area. Count Value Bits 0 through 9 of the counter word contain the count value in binary code. The range of the count value is 0 to 999.1 Overview of Counter Instructions Area in Memory Counters have an area reserved for them in the memory of your CPU.

Bits 0 through 11 of the counter contain the count value in binary coded decimal format. for example 127. in the following format: C#127. The following figure shows the contents of the counter after you have loaded the count value 127. and the contents of the counter cell after the counter has been set.Counter Instructions Bit Configuration in the Counter You provide a counter with a preset value by entering a number from 0 to 999. 15 14 13 12 11 10 0 0 9 0 8 1 7 0 6 0 5 1 4 0 3 0 2 1 1 1 0 1 irrelevant 1 2 Count value in BCD (0 to 999) 7 15 14 13 12 11 10 9 0 8 0 7 0 6 1 5 1 4 1 3 1 2 1 1 1 0 1 irrelevant Binary count value 4-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . The C# stands for binary coded decimal format (BCD format: each set of four bits contains the binary code for one decimal value).

M. L. D I. M. BCD coded Status of the counter CU CD S PV ZV ZR S ZW BOOL BOOL BOOL WORD I. Q. M. M. L. Q. Q. L. Q.2 Symbol S_CUD Up-Down Counter English C no. Q. Q. L.Counter Instructions 4. L. Q. L. M. D I. D PV R CV CV_BCD Q ZW R DUAL DEZ Q WORD BOOL WORD WORD BOOL Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 4-3 . M. Q. M. D I. L. range depends on CPU Count up input Count down input Set input for presetting counter Enter counter value as C#<value> in the range from 0 to 999 Value for presetting counter Reset input Current counter value. D I. D I. S_CUD CU Q CV CV_BCD German Z no. D or constant I. Q. Parameter German Z no. D I. D I. L. ZAEHLER ZV ZR S ZW R DUAL DEZ Q CD S PV R Parameter English C no. M. L. M. Data Type COUNTER Memory Area Description C Counter identification number. hexadecimal number Current counter value.

the counter is preset with the value of MW10.1 changes from "0" to "1". Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Note Avoid to use a counter at several program points (risk of counting errors). If I0. If the signal state of I0. both instructions are executed and the count value remains unchanged.Counter Instructions Description S_CUD (Up-Down Counter) is preset with the value at input PV if there is a positive edge at input S. If there is a 1 at input R. even if there was no change from a positive to a negative edge or viceversa.0 I 0.except when the value of C10 is equal than "999". 4-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . the counter is reset and the count is set to zero. If the counter is set and if RLO = 1 at the inputs CU/CD. the value of counter C10 will be incremented by one .0 I 0.2 S CV CV_BCD CU CD Q Q 4.3 MW10 PV R If I0.0 is "1" if C10 is not equal to zero. The counter is decremented by one if there is a positive edge at input CD and the value of the counter is greater than "0". C10 is decremented by one . The counter is incremented by one if the signal state at input CU changes from "0" to "1" and the value of the counter is less than "999". If there is a positive edge at both count inputs.2 changes from "0" to "1". The signal state at output Q is "1" if the count is greater than zero and "0" if the count is equal to zero.1 I 0.0 changes from "0" to "1". the counter will count accordingly in the next scan cycle. Example C10 S_CUD I 0.except when the value of C10 is equal to "0". Q4.

The counter is reset if there is a "1" at input R and the count value is then set to zero.Counter Instructions 4. M.3 Symbol S_CU Up Counter English C no. If the counter is set and if RLO = 1 at the inputs CU. L. L. D Counter identification number. M. L. Q. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 4-5 . Q. the counter will count accordingly in the next scan cycle. D I. Z_VORW ZV S ZW R DUAL DEZ Q S PV Parameter English C no. range depends of CPU Count up input Set input for presetting counter Enter counter value as C#<value> in the range from 0 to 999 Value for presetting counter Reset input Current counter value. L. M. Q. L. ZV S ZW Data Type COUNTER BOOL BOOL WORD Memory Area Description C I. M. M. BCD coded Status of the counter PV R CV CV_BCD Q ZW R DUAL DEZ Q WORD BOOL WORD WORD BOOL Description S_CU (Up Counter) is preset with the value at input PV if there is a positive edge at input S. Q. M. L. CU S PV Parameter German Z no. D I. Q. Q. D I. L. even if there was no change from a positive to a negative edge or viceversa. Q. D I. S_CU CU Q CV CV_BCD R German Z no. Q. M. The signal state at output Q is "1" if the count is greater than zero and "0" if the count is equal to zero. The counter is incremented by one if the signal state at input CU changes from "0" to "1" and the value of the counter is less than "999". D I. L. M. D or constant I. hexadecimal number Current counter value. D I.

Q4. the value of counter C10 will be incremented by one . 4-6 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .0 CU Q Q 4. the counter is preset with the value of MW10.2 S I 0. Example C10 S_CU I 0.0 I 0. If the signal state of I0.Counter Instructions Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Note Avoid to use a counter at several program points (risk of counting errors).3 MW10 PV R CV CV_BCD If I0.unless the value of C10 is equal to "999".0 is "1" if C10 is not equal to zero.2 changes from "0" to "1".0 changes from "0" to "1".

M. L. CD S PV Parameter German Z no. Q. S_CD CD Q CV CV_BCD R German Z no. BCD coded Status counter PV R CV CV_BCD Q ZW R DUAL DEZ Q WORD BOOL WORD WORD BOOL Description S_CD (Down Counter) is set with the value at input PV if there is a positive edge at input S. ZR S ZW Data Type COUNTER BOOL BOOL WORD Memory Area Description C I. Q.Counter Instructions 4. D I. D I. Q. L. range depends of CPU Count down input Set input for presetting counter Enter counter value as C#<value> in the range from 0 to 999 Value for presetting counter Reset input Current counter value. D I. M. D or constant I. The counter is reset if there is a 1 at input R and the count value is then set to zero. the counter will count accordingly in the next scan cycle. L. M. D I. M. The counter is decremented by one if the signal state at input CD changes from "0" to "1" and the value of the counter is greater than zero. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 4-7 . If the counter is set and if RLO = 1 at the inputs CD. D Counter identification number. L.4 Symbol S_CD Down Counter English C no. D I. L. Q. Q. L. M. D I. L. hexadecimal number Current counter value. Z_RUECK ZR S ZW R DUAL DEZ Q S PV Parameter English C no. even if there was no change from a positive to a negative edge or viceversa. The signal state at output Q is "1" if the count is greater than zero and "0" if the count is equal to zero. Q. M. M. M. Q. L. Q.

4-8 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .0 changes from "0" to "1".0 I 0. If the signal state of I0.0 CD Q Q 4.2 S I 0. Example C10 C_CD I 0.2 changes from "0" to "1". the value of counter C10 will be decremented by one .unless the value of C10 is equal to "0".Counter Instructions Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Note Avoid to use a counter at several program points (risk of counting errors). Q4.3 MW10 PV R CV CV_BCD If I0.0 is "1" if C10 is not equal to zero. the counter is preset with the value of MW10.

Status word BR writes: x CC 1 CC 0 OV OS OR 0 STA x RLO /FC 0 Example I 0. M.> <preset value> Data Type COUNTER WORD Memory Area Description C I. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 4-9 . Q. the preset value transferred into the specified counter.0 (change from "0" to "1").> <preset value> Parameter German <Z no.Counter Instructions 4. the value of counter C5 remains unchanged.5 Symbol ---( SC ) Set Counter Value English <C no.> ---( SC ) German <Z no. D or constant Counter number to be preset Value for presetting BCD (0 to 999) Description ---( SC ) (Set Counter Value) executes only if there is a positive edge in RLO.> ---( SZ ) <preset value> <preset value> Parameter English <C no. L.0 C5 SC C#100 The counter C5 is preset with the value of 100 if there is a positive edge at input I0. If there is no positive edge. At that time.

the value of the counter will be unchanged.Counter Instructions 4.> ---( CU ) German <Z no. Status word BR writes: CC 1 CC 0 OV OS OR 0 STA RLO /FC 0 4-10 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . range depends on CPU Description ---( CU ) (Up Counter Coil) increments the value of the specified counter by one if there is a positive edge in the RLO and the value of the counter is less than "999".> ---( ZV ) Parameter English <C no.6 Symbol ---( CU ) Up Counter Coil English <C no.> Parameter German <Z no.> Data Type COUNTER Memory Area Description C Counter identification number. If there is no positive edge in the RLO or the counter already has the value "999".

0 changes from "0" to "1" (positive edge in RLO). If there is no positive edge in RLO. the counter C10 is reset to "0".2 C10 CU C10 R If the signal state of input I0. If the signal state of I0. the value of C10 will be unchanged.2 is "1". Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 4-11 . If the signal state of input I0.Counter Instructions Example Network 1 I 0.0 C10 SC C#100 Network 2 I 0.1 changes from "0" to "1" (positive edge in RLO). counter C10 count value will be incremented by one unless the value of C10 is equal to "999". the preset value of 100 is loaded to counter C10.1 Network 3 I 0.

Counter Instructions 4.7 Symbol ---( CD ) Down Counter Coil English <C no. if there is a positive edge in the RLO state and the value of the counter is more than "0".> ---( CD ) German <Z no. If there is no positive edge in the RLO or the counter has already the value "0".> ---( ZD ) Parameter English <C no.> Data Type COUNTER Memory Area Description C Counter identification number. the value of the counter will be unchanged. Status word BR writes: CC 1 CC 0 OV OS OR 0 STA RLO /FC 0 4-12 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .> Parameter German <Z no. range depends on CPU Description ---( CD ) (Down Counter Coil) decrements the value of the specified counter by one.

1 C10 CU Network 2 Network 3 C10 Q 4.2 C10 R If the signal state of input I0.0 is turned on. If the count value = 0. If there is no positive edge in RLO. counter C10 count value will be decremented by one unless the value of C10 is equal to "0". Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 4-13 . If the signal state of input I0. the value of C10 will be unchanged.0 changes from "0" to "1" (positive edge in RLO).1 changes from "0" to "1" (positive edge in RLO).0 Z10 SC C#100 I 0. the counter C10 is reset to "0". then Q4.Counter Instructions Example Network 1 I 0.2 is "1". If the signal state of input I0. the preset value of 100 is loaded to counter C10.0 "0" count value detector Network 4 I 0.

Counter Instructions 4-14 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

0 Q 4. depending on the register contents.> <DI no. The signal state of this bit is assigned to the output Q4. range depends on CPU Description ---(OPN) (Open a Data Block) opens a shared data block (DB) or an instance data block (DI).> or <DI no. The number of the data block is transferred into the DB or DI register.1 Symbol ---(OPN) Open Data Block: DB or DI <DB no. DI Description Number of DB/DI. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 5-1 .> ---(OPN) Parameter <DB no. The ---(OPN) function is an unconditional call of a data block.0) refers to bit zero of data byte zero of the current data record contained in DB10. The contact address (DBX0.5 Data Block Instructions 5. Status word BR writes: CC 1 CC 0 OV OS OR STA RLO /FC - Example Network 1 DB10 OPN DBX0.0.0 Network 2 Data block 10 (DB10) is opened.> Data Type BLOCK_DB Memory Area DB. The subsequent DB and DI commands access the corresponding blocks.

Data Block Instructions 5-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

Label as Destination The destination label must be at the beginning of a network. There are logic control instructions to perform the following functions: • • • ---( JMP )-----( JMP )-----( JMPN )--Unconditional Jump Conditional Jump Jump-If-Not Label as Address The address of a Jump instruction is a label. you type the name of the label. Network 1 SEG3 JMP Network 2 Q 4. .0 I 0.1 = . the other characters can be letters or numbers (for example. Network X SEG3 Q 4. function blocks (FBs).1 I 0.6 Logic Control Instructions 6. and functions (FCs). The jump label indicates the destination to which you want the program to jump. An empty box appears. In the box. The first character must be a letter of the alphabet. A label consists of a maximum of four characters. You enter the destination label at the beginning of the network by selecting LABEL from the ladder logic browser. SEG3).1 Overview of Logic Control Instructions Description You can use logic control instructions in all logic blocks: organization blocks (OBs).4 R Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 6-1 .

Status word BR writes: CC 1 CC 0 OV OS OR STA RLO /FC - Example Network 1 CAS1 JMP : : Network X CAS1 I 0.Unconditional Jump <label name> ---( JMP ) Description ---( JMP ) (jump within the block when 1) functions as an absolute jump when there is no other Ladder element between the left-hand power rail and the instruction (see example).Logic Control Instructions 6.4 Q 4. All instructions between the jump instruction and the label are not executed. A destination (LABEL) must also exist for every ---( JMP ).2 Symbol ---(JMP)--. 6-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .1 R : : The jump is always executed and the instructions between the jump instruction and the jump label are missed out.

3. the RLO changes to "1" after the jump instruction.Conditional Jump <label name> ---( JMP ) Description ---( JMP ) (jump within the block when 1) functions as a conditional jump when the RLO of the previous logic operation is "1". Because of the jump. If a conditional jump is not executed. the jump to label CAS1 is executed.3 Q 4. the instruction to reset output Q4. All instructions between the jump instruction and the label are not executed.0 CAS1 JMP I 0. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 6-3 .0 = "1".0 R Network 2 Network 3 CAS1 I 0.1 R If I0. Status word BR writes: CC 1 CC 0 OV OS OR 0 STA 1 RLO 1 /FC 0 Example Network 1 I 0.4 Q 4.Logic Control Instructions 6.0 is not executed even if there is a logic "1" at I0.3 Symbol ---(JMP)--. A destination (LABEL) must also exist for every ---( JMP ).

3.3 Q 4. the jump to label CAS1 is executed. If a conditional jump is not executed. Status word BR writes: CC 1 CC 0 OV OS OR 0 STA 1 RLO 1 /FC 0 Example Network 1 I 0.4 Q 4. 6-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .0 R Network 2 Network 3 CAS1 I 0.0 = "0". All instructions between the jump instruction and the label are not executed.0 is not executed even if there is a logic "1" at I0. the RLO changes to "1" after the jump instruction. Because of the jump. the instruction to reset output Q4.0 CAS1 JMP I 0.1 R If I0.4 Symbol ---( JMPN ) Jump-If-Not <label name> ---( JMPN ) Description ---( JMPN ) (Jump-If-not) corresponds to a "goto label" function which is executed if the RLO is "0".Logic Control Instructions 6. A destination (LABEL) must also exist for every ---( JMPN ).

Example Network 1 I 0. A jump label (LABEL) must exist for every ---( JMP ) or ---( JMPN ).0 CAS1 JMP I 0.4 Q 4.1 R If I0. the jump to label CAS1 is executed. The first character must be a letter of the alphabet. the other characters can be letters or numbers (for example. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 6-5 . Because of the jump. the instruction to reset output Q4.3.0 = "1". CAS1).5 Symbol LABEL Label LABEL Description LABEL is the identifier for the destination of a jump instruction.0 R Network 2 Network 3 CAS1 I 0.0 is not executed even if there is a logic "1" at I0.Logic Control Instructions 6.3 Q 4.

Logic Control Instructions 6-6 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

1 Overview of Integer Math Instructions Description Using integer math.7 Integer Math Instructions 7. you can carry out the following operations with two integer numbers (16 and 32 bits): • • • • • • • • • ADD_I SUB_I MUL_I DIV_I Add Integer Subtract Integer Multiply Integer Divide Integer ADD_DI Add Double Integer SUB_DI Subtract Double Integer MUL_DI Multiply Double Integer DIV_DI Divide Double Integer MOD_DI Return Fraction Double Integer Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 7-1 .

Integer Math Instructions 7. 768 (negative number) 32 bits: result < -2 147 483 648 (negative number) Division by 0 A1 0 A0 0 OV 1 OS 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 Operation +D: result = -4 294 967 296 /D or MOD: division by 0 A1 0 1 A0 0 1 OV 1 1 OS 1 1 7-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . Invalid Range for the Result Underflow (addition) 16 bits: result = -65536 32 bits: result = -4 294 967 296 Underflow (multiplication) 16 bits: result < -32 768 (negative number) 32 bits: result < -2 147 483 648 (negative number) Overflow (addition. division) 16 bits: result > 32 767 (positive number) 32 bits: result > 2 147 483 647 (positive number) Underflow (addition. subtraction) 16 bits: result < -32. OV and OS. subtraction) 16 bits: result > 32 767 (positive number) 32 bits: result > 2 147 483 647 (positive number) Overflow (multiplication. The following tables show the signal state of the bits in the status word for the results of instructions with Integers (16 and 32 bits): Valid Range for the Result 0 (zero) 16 bits: -32 768 <= result < 0 (negative number) 32 bits: -2 147 483 648 <=result < 0 (negative number) 16 bits: 32 767 >= result > 0 (positive number) 32 bits: 2 147 483 647 >= result > 0 (positive number) CC 1 0 0 1 CC 0 0 1 0 OV 0 0 0 OS * * * * The OS bit is not affected by the result of the instruction.2 Evaluating the Bits of the Status Word with Integer Math Instructions Description The integer math instructions affect the following bits in the Status word: CC1 and CC0.

so that other functions after this math box which are connected by the ENO (cascade arrangement) are not executed.0 is set. Q. The result of the addition MW0 + MW2 is output to MW10. D Description Enable input Enable output First value for addition Second value for addition Result of addition Description ADD_I (Add Integer) is activated by a logic "1" at the Enable (EN) Input. L. the output Q4. M. the OV bit and OS bit will be "1" and ENO is logic "0". D or constant I. D I. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 7-3 .Integer Math Instructions 7. M. L. IN1 and IN2 are added and the result can be scanned at OUT. L. L. M. If the result was outside the permissible range for an integer.0 = "1".0 S The ADD_I box is activated if I0. See also Evaluating the Bits of the Status Word with Integer Math Instructions. Q. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Example I 0.0 MW0 MW2 ADD_I EN IN1 IN2 ENO OUT NOT MW10 Q 4. L. If the result is outside the permissible range for an integer (16-bit).3 Symbol ADD_I Add Integer ADD_I EN ENO IN1 IN2 OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL INT INT INT Memory Area I. M. D or constant I. Q. D I. Q. M. Q.

Integer Math Instructions

7.4
Symbol

SUB_I Subtract Integer

SUB_I EN ENO IN1 IN2 OUT

Parameter EN ENO IN1 IN2 OUT

Data Type BOOL BOOL INT INT INT

Memory Area I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D or constant I, Q, M, L, D or constant I, Q, M, L, D

Description Enable input Enable output First value for subtraction Value to subtract Result of subtraction

Description
SUB_I (Subtract Integer) is activated by a logic "1" at the Enable (EN) Input. IN2 is subtracted from IN1 and the result can be scanned at OUT. If the result is outside the permissible range for an integer (16-bit), the OV bit and OS bit will be "1" and ENO is logic "0", so that other functions after this math box which are connected by the ENO (cascade arrangement) are not executed. See also Evaluating the Bits of the Status Word with Integer Math Instructions.

Status word
BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1

Example
I 0.0 MW0 MW2
SUB_I

EN IN1 IN2

ENO OUT

NOT MW10

Q 4.0 S

The SUB_I box is activated if I0.0 = "1". The result of the subtraction MW0 - MW2 is output to MW10. If the result was outside the permissible range for an integer or the signal state of I0.0 = 0, the output Q4.0 is set.

7-4

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

Integer Math Instructions

7.5
Symbol

MUL_I Multiply Integer

MUL_I EN ENO IN1 IN2 OUT

Parameter EN ENO IN1 IN2 OUT

Data Type BOOL BOOL INT INT INT

Memory Area I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D or constant I, Q, M, L, D or constant I, Q, M, L, D

Description Enable input Enable output First value for multiplication Second value for multiplication Result of multiplication

Description
MUL_I (Multiply Integer) is activated by a logic "1" at the Enable (EN) Input. IN1 and IN2 are multiplied and the result can be scanned at OUT. If the result is outside the permissible range for an integer (16-bit), the OV bit and OS bit will be "1" and ENO is logic "0", so that other functions after this math box which are connected by the ENO (cascade arrangement) are not executed. See also Evaluating the Bits of the Status Word with Integer Math Instructions.

Status word
BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1

Example
I 0.0 MW0 MW2
MUL_I

EN IN1 IN2

ENO OUT

NOT MW10

Q 4.0 S

The MUL_I box is activated if I0.0 = "1". The result of the multiplication MW0 x MW2 is output to MD10. If the result was outside the permissible range for an integer, the output Q4.0 is set.

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

7-5

Integer Math Instructions

7.6
Symbol

DIV_I Divide Integer

DIV_I EN ENO IN1 IN2 OUT

Parameter EN ENO IN1 IN2 OUT

Data Type BOOL BOOL INT INT INT

Memory Area I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D or constant I, Q, M, L, D or constant I, Q, M, L, D

Description Enable input Enable output Dividend Divisor Result of division

Description
DIV_I (Divide Integer) is activated by a logic "1" at the Enable (EN) Input. IN1 is divided by IN2 and the result can be scanned at OUT. If the result is outside the permissible range for an integer (16-bit), the OV bit and OS bit is "1" and ENO is logic "0", so that other functions after this math box which are connected by ENO (cascade arrangement) are not executed. See also Evaluating the Bits of the Status Word with Integer Math Instructions.

Status word
BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1

Example
I 0.0 MW0 MW2
DIV_I

EN IN1 IN2

ENO OUT

NOT MW10

Q 4.0 S

The DIV_I box is activated if I0.0 = "1". The result of the division MW0 by MW2 is output to MW10. If the result was outside the permissible range for an integer, the output Q4.0 is set.

7-6

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

Integer Math Instructions

7.7
Symbol

ADD_DI Add Double Integer

ADD_DI EN ENO IN1 IN2 OUT

Parameter EN ENO IN1 IN2 OUT

Data Type BOOL BOOL DINT DINT DINT

Memory Area I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D or constant I, Q, M, L, D or constant I, Q, M, L, D

Description Enable input Enable output First value for addition Second value for addition Result of addition

Description
ADD_DI (Add Double Integer) is activated by a logic "1" at the Enable (EN) Input. IN1 and IN2 are added and the result can be scanned at OUT. If the result is outside the permissible range for a double integer (32-bit), the OV bit and OS bit will be "1" and ENO is logic "0", so that other functions after this math box which are connected by the ENO (cascade arrangement) are not executed. See also Evaluating the Bits of the Status Word with Integer Math Instructions.

Status word
BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1

Example
I 0.0 MD0 MD4
ADD_DI

EN IN1 IN2

ENO OUT

NOT MD10

Q 4.0 S

The ADD_DI box is activated if I0.0 = "1". The result of the addition MD0 + MD4 is output to MD10. If the result was outside the permissible range for a double integer, the output Q4.0 is set.

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

7-7

M. M. L.0 is set. Q. the output Q4. D I. L. M. If the result is outside the permissible range for a double integer (32-bit). L. L. D I. See also Evaluating the Bits of the Status Word with Integer Math Instructions.0 S The SUB_DI box is activated if I0. Q. the OV bit and OS bit will be "1" and ENO is logic "0". D Description Enable input Enable output First value for subtraction Value to subtract Result of subtraction Description SUB_DI (Subtract Double Integer) is activated by a logic "1" at the Enable (EN) Input. IN2 is subtracted from IN1 and the result can be scanned at OUT.8 Symbol SUB_DI Subtract Double Integer SUB_DI EN ENO IN1 IN2 OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL DINT DINT DINT Memory Area I. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. D or constant I. M.MD4 is output to MD10. Q. 7-8 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . L.Integer Math Instructions 7.0 = "1". If the result was outside the permissible range for a double integer. so that other functions after this math box which are connected by the ENO (cascade arrangement) are not executed.0 MD0 MD4 SUB_DI EN IN1 IN2 ENO OUT NOT MD10 Q 4. D or constant I. M. The result of the subtraction MD0 . Q. Q.

L. the OV bit and OS bit will be "1" and ENO is logic "0".Integer Math Instructions 7. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. M. M. Q. D or constant I. IN1 and IN2 are multiplied and the result can be scanned at OUT. M. so that other functions after this math box which are connected by the ENO (cascade arrangement) are not executed.0 is set. M.0 MD0 MD4 MUL_DI EN IN1 IN2 ENO OUT NOT MD10 Q 4. L. D Description Enable input Enable output First value for multiplication Second value for multiplication Result of multiplication Description MUL_DI (Multiply Double Integer) is activated by a logic "1" at the Enable (EN) Input. D or constant I. the output Q4.0 = "1". Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 7-9 . L. D I. If the result is outside the permissible range for a double integer (32-bit). M. L. See also Evaluating the Bits of the Status Word with Integer Math Instructions. D I. Q. Q. Q. L.0 S The MUL_DI box is activated if I0. The result of the multiplication MD0 x MD4 is output to MD10. Q. If the result was outside the permissible range for a double integer.9 Symbol MUL_DI Multiply Double Integer MUL_DI EN ENO IN1 IN2 OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL DINT DINT DINT Memory Area I.

Q. the output Q4. the OV bit and OS bit is "1" and ENO is logic "0". Q.0 S The DIV_DI box is activated if I0. See also Evaluating the Bits of the Status Word with Integer Math Instructions. L. M. Q. The result of the division MD0 : MD4 is output to MD10. L.0 = "1". IN1 is divided by IN2 and the result can be scanned at OUT. M. D I. L.0 MD0 MD4 DIV_DI EN IN1 IN2 ENO OUT NOT MD10 Q 4. so that other functions after this math box which are connected by the ENO (cascade arrangement) are not executed. M. Q. L. D or constant I. If the result is outside the permissible range for a double integer (32-bit). Q. D I. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. 7-10 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .Integer Math Instructions 7. If the result was outside the permissible range for a double integer. D Description Enable input Enable output Dividend Divisor Whole-number result of division Description DIV_DI (Divide Double Integer) is activated by a logic "1" at the Enable (EN) Input. The Divide Double Integer element does not produce a remainder. D or constant I.0 is set.10 Symbol DIV_DI Divide Double Integer DIV_DI EN ENO IN1 IN2 OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL DINT DINT DINT Memory Area I. M. M. L.

0 S The DIV_DI box is activated if I0. L. M.11 Symbol MOD_DI Return Fraction Double Integer MOD_DI EN ENO IN1 IN2 OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL DINT DINT DINT Memory Area I. D or constant I. D or constant I. IN1 is divided by IN2 and the fraction can be scanned at OUT. The remainder of the division MD0:MD4 is output to MD10. L. so that other functions after this math box which are connected by the ENO (cascade arrangement) are not executed. Q. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Example I 0.Integer Math Instructions 7. Q. Q. M. L.0 MD0 MD4 MOD_DI EN IN1 IN2 ENO OUT NOT MD10 Q 4.0 = "1". L. See also Evaluating the Bits of the Status Word with Integer Math Instructions. M. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 7-11 . D I. If the remainder was outside the permissible range for a double integer. the OV bit and OS bit is "1" and ENO is logic "0". If the result is outside the permissible range for a double integer (32-bit). D I. M. M. D Description Enable input Enable output Dividend Divisor Remainder of division Description MOD_DI (Return Fraction Double Integer) is activated by a logic "1" at the Enable (EN) Input.0 is set. Q. L. Q. the output Q4.

Integer Math Instructions 7-12 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

you can carry out the following operations with one 32-bit IEEE floating-point number: • • • • • Establish the Absolute Value (ABS) Establish the Square (SQR) and the Square Root (SQRT) Establish the Natural Logarithm (LN) Establish the Exponential Value (EXP) to base e (= 2.71828) Establish the following trigonometrical functions of an angle represented as a 32-bit IEEE floating-point number - Sine (SIN) and Arc Sine (ASIN) Cosine (COS) and Arc Cosine (ACOS) Tangent (TAN) and Arc Tangent (ATAN) See also Evaluating the Bits of the Status Word.8 Floating Point Math Instructions 8.1 Overview of Floating-Point Math Instruction Description The IEEE 32-bit floating-point numbers belong to the data type called REAL. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 8-1 . You can use the floating-point math instructions to perform the following math instructions using two 32-bit IEEE floating-point numbers: • • • • ADD_R SUB_R MUL_R DIV_R Add Real Subtract Real Multiply Real Divide Real Using floating-point math.

175494E-38 < result < .401298E-45 (negative number) Underflow +1. Invalid Area for a Result Underflow -1. -0 (zero) -3.402823E+38 (positive number) Not a valid floating-point number or illegal instruction (input value outside the valid range) CC 1 CC 0 OV 0 0 0 1 1 0 0 1 0 1 1 1 1 1 1 OS 1 1 1 1 1 8-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .175494E-38 (positive number) Overflow Result < -3.Floating Point Math Instructions 8.2 Evaluating the Bits of the Status Word with FloatingPoint Math Instructions Description Floating-point instructions affect the following bits in the status word: CC 1 and CC 0.402824E+38 (positive number) CC 1 CC 0 OV 0 0 1 0 1 0 0 0 0 OS * * * * The OS bit is not affected by the result of the instruction. The following tables show the signal state of the bits in the status word for the results of instructions with floating-point numbers (32 bits): Valid Area for a Result +0.1. OV and OS.402823E+38 < result < -1.175494E-38 (negative number) +1.402823E+38 (negative number) Overflow Result > 3.401298E-45 < result < +1.175494E-38 < result < 3.

0 NOT MD10 S The ADD_R box is activated by logic "1" at I0. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. The result of the addition MD0 + MD4 is output to MD10.1 Symbol Basic Instructions ADD_R Add Real ADD_R EN ENO IN1 IN2 OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL REAL REAL REAL Memory Area I. L. Q. L. D or constant I. If the result was outside the permissible range for a floating-point number or if the program statement was not processed (I0. the OV bit and OS bit will be "1" and ENO is "0". L. D or constant I. so that other functions after this math box which are connected by the ENO (cascade arrangement) are not executed.3 8.0 = 0). D Description Enable input Enable output First value for addition Second value for addition Result of addition Description ADD_R (Add Real) is activated by a logic "1" at the Enable (EN) Input. M. L. D I. M. Q. the output Q4.0. IN1 and IN2 are added and the result can be scanned at OUT. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 8-3 . D I.0 MD0 MD4 ADD_R ENO EN IN1 OUT IN2 Q 4.Floating Point Math Instructions 8. M. Q. M. Q. M.3. Q. L. See also Evaluating the Bits of the Status Word.0 is set. If the result is outside the permissible range for a floating-point number (overflow or underflow).

If the result was outside the permissible range for a floating-point number or if the program statement was not processed. Q.2 SUB_R Subtract Real Symbol SUB_R EN ENO IN1 IN2 OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL REAL REAL REAL Memory Area I. M. L. M.0 MD0 MD4 SUB_R ENO EN IN1 OUT IN2 Q 4. M.MD4 is output to MD10. D or constant I. L. D I. L. IN2 is subtracted from IN1 and the result can be scanned at OUT. D I. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. D Description Enable input Enable output First value for subtraction Value to subtract Result of subtraction Description SUB_R (Subtract Real) is activated by a logic "1" at the Enable (EN) Input. See also Evaluating the Bits of the Status Word. so that other functions after this math box which are connected by the ENO (cascade arrangement) are not executed. Q.0 is set. L. If the result is outside the permissible range for a floating-point number (overflow or underflow).Floating Point Math Instructions 8. L. 8-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .0. the OV bit and OS bit will be "1" and ENO is logic "0". M. Q. D or constant I. the output Q4. The result of the subtraction MD0 .3.0 NOT MD10 S The SUB_R box is activated by logic "1" at I0. M. Q. Q.

L. M.3 MUL_R Multiply Real Symbol MUL_R EN ENO IN1 IN2 OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL REAL REAL REAL Memory Area I. D Description Enable input Enable output First value for multiplication Second value for multiplication Result of multiplication Description MUL_R (Multiply Real) is activated by a logic "1" at the Enable (EN) Input.0 is set. L. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. the OV bit and OS bit will be "1" and ENO is logic "0".0. the output Q4. D or constant I. D or constant I.0 MD0 MD4 MUL_R ENO EN IN1 OUT IN2 Q 4. If the result was outside the permissible range for a floating-point number or if the program statement was not processed. so that other functions after this math box which are connected by the ENO (cascade arrangement) are not executed. Q. Q. D I.0 NOT MD10 S The MUL_R box is activated by logic "1" at I0. L. Q. L. The result of the multiplication MD0 x MD4 is output to MD0. Q. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 8-5 .Floating Point Math Instructions 8. M. If the result is outside the permissible range for a floating-point number (overflow or underflow).3. IN1 and IN2 are multiplied and the result can be scanned at OUT. M. M. M. Q. L. See also Evaluating the Bits of the Status Word. D I.

Q. 8-6 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . L.0 NOT MD10 S The DIV_R box is activated by logic "1" at I0. M.0 is set.Floating Point Math Instructions 8. the OV bit and OS bit is "1" and ENO is logic "0". D or constant I. See also Evaluating the Bits of the Status Word. If the result is outside the permissible range for a floating-point number (overflow or underflow). Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Example I 0. IN1 is divided by IN2 and the result can be scanned at OUT. the output Q4. M. L.0 MD0 MD4 DIV_R ENO EN IN1 OUT IN2 Q 4. so that other functions after this math box which are connected by the ENO (cascade arrangement) are not executed.4 DIV_R Divide Real Symbol DIV_R EN ENO IN1 IN2 OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL REAL REAL REAL Memory Area I. M. The result of the division MD0 by MD4 is output to MD10. D or constant I. Q. L. D I. M.3. Q. Q. L. L. Q. D I.0. If the result was outside the permissible range for a floating-point number or if the program statement was not processed. M. D Description Enable input Enable output Dividend Divisor Result of division Description DIV_R (Divide Real) is activated by a logic "1" at the Enable (EN) Input.

D or constant I.234 gives MD12 = 6.5 ABS Establish the Absolute Value of a Floating-Point Number Symbol ABS EN ENO IN OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL REAL Memory Area I. M. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 8-7 . Q.0 is "1" when the conversion is not executed (ENO = EN = 0). Q.Floating Point Math Instructions 8. Output Q4. M. L. Q.0 ABS EN ENO IN OUT Q 4. Q.0 NOT MD12 MD8 If I0. D I.234.3. MD8 = + 6. L. M. Status word BR writes: 1 CC 1 CC 0 OV OS OR 0 STA 1 RLO 1 /FC 1 Example I 0. M. the absolute value of MD8 is output at MD12. L. L. D Description Enable input Enable output Input value: floating-point Output value: absolute value of the floating-point number Description ABS establishes the absolute value of a floating-point number.0 = "1". D I.

Q. Q. D I. M. M. D Description Enable input Enable output Input value: floating-point Output value: square of floatingpoint number Description SQR establishes the square of a floating-point number. See also Evaluating the Bits of the Status Word. D I.4 8.Floating Point Math Instructions 8. D or constant I. L. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 8-8 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . Q. L. M. L. L. M.4.1 Extended Instructions SQR Establish the Square Symbol SQR EN ENO IN OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL REAL Memory Area I. Q.

D or constant I. D I. Q. D Description Enable input Enable output Input value: floating-point Output value: square root of floating-point number Description SQRT establishes the square root of a floating-point number. M. L. Q. M. L.Floating Point Math Instructions 8. Sole exception: the square root of -0 is -0.2 SQRT Establish the Square Root Symbol SQRT EN ENO IN OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL REAL Memory Area I. D I. M. Q. Q. L.4. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 8-9 . See also Evaluating the Bits of the Status Word. L. M. This instruction issues a positive result when the address is greater than "0".

4. See also Evaluating the Bits of the Status Word. L. L. Q.. M. D I. L. M. M.. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 8-10 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . M. D or constant I. Q.). Q. D Description Enable input Enable output Input value: floating-point Output value: exponential value of the floating-point number Description EXP establishes the exponential value of a floating-point number on the basis e (=2.Floating Point Math Instructions 8. Q. L.3 EXP Establish the Exponential Value Symbol EXP EN ENO IN OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL REAL Memory Area I.71828. D I.

Q. L.4. Q. M. M. Q. L. M. Q. M. L. D Description Enable input Enable output Input value: floating-point Output value: natural logarithm of the floating-point number Description LN establishes the natural logarithm of a floating-point number.Floating Point Math Instructions 8. D or constant I. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 8-11 .4 LN Establish the Natural Logarithm Symbol LN EN ENO IN OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL REAL Memory Area I. See also Evaluating the Bits of the Status Word. L. D I. D I.

M. D I. L. D or constant I. L.5 SIN Establish the Sine Value Symbol SIN EN ENO IN OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL REAL Memory Area I. D I. M. L. The floating-point number represents an angle in a radian measure here. M. Q. M. L. See also Evaluating the Bits of the Status Word. D Description Enable input Enable output Input value: floating-point Output value: sine of the floatingpoint number Description SIN establishes the sine value of a floating-point number. Q.Floating Point Math Instructions 8. Q.4. Q. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 8-12 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

M. L. L. Q. M. D or constant I. M.Floating Point Math Instructions 8. L.6 COS Establish the Cosine Value Symbol COS EN ENO IN OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL REAL Memory Area I. See also Evaluating the Bits of the Status Word. M. Q. D Description Enable input Enable output Input value: floating-point Output value: cosine of the floating-point number Description COS establishes the cosine value of a floating-point number. Q. The floating-point number represents an angle in a radian measure here.4. Q. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 8-13 . L. D I. D I.

7 TAN Establish the Tangent Value Symbol TAN EN ENO IN OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL REAL Memory Area I. M.4. L. D I. D Description Enable input Enable output Input value: floating-point Output value: tangent of the floating-point number Description TAN establishes the tangent value of a floating-point number. Q. See also Evaluating the Bits of the Status Word. Q. M. D I. L. L. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 8-14 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . The floating-point number represents an angle in a radian measure here. M. Q. M.Floating Point Math Instructions 8. L. D or constant I. Q.

L. M.1415.. D Description Enable input Enable output Input value: floating-point Output value: arc sine of the floating-point number Description ASIN establishes the arc sine value of a floating-point number with a definition range -1 <= input value <= 1. Q.Floating Point Math Instructions 8. Q. M. The result represents an angle in a radian measure within the range -π/2 ≤ output value ≤ +π/2 where π = 3. M.. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 8-15 . Q.. Q.4. L. D I. D I. See also Evaluating the Bits of the Status Word. D or constant I. L.8 ASIN Establish the Arc Sine Value Symbol ASIN EN ENO IN OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL REAL Memory Area I. L. M.

M.4. Status word BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1 8-16 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . D I. Q. M. D I.9 ACOS Establish the Arc Cosine Value Symbol ACOS EN ENO IN OUT Parameter EN ENO IN OUT Data Type BOOL BOOL REAL REAL Memory Area I. The result represents an angle in a radian measure within the range 0 ≤ output value ≤ +π where π = 3. Q. See also Evaluating the Bits of the Status Word. M. L. D or constant I.Floating Point Math Instructions 8... M. Q.1415. D Description Enable input Enable output Input value: floating-point Output value: arc cosine of the floating-point number Description ACOS establishes the arc cosine value of a floating-point number with a definition range -1 <= input value <= 1. L. L. Q. L..

Floating Point Math Instructions

8.4.10

ATAN Establish the Arc Tangent Value

Symbol
ATAN EN ENO IN OUT

Parameter EN ENO IN OUT

Data Type BOOL BOOL REAL REAL

Memory Area I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D or constant I, Q, M, L, D

Description Enable input Enable output Input value: floating-point Output value: arc tangent of the floating-point number

Description
ATAN establishes the arc tangent value of a floating-point number. The result represents an angle in a radian measure within the range

-π/2 ≤ output value ≤ +π/2 where π = 3.1415....
See also Evaluating the Bits of the Status Word.

Status word
BR writes: x CC 1 x CC 0 x OV x OS x OR 0 STA x RLO x /FC 1

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

8-17

Floating Point Math Instructions

8-18

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

9

Move Instructions

9.1
Symbol

MOVE Assign a Value

MOVE
EN IN ENO OUT

Parameter EN ENO IN

Data Type BOOL BOOL

Memory Area I, Q, M, L, D I, Q, M, L, D

Description Enable input Enable output Source value

All elementary data I, Q, M, L, D or types with a length of constant 8, 16, or 32 bits All elementary data I, Q, M, L, D types with a length of 8, 16, or 32 bits

OUT

Destination address

Description
MOVE (Assign a Value) is activated by the Enable EN Input. The value specified at the IN input is copied to the address specified at the OUT output. ENO has the same logic state as EN. MOVE can copy only BYTE, WORD, or DWORD data objects. User-defined data types like arrays or structures have to be copied with the system function "BLKMOVE" (SFC 20).

Status word
BR writes: 1 CC 1 CC 0 OV OS OR 0 STA 1 RLO 1 /FC 1

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

9-1

Move Instructions

MCR (Master Control Relay) dependency
MCR dependency is activated only if a Move box is placed inside an active MCR zone. Within an activated MCR zone, if the MCR is on and there is power flow to the enable input; the addressed data is copied as described above. If the MCR is off, and a MOVE is executed, a logic "0" is written to the specified OUT address regardless of current IN states.

Note
When moving a value to a data type of a different length, higher-value bytes are truncated as necessary or filled up with zeros:
Example: Double Word Move to a double word: to a byte: to a word: Example: Byte Move to a byte: to a word: to a double word: 0000 0000 0000 0000 0000 0000 0000 0000 Result 1111 0000 1111 0000 1111 0000 1111 0000 1111 1111 Result 1111 1111 0000 1111 1111 0000 0101 0101 0101 0101 0101 0101 1111 0000 0000 1111 1111 0000 0101 0101

Example
I 0.0

MOVE
EN ENO OUT

Q 4.0

MW10

IN

DBW12

The instruction is executed if I0.0 is "1". The content of MW10 is copied to data word 12 of the currently open DB. Q4.0 is "1" if the instruction is executed.

If the example rungs are within an activated MCR zone: • • When MCR is on, MW10 data is copied to DBW12 as described above. When MCR is off, "0" is written to DBW12.

9-2

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

10 Program Control Instructions 10.1 Overview of Program Control Instructions Description The following program control instructions are available: • • • • • • • • • • • • • ---(CALL) CALL_FB CALL_FC CALL_SFB Call FC SFC from Coil (without Parameters) Call FB from Box Call FC from Box Call System FB from Box CALL_SFC Call System FC from Box Call Multiple Instance Call Block from a Library Important Notes on Using MCR Functions ---(MCR<) ---(MCR>) ---(MCRA) ---(MCRD) RET Master Control Relay On Master Control Relay Off Master Control Relay Activate Master Control Relay Deactivate Return Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 10-1 .

Program Control Instructions

10.2
Symbol

---(Call) Call FC SFC from Coil (without Parameters)

<FC/SFC no.> ---( CALL )
Parameter <FC/SFC no.> Data Type BLOCK_FC BLOCK_SFC Memory Area Description Number of FC/SFC; range depends on CPU

Description
---(Call) (Call FC or SFC without Parameters) is used to call a function (FC) or system function (SFC) that has no passed parameters. A call is only executed if RLO is "1" at the CALL coil. If ---(Call) is executed, • • • • The return address of the calling block is stored, The previous local data area is replaced by the current local data area, The MA bit (active MCR bit) is shifted to the B stack, A new local data area for the called function is created.

After this, program processing continues in the called FC or SFC.

Status word
BR Unconditional: writes: Conditional: writes: CC 1 CC 0 OV OS 0 0 OR 0 0 STA 1 1 RLO 1 /FC 0 0

10-2

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

Program Control Instructions

Example
. . . . . . . . .

DB10 OPN

MCRA FC10 CALL I 0.0 Q 4.0

. . . . . . MCRD I 0.1 FC11 CALL

The Ladder rungs shown above are program sections from a function block written by a user. In this FB, DB10 is opened and MCR functionality is activated. If the unconditional call of FC10 is executed, the following occurs: The return address of the calling FB plus selection data for DB10 and for the instance data block for the calling FB are saved. The MA bit, set to "1" in the MCRA instruction, is pushed to the B stack and then set to "0" for the called block (FC10). Program processing continues in FC10. If MCR functionality is required by FC10, it must be re-activated within FC10. When FC10 is finished, program processing returns to the calling FB. The MA bit is restored, DB10 and the instance data block for the user-written FB become the current DBs again, regardless of which DBs FC10 has used. The program continues with the next rung by assigning the logic state of I0.0 to output Q4.0. The call of FC11 is a conditional call. It is only executed if I0.1 is "1". If it is executed, the process of passing program control to and returning from FC11 is the same as was described for FC10.

Note
After returning to the calling block, the previously open DB is not always open again. Please make sure you read the note in the README file.

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

10-3

Program Control Instructions

10.3
Symbol

CALL_FB Call FB from Box

<DB no.> FB no. EN ENO

The symbol depends on the FB (whether it has parameters and how many of them). It must have the EN, ENO, and the name or number of the FB.
Parameter EN ENO FB no. DB no. Data Type BOOL BOOL BLOCK_FB BLOCK_DB Memory Area I, Q, M, L, D I, Q, M, L, D Description Enable input Enable output Number of FB/DB; range depends on CPU

Description
CALL_FB (Call a Function Block from a Box) executed if EN is "1". If CALL_FB is executed, • • • • • The return address of the calling block is stored, The selection data for the two current data blocks (DB and instance DB) are stored, The previous local data area is replaced by the current local data area, The MA bit (active MCR bit) is shifted to the B stack, A new local data area for the called function block is created.

After this, program processing continues within the called function block. The BR bit is scanned in order to find out the ENO. The user has to assign the required state (error evaluation) to the BR bit in the called block using ---(SAVE).

Status word
BR Unconditional: writes: Conditional: writes: x CC 1 CC 0 OV OS 0 0 OR 0 0 STA x x RLO x x /FC x x

10-4

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

Program Control Instructions

Example
. . . . . . . . . . . . DB11 FB11 EN ENO DB10 OPN

DB10 OPN

MCRA Q 4.0

The Ladder rungs shown above are program sections from a function block written by a user. In this FB, DB10 is opened and MCR functionality is activated. If the unconditional call of FB11 is executed, the following occurs: The return address of the calling FB plus selection data for DB10 and for the instance data block for the calling FB are saved. The MA bit, set to "1" in the MCRA instruction, is pushed to the B stack and then set to "0" for the called block (FB11). Program processing continues in FB11. If MCR functionality is required by FB11, it must be re-activated within FB11. The state of the RLO must be saved in the BR bit by the instruction ---(SAVE) in order to be able to evaluate errors in the calling FB. When FB11 is finished, program processing returns to the calling FB. The MA bit is restored and the instance data block of the user-written FB is opened again. If the FB11 is processed correctly, ENO = "1" and therefore Q4.0 = "1".

Note
When opening an FB or SFB, the number of the previously opened DB is lost. The required DB has to be reopened.

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

10-5

M. program processing continues in the called function. and IN_OUT declarations. The BR bit is scanned in order to find out the ENO. If you call a function and the variable declaration table of the called block has IN. If CALL_FC is executed. L.4 Symbol CALL_FC Call FC from Box FC no. It must have EN. L. D I. Parameter EN ENO FC no. D Description Enable input Enable output Number of FC. When calling the function. The user has to assign the required state (error evaluation) to the BR bit in the called block using ---(SAVE). you must assign actual parameters to the formal parameters at the call location. Q. Q. The previous local data area is replaced by the current local data area. OUT. M. Data Type BOOL BOOL BLOCK_FC Memory Area I.Program Control Instructions 10. • • • • The return address of the calling block is stored. Any initial values in the function declaration have no significance. range depends on CPU Description CALL_FC (Call a Function from a Box) is used to call a function (FC). these variables are added in the program for the calling block as a list of formal parameters. A new local data area for the called function is created. After this. ENO. Status word BR Unconditional: writes: Conditional: writes: x CC 1 CC 0 OV OS 0 0 OR 0 0 STA x x RLO x x /FC x x 10-6 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . The call is executed if EN is "1". The MA bit (active MCR bit) is shifted to the B stack. and the name or number of the FC. EN ENO The symbol depends on the FC (whether it has parameters and how many of them). no.

the following occurs: The return address of the calling FB plus selection data for DB10 and for the instance data block for the calling FB are saved. After execution of FC10. . program processing returns to the calling FB.Program Control Instructions Example .0 = "1". If the unconditional call of FC10 is executed. . set to "1" in the MCRA instruction. The MA bit. When FC10 is finished. If MCR functionality is required by FC10. In this FB. Please make sure you read the note in the README file. the previously open DB is not always open again. . DB10 is opened and MCR functionality is activated. it must be re-activated within FC10. The state of the RLO must be saved in the BR bit by the instruction ---(SAVE) in order to be able to evaluate errors in the calling FB. program processing is continued in the calling FB depending on the ENO: ENO = "1" FC11 is processed ENO = "0" processing starts in the next network If FC11 is also processed correctly. The MA bit is restored. . Note After returning to the calling block. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 10-7 . ENO = "1" and therefore Q4. .0 EN ENO EN ENO The Ladder rungs shown above are program sections from a function block written by a user. . . . . is pushed to the B stack and then set to "0" for the called block (FC10). DB10 OPN MCRA FC10 FC11 Q 4. . Program processing continues in FC10. .

ENO.> SFB no. and the name or number of the SFB. range depends on CPU Description CALL_SFB (Call a System Function Block from a Box) is executed if EN is "1". Data Type BOOL BOOL BLOCK_SFB BLOCK_DB Memory Area I. If CALL_SFB is executed. M. EN ENO The symbol depends on the SFB (whether it has parameters and how many of them). It must have the EN. Q. • • • • • The return address of the calling block is stored. The MA bit (active MCR bit) is shifted to the B stack.5 Symbol CALL_SFB Call System FB from Box <DB no. ENO is "1" if the SFB was called (EN = "1") and no error occurs. A new local data area for the called system function block is created. Parameter EN ENO SFB no. D I. DB no. L. Program processing then continues in the called SFB. M.Program Control Instructions 10. Status word BR Unconditional: writes: Conditional: writes: x CC 1 CC 0 OV OS 0 0 OR 0 0 STA x x RLO x x /FC x x 10-8 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . The previous local data area is replaced by the current local data area. D Description Enable input Enable output Number of SFB. The selection data for the two current data blocks (DB and instance DB) are stored. Q. L.

program processing returns to the calling FB. is pushed to the B stack and then set to "0" for the called block (SFB8). the following occurs: The return address of the calling FB plus selection data for DB10 and for the instance data block for the calling FB are saved. In this FB. If the unconditional call of SFB8 is executed. ENO = "1" and therefore Q4. . . The required DB has to be reopened. Program processing continues in SFB8. . .0 = "1". .0 CODE DB10 OPN MCRA Q 4. The MA bit. Note When opening an FB or SFB. When SFB8 is finished. If the SFB8 is processed correctly.Program Control Instructions Example . DB10 is opened and MCR functionality is activated. EN M11. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 10-9 . the number of the previously opened DB is lost. set to "1" in the MCRA instruction. . . .0 The Ladder rungs shown above are program sections from a function block written by a user.0 REQ ID R_ID DW12 DW14 DW16 SD_1 SD_2 SD_3 SD_4 DB10 OPN DB 8 SFB 8 ENO DONE ERROR STATUS READY M10. The MA bit is restored and the instance data block of the user-written FB becomes the current instance DB.

After this. • • • • The return address of the calling block is stored. Status word BR Unconditional: writes: Conditional: writes: x CC 1 CC 0 OV OS 0 0 OR 0 0 STA x x RLO x x /FC x x 10-10 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . The previous local data area is replaced by the current local data area. The call is executed if EN is "1".Program Control Instructions 10. Parameter EN ENO SFC no. If CALL_SFC is executed. It must have EN. and the name or number of the SFC. ENO. range depends on CPU Description CALL_SFC (Call a System Function from a Box) is used to call an SFC. The MA bit (active MCR bit) is shifted to the B stack. program processing continues in the called SFC.6 CALL_SFC Call System FC from Box Symbol SFC no. ENO is "1" if the SFC was called (EN = "1") and no error occurs. no. A new local data area for the called system function is created. Data Type BOOL BOOL BLOCK_SFC Memory Area Description Enable input Enable output Number of SFC. EN ENO The symbol depends on the SFC (whether it has parameters and how many of them).

SRCBLK RET_VAL DSTBLK The Ladder rungs shown above are program sections from a function block written by a user. is pushed to the B stack and then set to "0" for the called block (SFC20). . Please make sure you read the note in the README file. . . In this FB. set to "1" in the MCRA instruction. DB10 is opened and MCR functionality is activated. program processing returns to the calling FB. When SFC20 is finished. . Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 10-11 . . the following occurs: The return address of the calling FB plus selection data for DB10 and for the instance data block for the calling FB are saved.0 = "0" Note After returning to the calling block. EN DB10 OPN MCRA SFC20 ENO Q 4. . the previously open DB is not always open again.0 = "1" ENO = "0" Q4. . The MA bit is restored. If the unconditional call of SFC20 is executed. . . Program processing continues in SFC20. After processing the SFC20. The MA bit.0 MW10 MOTOR. .Program Control Instructions Example . the program is continued in the calling FB depending on the ENO: ENO = "1" Q4.SPEED DBDW12 .

M. EN. Status word BR writes: CC 1 CC 0 OV OS 0 OR 0 STA x RLO x /FC x 10.8 Call Block from a Library The libraries available in the SIMATIC Manager can be used here to select a block that • Is integrated in your CPU operating system ("Standard Library" library for STEP 7 projects in version 3 and "stdlibs (V2)" for STEP 7 projects in version 2) You saved yourself in a library because you wanted to use it a number of times. Q. SFB Memory Area I. L. M.7 Symbol Call Multiple Instance #Variable name EN ENO Parameter EN ENO #Variable name Data Type BOOL BOOL FB. The symbol for a multiple instance varies depending on whether and how many parameters are present.Program Control Instructions 10. ENO and the variable name are always present. L. D - Description Enable input Enable output Name of multiple instance Description A multiple instance is created by declaring a static variable with the data type of a function block. D I. • 10-12 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . Q. Only multiple instances that have already been declared are included in the program element catalog.

including the parameter transfer to blocks. T 0. UDT. This means the following command sequences will set the PLC to STOP or lead to undefined runtime characteristics: Formal parameter access • • • • Access to components of complex FC parameters of the type STRUCT. T branches and midline outputs in Ladder or FBD starting with RLO = 0. BLOCK_FC. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 10-13 . the value 0 is written by all assignments in program segments between ---(MCR<) and ---(MCR>). Calls in which parameters are transferred. STRING from the IN_OUT area in a version 2 block.Program Control Instructions 10.0. or FB0 are also always used for TIMER. Parameter passing • • LAD/FBD Remedy Free the above commands from their dependence on the MCR: 1. This is valid for all boxes which contain an assignment. COUNTER. Activate the Master Control Relay again using the Master Control Relay Activate instruction after the statement or network in question. ARRAY. Any subsequent data access sets the CPU to STOP. ARRAY.9 Important Notes on Using MCR Functions Take care with blocks in which the Master Control Relay was activated with MCRA: • If the MCR is deactivated. Deactivate the Master Control Relay using the Master Control Relay Deactivate instruction before the statement or network in question. STRING Access to components of complex FB parameters of the type STRUCT. ! • ! Danger: PLC in STOP or undefined runtime characteristics! The compiler also uses write access to local data behind the temporary variables defined in VAR_TEMP for calculating addresses. UDT. The MCR is deactivated if the RLO was = 0 before an MCR< instruction. 2. Access in a version 2 function block to a parameter of the type BLOCK_DB opens DB0. FC0. C 0. Access to parameters of a version 2 function block if its address is greater than 8180. and BLOCK_FB.

The following elements are MCR-dependent and influenced by the RLO state that is saved to the MCR stack while opening an MCR zone: • • • • • • • --( # ) --( ) --( S ) --( R ) RS SR MOVE Midline Output Output Set Output Reset Output Reset Flip Flop Set Flip Flop Assign a Value Status word BR writes: CC 1 CC 0 OV OS OR 0 STA 1 RLO /FC 0 10-14 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .Program Control Instructions 10.10 ---(MCR<) Master Control Relay On Important Notes on Using MCR Functions Symbol ---(MCR<) Description ---(MCR<) (Open a Master Control Relay zone) saves the RLO in the MCR stack. first out) and only 8 stack entries (nesting levels) are possible. If the stack is already full. the ---(MCR<) function produces an MCR stack fault (MCRF). The MCR nesting stack is a LIFO stack (last in.

3 Q 4. In the example there are two MCR zones.4 Q 4.1 = "1" (MCR is ON for zone 2): Q4.0 = "0" (MCR is OFF for zone 1): Q4.3 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 10-15 .1 is "0" regardless of the logic state of I0.0 = "1" (MCR is ON for zone 1): the logic state of I0.0 S MCR zone 2 MCR zone 1 MCR functionality is activated by the MCRA rung. It is then possible to create up to eight nested MCR zones.4 is assigned to Q4.4 I0.1 I0.0 is set to "1" if I0.1 I 0.0 MCR< I 0. The functions are executed as follows: I0.Program Control Instructions Example Network 1 MCRA Network 2 Network 3 Network 4 Network 5 MCR> Network 6 Network 7 MCR> Network 8 MCRD I 0.0 remains unchanged regardless the logic state of I0.1 = "0" (MCR is OFF for zone 2): Q4.3 is "1" I0.1 MCR< I 0.

The following elements are MCR-dependent and influenced by the RLO state that is saved to the MCR stack while opening the MCR zone: • • • • • • • --( # ) --( ) --( S ) --( R ) RS SR MOVE Midline Output Output Set Output Reset Output Reset Flip Flop Set Flip Flop Assign a Value Status word BR writes: CC 1 CC 0 OV OS OR 0 STA 1 RLO /FC 0 10-16 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .Program Control Instructions 10. If the stack is already empty. first out) and only 8 stack entries (nesting levels) are possible. ---(MCR>) produces an MCR stack fault (MCRF).11 ---(MCR>) Master Control Relay Off Important Notes on Using MCR Functions Symbol ---(MCR>) Description ---(MCR>) (close the last opened MCR zone) removes an RLO entry from the MCR stack. The MCR nesting stack is a LIFO stack (last in.

1 = "1": Q4.3 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 10-17 .1 I 0.4 is assigned to Q4.0 remains unchanged regardless of the logic state of I0.1 I0.Program Control Instructions Example Network 1 MCRA Network 2 Network 3 Network 4 Network 5 MCR> Network 6 Network 7 MCR> Network 8 MCRD I 0. The first ---(MCR>) (MCR OFF) rung belongs to the second ---(MCR<) (MCR ON) rung.1 = "0": Q4.0 = "0": Q4.0 = "1": the logic state of I0.1 MCR< I 0. All rungs between belong to the MCR zone 2.4 I0.4 Q 4.0 is set to "1" if I0.3 is "1" I0.0 S MCR zone 2 MCR zone 1 MCR functionality is activated by the ---(MCRA) rung. It is then possible to create up to eight nested MCR zones. The functions are executed as follows: I0.1 is "0" regardless of the logic state of I0.0 MCR< I 0.3 Q 4. In the example there are two MCR zones.

After this command. the instruction ---(MCRD) deactivates the MCR.12 ---(MCRA) Master Control Relay Activate Important Notes on Using MCR Functions Symbol ---(MCRA) Description ---(MCRA) (Activate Master Control Relay) activates master control relay function.4 is assigned to Q4.1 10-18 . . Network n MCR> Network n + 1 MCRD MCR functionality is activated by the MCRA rung.3 Q 4.3 and Q4. .0 = "0" ( MCR is OFF): Q4.4 In the next rung. This means that you cannot program any more MCR zones using the instruction pair ---(MCR<) and ---(MCR>).0 is set to "1" if I0. The rungs between the MCR< and the MCR> (outputs Q4.3 is "0" and the logic state of I0. it is possible to program MCR zones with the commands: • • ---(MCR<) ---(MCR>) Status word BR writes: CC 1 CC 0 OV OS OR STA RLO /FC - Example Network 1 MCRA Network 2 Network 3 .1 is "0" regardless of the logic state of I0.1 I0.1) are executed as follows: I0. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 I 0.3 is logic "1".Program Control Instructions 10.0 S I 0. or will remain unchanged if I0. .0 remains unchanged regardless of the logic state of I0.4 Q 4.0 = "1" ( MCR is ON ): Q4.0. Q4.0 MCR< I 0.

.0 = "0" (MCR is OFF): Q4.13 ---(MCRD) Master Control Relay Deactivate Important Notes on Using MCR Functions Symbol ---(MCRD) Description ---(MCRD) (Deactivate Master Control Relay) deactivates MCR functionality.1 MCR functionality is activated by the MCRA rung. the instruction ---(MCRD) deactivates the MCR. I0.3 and Q4. This means that you cannot program any more MCR zones using the instruction pair ---(MCR<) and ---(MCR>).1. Q4. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 10-19 . .4 is assigned to Q4.4 Q 4.0 MCR< I 0. After this command.3 Q 4.0 is set to "1" if I0.0 S I 0. Status word BR writes: CC 1 CC 0 OV OS OR STA RLO /FC - Example Network 1 MCRA Network 2 Network 3 .0.Program Control Instructions 10.4. .0 remains unchanged regardless of the logic state of I0.1 is "0" regardless of the logic state of I0.3 is logic "1" and the logic state of I0. The rungs between the MCR< and the MCR> (outputs Q4. Network n MCR> Network n + 1 MCRD I 0. you cannot program MCR zones. In the next rung.1) are executed as follows: I0.0 = "1" (MCR is ON): Q4.

a preceding logic operation is required. . For this output. . .14 ---(RET) Return Symbol ---( RET ) Description RET (Return) is used to conditionally exit blocks. . BEC. . Status word Conditional Return (Return if RLO = "1"): BR writes: * CC 1 CC 0 OV OS 0 OR 0 STA 1 RLO 1 /FC 0 * The operation RET is shown internally in the sequence "SAVE. ". 10-20 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . This also affects the BR bit.0 RET The block is exited if I0. I 0. Example .0 is "1".Program Control Instructions 10.

you obtain the binary equivalent of the decimal value 24 in the accumulator.1 11. you obtain the binary equivalent of the decimal value 4 in the accumulator. The signal state of the bit that is shifted last is loaded into the CC 1 bit of the status word.1. Shifting to the left multiplies the contents of input IN by 2 to the power n (2 n ).1 Shift Instructions Overview of Shift Instructions Description You can use the Shift instructions to move the contents of input IN bit by bit to the left or the right (see also CPU Registers). The following shift instructions are available: • • • • • • SHR_I Shift Right Integer SHR_DI Shift Right Double Integer SHL_W SHR_W Shift Left Word Shift Right Word SHL_DW Shift Left Double Word SHR_DW Shift Right Double Word Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 11-1 .11 Shift and Rotate Instructions 11. The bit places that are vacated by the Shift instruction are either filled with zeros or with the signal state of the sign bit (a 0 stands for positive and a 1 stands for negative). You can use jump instructions to evaluate the CC 1 bit. if you shift the binary equivalent of the decimal value 3 to the left by 3 bits. shifting to the right divides the contents of input IN by 2 to the power n (2 n ). The CC 0 and OV bits of the status word are reset to 0. For example. If you shift the binary equivalent of the decimal value 16 to the right by 2 bits. The number that you supply for input parameter N indicates the number of bits by which to shift.

If N is larger than 16.8 7. ENO has the same signal state as EN. L. Q. D Description Enable input Enable output Value to shift Number of bit positions to shift Result of shift instruction Description SHR_I (Shift Right Integer) is activated by a logic "1" at the Enable (EN) Input. M. The result of the shift instruction can be scanned at output OUT. D I... The input N specifies the number of bits by which to shift. Bits 16 to 31 are not affected. L. L. M. 15.. L. The vacated places are filled with the signal state of the sign bit. L... 11-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .. The bit positions shifted in from the left to fill vacated bit positions are assigned the logic state of bit 15 (sign bit for the integer).0 1 0 1 0 IN N OUT 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 1 0 1 0 These four bits are lost. D I. Q.1. 1 0 1 0 Sign bit . D I.Shift and Rotate Instructions 11..2 SHR_I Shift Right Integer Symbol SHR_I EN ENO IN OUT N Parameter EN ENO IN N OUT Data Type BOOL BOOL INT WORD INT Memory Area I. Q. M. D I. Q.. the command acts as if N were equal to 16. Q. This means these bit positions are assigned "0" if the integer is positive and "1" if the integer is negative. M. The SHR_I instruction is used to shift bits 0 to 15 of input IN bit by bit to the right. The CC 0 bit and the OV bit are set to "0" by SHR_I if N is not equal to 0. 1 1 1 1 0 0 0 0 4 places . M.

D I. Q. M.3 SHR_DI Shift Right Double Integer Symbol SHR_DI EN ENO IN OUT N Parameter EN ENO IN N OUT Data Type BOOL BOOL DINT WORD DINT Memory Area I. L. D I. MW0 is loaded and shifted right by the number of bits specified with MW2.0.0 MW0 MW2 SHR_I EN IN N ENO OUT Q 4. M. D I. L. M. L. Q. Q4.0 S MW4 The SHR_I box is activated by logic "1" at I0. M. L. D I. The result is written to MW4. Q. 11. Q. L.0 is set. D Description Enable input Enable output Value to shift Number of bit positions to shift Result of shift instruction Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 11-3 . M.Shift and Rotate Instructions Status word BR writes: x CC 1 x CC 0 x OV x OS OR x STA x RLO x /FC 1 Example I 0.1. Q.

0 S MD10 The SHR_DI box is activated by logic "1" at I0. 11-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .Shift and Rotate Instructions Description SHR_DI (Shift Right Double Integer) is activated by a logic "1" at the Enable (EN) Input. MD0 is loaded and shifted right by the number of bits specified with MW4. The result of the shift instruction can be scanned at output OUT.0 is set. The input N specifies the number of bits by which to shift. The bit positions shifted in from the left to fill vacated bit positions are assigned the logic state of bit 31 (sign bit for the double integer).0. ENO has the same signal state as EN. Status word BR writes: x CC 1 x CC 0 x OV x OS OR x STA x RLO x /FC 1 Example I 0. This means these bit positions are assigned "0" if the integer is positive and "1" if the integer is negative. If N is larger than 32.0 MD0 MW4 SHR_DI EN IN N ENO OUT Q 4. The SHR_DI instruction is used to shift bits 0 to 31 of input IN bit by bit to the right. the command acts as if N were equal to 32. The CC 0 bit and the OV bit are set to "0" by SHR_DI if N is not equal to 0. Q4. The result is written to MD10.

the command writes a "0" at output OUT and sets the bits CC 0 and OV in the status word to "0". If N is larger than 16. L. Q. The CC 0 bit and the OV bit are set to "0" by SHL_W if N is not equal to 0. D I. L. D Description Enable input Enable output Value to shift Number of bit positions to shift Result of shift instruction Description SHL_W (Shift Left Word) is activated by a logic "1" at the Enable (EN) Input.. D I. L. The SHL_W instruction is used to shift bits 0 to 15 of input IN bit by bit to the left. 0 0 0 0 . Q. The input N specifies the number of bits by which to shift. Bits 16 to 31 are not affected. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 11-5 .. M.. L. Q. M. ENO has the same signal state as EN..4 SHL_W Shift Left Word Symbol SHL_W EN ENO IN OUT N Parameter EN ENO IN N OUT Data Type BOOL BOOL WORD WORD WORD Memory Area I.. D I.Shift and Rotate Instructions 11. 0 1 0 1 0 1 0 0 0 0 0 0 The vacated places are filled with zeros... Q. The result of the shift instruction can be scanned at output OUT.1.8 7. Q. 1 1 1 1 0 1 0 1 6 places . M. M. M.. L. 15. N zeros are also shifted in from the right to fill vacated bit positions. D I.0 0 1 0 1 IN N OUT 0 0 0 0 1 1 1 1 0 1 These six bits are lost.

D I. L. 11.0 MW0 MW2 SHL_W EN IN N ENO OUT Q 4. Q.0 is set. L. L.0. L. The result is written to MW4. D I. Q. Q.Shift and Rotate Instructions Status word BR writes: x CC 1 x CC 0 x OV x OS OR x STA x RLO x /FC 1 Example I 0. D I.0 S MW4 The SHL_W box is activated by logic "1" at I0. D Description Enable input Enable output Value to shift Number of bit positions to shift Result word of shift instruction 11-6 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . M. M. M. Q4. Q. D I. M.1. M. MW0 is loaded and shifted left by the number of bits specified with MW2. L.5 SHR_W Shift Right Word Symbol SHR_W EN ENO IN OUT N Parameter EN ENO IN N OUT Data Type BOOL BOOL WORD WORD WORD Memory Area I. Q.

D Description Enable input Enable output Value to shift Number of bit positions to shift Result double word of shift instruction Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 11-7 . The result is written to MW4. L. The SHR_W instruction is used to shift bits 0 to 15 of input IN bit by bit to the right. If N is larger than 16. the command writes a "0" at output OUT and sets the bits CC 0 and OV in the status word to "0". Q. M. L.Shift and Rotate Instructions Description SHR_W (Shift Right Word) is activated by a logic "1" at the Enable (EN) Input. MW0 is loaded and shifted right by the number of bits specified with MW2. Bits 16 to 31 are not affected.1. Q. The result of the shift instruction can be scanned at output OUT.6 SHL_DW Shift Left Double Word Symbol SHL_DW EN ENO OUT IN N Parameter EN ENO IN N OUT Data Type BOOL BOOL DWORD WORD DWORD Memory Area I. M. M. N zeros are also shifted in from the left to fill vacated bit positions.0 S MW4 The SHR_W box is activated by logic "1" at I0. D I. The CC 0 bit and the OV bit are set to "0" by SHR_W if N is not equal to 0. Q. The input N specifies the number of bits by which to shift. Status word BR writes: x CC 1 x CC 0 x OV x OS OR x STA x RLO x /FC 1 Example I 0. D I. Q4. Q. L.0 is set. D I. Q. L. D I. L. M.0 MW0 MW2 SHR_W EN IN N ENO OUT Q 4.0. M. ENO has the same signal state as EN. 11.

The input N specifies the number of bits by which to shift. the command writes a "0" at output OUT and sets the bits CC 0 and OV in the status word to "0". 11-8 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . N zeros are also shifted in from the right to fill vacated bit positions. The result is written to MD10. If N is larger than 32.0. Status word BR writes: x CC 1 x CC 0 x OV x OS OR x STA x RLO x /FC 1 Example I 0. ENO has the same signal state as EN.Shift and Rotate Instructions Description SHL_DW (Shift Left Double Word) is activated by a logic "1" at the Enable (EN) Input.0 S MD10 The SHL_DW box is activated by logic "1" at I0. The SHL_DW instruction is used to shift bits 0 to 31 of input IN bit by bit to the left. Q4. The CC 0 bit and the OV bit are set to "0" by SHL_DW if N is not equal to 0.0 MD0 MW4 SHL_DW EN IN N ENO OUT Q 4. MD0 is loaded and shifted left by the number of bits specified with MW4.0 is set. The result double word of the shift instruction can be scanned at output OUT.

The SHR_DW instruction is used to shift bits 0 to 31 of input IN bit by bit to the right.7 SHR_DW Shift Right Double Word Symbol SHR_DW EN ENO IN OUT N Parameter EN ENO IN N OUT Data Type BOOL BOOL DWORD WORD DWORD Memory Area I.0 1111 1111 0101 0101 1010 1010 1111 1111 3 places IN N OUT 0001 1111 1110 1010 1011 0101 0101 1111 The vacated places are filled with zeros.. ENO has the same signal state as EN... M. M. The result double word of the shift instruction can be scanned at output OUT. D I.. D I... The input N specifies the number of bits by which to shift. Q. L. Q. M. Q. L. the command writes a "0" at output OUT and sets the bits CC 0 and OV in the status word to "0". D I.Shift and Rotate Instructions 11. . D Description Enable input Enable output Value to shift Number of bit positions to shift Result double word of shift instruction Description SHR_DW (Shift Right Double Word) is activated by a logic "1" at the Enable (EN) Input. . L. Q. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 11-9 . L. 111 These three bits are lost. If N is larger than 32. D I. N zeros are also shifted in from the left to fill vacated bit positions. L.. Q. 31. M.1.. The CC 0 bit and the OV bit are set to "0" by SHR_DW if N is not equal to 0. M.16 15.

0. 11-10 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .0 is set. Q4.Shift and Rotate Instructions Status word BR writes: x CC 1 x CC 0 x OV x OS OR x STA x RLO x /FC 1 Example I 0. The result is written to MD10. MD0 is loaded and shifted right by the number of bits specified with MW4.0 S MD10 The SHR_DW box is activated by logic "1" at I0.0 MD0 MW4 SHR_DW EN IN N ENO OUT Q 4.

Q.2. M. Q. L. D I.Shift and Rotate Instructions 11. M.2 11. D Description Enable input Enable output Value to rotate Number of bit positions to rotate Result double word of rotate instruction Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 11-11 . Depending on the instruction. Q. L. M. D I.2 ROL_DW Rotate Left Double Word Symbol ROL_DW EN ENO IN OUT N Parameter EN ENO IN N OUT Data Type BOOL BOOL DWORD WORD DWORD Memory Area I. M. L. Q. The vacated bit places are filled with the signal states of the bits that are shifted out of input IN. The number that you supply for input parameter N specifies the number of bits by which to rotate. L. D I. L.1 Rotate Instructions Overview of Rotate Instructions Description You can use the Rotate instructions to rotate the entire contents of input IN bit by bit to the left or to the right.2. rotation takes place via the CC 1 bit of the status word. The CC 0 bit of the status word is reset to 0. D I. M. Q. The following rotate instructions are available: • • ROL_DW ROR_DW Rotate Left Double Word Rotate Right Double Word 11.

. MD0 is loaded and rotated to the left by the number of bits specified with MW4.Shift and Rotate Instructions Description ROL_DW (Rotate Left Double Word) is activated by a logic "1" at the Enable (EN) Input.16 15. the double word IN is rotated by ((N-1) modulo 32)+1 positions.. Q4.. .. The result is written to MD10. If N is larger than 32.. 11-12 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .0 1111 0000 1010 1010 0000 1111 0000 1111 3 places IN N OUT 111 1000 0101 0101 0000 0111 1000 0111 1111 These three bits are lost. The input N specifies the number of bits by which to rotate.. 31.0 MD0 MW4 ROL_DW EN IN N ENO OUT Q 4. The bit positions shifted in from the right are assigned the logic states of the bits which were rotated out to the left. The result double word of the rotate instruction can be scanned at output OUT.0. The ROL_DW instruction is used to rotate the entire contents of input IN bit by bit to the left. ENO has the same signal state as EN. Status word BR writes: x CC 1 x CC 0 x OV x OS OR x STA x RLO x /FC 1 Example I 0.0 S MD10 The ROL_DW box is activated by logic "1" at I0. The signal states of the three bits that are shifted out are inserted in the vacated places....0 is set. The CC 0 bit and the OV bit are set to "0" by ROL_DW if N is not equal to 0.

M. L.. the double word IN is rotated by ((N-1) modulo 32)+1 positions.. The result double word of the rotate instruction can be scanned at output OUT. Q.. . 31. The CC 0 bit and the OV bit are set to "0" by ROR_DW if N is not equal to 0. M. If N is larger than 32.. . D I.0 1010 1010 0000 1111 0000 1111 0101 0101 3 places IN N OUT 1011 0101 0100 0001 1110 0001 1110 1010 The signal states of the three bits that are shifted out are inserted in the vacated places. 101 Status word BR writes: x CC 1 x CC 0 x OV x OS OR x STA x RLO x /FC 1 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 11-13 . L. Q.3 ROR_DW Rotate Right Double Word Symbol ROR_DW EN ENO IN OUT N Parameter EN ENO IN N OUT Data Type BOOL BOOL DWORD WORD DWORD Memory Area I. L. D I. M.Shift and Rotate Instructions 11. Q. Q. M. D I.. The bit positions shifted in from the left are assigned the logic states of the bits which were rotated out to the right. L. D Description Enable input Enable output Value to rotate Number of bit positions to rotate Result double word of rotate instruction Description ROR_DW (Rotate Right Double Word) is activated by a logic "1" at the Enable (EN) Input. The ROR_DW instruction is used to rotate the entire contents of input IN bit by bit to the right.2.. Q.16 15. The input N specifies the number of bits by which to rotate. ENO has the same signal state as EN. D I. L... M.

MD0 is loaded and rotated to the right by the number of bits specified with MW4. The result is written to MD10.0.0 is set.Shift and Rotate Instructions Example I 0. Q4.0 S MD10 The ROR_DW box is activated by logic "1" at I0.0 MD0 MW4 ROR_DW EN IN N ENO OUT Q 4. 11-14 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

. by Floating-point Functions. Structure of the status word: 2 . 15 . Status word The status word is a register in the memory of your CPU that contains bits that you can reference in the address of bit and word logic instructions.1 Overview of Statusbit Instructions Description The status bit instructions are bit logic instructions that work with the bits of the status word. The result of a math function is unordered (UO ---I I---). > 0. Each of these instructions reacts to one of the following conditions that is indicated by one or more bits of the status word: • • • • The Binary Result bit (BR ---I I---) is set (that is.2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 BR CC1 CC0 OV OS OR STA RLO /FC You can evaluate the bits in the status word • • by Integer Math Functions.. >= 0. The result of a math function is related to 0 in one of the following ways: == 0. < 0. it combines the result of its signal state check with the previous result of logic operation according to the And truth table... Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 12-1 . has a signal state of 1). When a status bit instruction is connected in series. <> 0. A math function had an Overflow (OV ---I I---) or a Stored Overflow (OS ---I I---). <= 0. When a status bit instruction is connected in parallel. it combines its result with the previous RLO according to the Or truth table.12 Status Bit Instructions 12.

the OV bit is set. the result of the scan is linked to the RLO by AND.0 IW0 IW2 Network 2 OV SUB_I EN ENO IN1 IN2 OUT MW10 I 0.2 I 0. Otherwise it is possible to take the ENO output of the math function that is "0" if the result is outside the permissible range. Used in series.IW2" is outside the permissible range for an integer. Note The scan with OV is only necessary because of the two separate networks. used in parallel. 12-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .Status Bit Instructions 12.0 is set if the scan of OV is signal state "1" and the RLO of network 2 is "1".Exception Bit Overflow OV or negation OV / Description OV ---| |--.0. This means that after the function executes. The signal state scan at OV is "1".(Exception Bit Overflow) or OV ---| / |--.2 Symbol OV ---| |--.2 Q 4. If the result of the math function "IW0 . the result of the instruction is outside the permissible negative or positive range. Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Example Network 1 I 0.0 S The box is activated by signal state "1" at I0. it is linked to the RLO by OR.( Negated Exception Bit Overflow) contact symbols are used to recognize an overflow in the last math function executed. Q4.1 I 0.

Status Bit Instructions

12.3
Symbol

OS ---| |--- Exception Bit Overflow Stored

OS or negation

OS

/

Description
OS ---| |--- (Exception Bit Overflow Stored) or OS ---| / |--- (Negated Exception Bit Overflow Stored) contact symbols are used to recognize and store a latching overflow in a math function. If the result of the instruction lies outside the permissible negative or positive range, the OS bit in the status word is set. Unlike the OV bit, which is rewritten for subsequent math functions, the OS bit stores an overflow when it occurs. The OS bit remains set until the block is left. Used in series, the result of the scan is linked to the RLO by AND, used in parallel, it is linked to the RLO by OR.

Status word
BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

12-3

Status Bit Instructions

Example
Network 1 I 0.0 IW0 IW2 Network 2 I 0.01 IW0 IW2 Network 3 OS ADD_I ENO EN IN1 IN2 OUT MW12 MUL_I EN ENO IN1 IN2 OUT MW10

Q 4.0 S

The MUL_I box is activated by signal state "1" at I0.0. The ADD_I box is activated by logic "1" at I0.1. If the result of one of the math functions was outside the permissible range for an integer, the OS bit in the status word is set to "1". Q4.0 is set if the scan of OS is logic "1".

Note
The scan with OS is only necessary because of the two separate networks. Otherwise it is possible to take the ENO output of the first math function and connect it with the EN input of the second (cascade arrangement).

12-4

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

Status Bit Instructions

12.4
Symbol

UO ---| |--- Exception Bit Unordered

UO or negation

UO

/

Description
UO ---| |--- (Exception Bit Unordered) or UO ---| / |--- (Negated Exception Bit Unordered) contact symbols are used to recognize if the math function with floating-point numbers is unordered (meaning, whether one of the values in the math function is an invalid floating-point number). If the result of a math function with floating-point numbers (UO) is invalid, the signal state scan is "1". If the logic operation in CC 1 and CC 0 shows "not invalid", the result of the signal state scan is "0". Used in series, the result of the scan is linked to the RLO by AND, used in parallel it is linked to the RLO by OR.

Status word
BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1

Example
I 0.0 ID0 ID4 DIV_R EN ENO IN1 IN2 OUT Q 4.0 S MD10

UO

Q 4.1 S

The box is activated by signal state "1" at I0.0. If the value of ID0 or ID4 is an invalid floating-point number, the math function is invalid. If the signal state of EN = 1 (activated) and if an error occurs during the processing of the function DIV_R, the signal state of ENO = 0. Output Q4.1 is set when the function DIV_R is executed but one of the values is not a valid floating-point number.

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

12-5

Status Bit Instructions

12.5
Symbol

BR ---| |--- Exception Bit Binary Result

BR or negation

BR

/

Description
BR ---| |--- (Exception Bit BR Memory) or BR ---| / |--- (Negated Exception Bit BR Memory) contact symbols are used to test the logic state of the BR bit in the status word. Used in series, the result of the scan is linked to the RLO by AND, used in parallel, it is linked to the RLO by OR. The BR bit is used in the transition from word to bit processing.

Status word
BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1

Example
I 0.0 I 0.2 BR Q 4.0 S

Q4.0 is set if I0.0 is "1" or I0.2 is "0" and in addition to this RLO the logic state of the BR bit is "1".

12-6

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01

Used in series.6 Symbol ==0 ---| |--. If the value of IW0 is equal to the value of IW2.0 IW0 IW2 SUB_I ENO EN IN1 OUT IN2 ==0 Q 4. it is linked to the RLO by OR.0 is set if the function is properly executed and the result is not equal to "0". The instructions scan the condition code bits CC 1 and CC 0 in the status word in order to determine the relation of the result to "0".0 S MW10 Q4. the result of the math function "IW0 .(Negated Result Bit Equal 0) contact symbols are used to recognize if the result of a math function is equal to "0".Status Bit Instructions 12. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 12-7 .0 S MW10 The box is activated by signal state "1" at I0. Q4.0 is set if the function is properly executed and the result is equal to "0".Result Bit Equal 0 ==0 or negation ==0 / Description ==0 ---| |--.0.(Result Bit Equal 0) or ==0 ---| / |--.IW2" is "0".0 IW0 IW2 SUB_I ENO EN IN1 OUT IN2 ==0 Q 4. I 0. the result of the scan is linked to the RLO by AND. Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Examples I 0. used in parallel.

The instructions scan the condition code bits CC 1 and CC 0 in the status word in order to determine the relation of the result to "0".7 Symbol <>0 ---| |--. the result of the math function "IW0 . I 0. Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Examples I 0.(Result Bit Not Equal 0) or <>0 ---| / |--.0 IW0 IW2 SUB_I ENO EN IN1 OUT IN2 <>0 Q 4.(Negated Result Bit Not Equal 0) contact symbols are used to recognize if the result of a math function is not equal to "0".0 S MW10 Q4.0 is set if the function is properly executed and the result is equal to "0".0 IW0 IW2 SUB_I ENO EN IN1 OUT IN2 <>0 Q 4.Status Bit Instructions 12. it is linked to the RLO by OR.0. the result of the scan is linked to the RLO by AND. used in parallel. If the value of IW0 is different to the value of IW2. 12-8 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . Q4.IW2" is not equal to "0".Result Bit Not Equal 0 <>0 or negation <>0 / Description <>0 ---| |--. Used in series.0 S MW10 The box is activated by signal state "1" at I0.0 is set if the function is properly executed and the result is not equal to "0".

the result of the scan is linked to the RLO by AND.0 IW0 IW2 SUB_I ENO EN IN1 OUT IN2 >0 Q 4.(Result Bit Greater Than 0) or >0 ---| / |--. If the value of IW0 is higher than the value of IW2.0 S MW10 Q4.IW2" is greater than "0".0.0 is set if the function is properly executed and the result is greater than "0".0 S MW10 The box is activated by signal state "1" at I0.Status Bit Instructions 12. used in parallel.Result Bit Greater Than 0 >0 or negation >0 / Description >0 ---| |--. it is linked to the RLO by OR. Q4.0 IW0 IW2 SUB_I ENO EN IN1 OUT IN2 >0 Q 4. Used in series.(Negated Result Bit Greater Than Zero) contact symbols are used to recognize if the result of a math function is greater than "0".8 Symbol >0 ---| |--. The instructions scan the condition code bits CC 1 and CC 0 in the status word in order to determine the relation to "0". Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 12-9 .0 is set if the function is properly executed and the result is not greater than "0". I 0. Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Example I 0. the result of the math function "IW0 .

Result Bit Less Than 0 <0 or negation <0 / Description <0 ---| |--.9 Symbol <0 ---| |--.IW2" is less than "0". I 0.0 IW0 IW2 SUB_I ENO EN IN1 OUT IN2 <0 Q 4. it is linked to the RLO by OR.0 is set if the function is properly executed and the result is not less than "0". The instructions scan the condition code bits CC 1 and CC 0 in the status word in order to determine the relation of the result to "0". the result of the scan is linked to the RLO by AND.0 S MW10 Q4. the result of the math function "IW0 . Used in series.(Negated Result Bit Less Than 0) contact symbols are used to recognize if the result of a math function is less than "0".Status Bit Instructions 12. If the value of IW0 is lower than the value of IW2.0 S MW10 The box is activated by signal state "1" at I0. used in parallel. Q4.0 is set if the function is properly executed and the result is less than "0".(Result Bit Less Than 0) or <0 ---| / |--. 12-10 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .0. Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Example I 0.0 IW0 IW2 SUB_I ENO EN IN1 OUT IN2 <0 Q 4.

the result of the math function "IW0 .10 >=0 ---| |--.Result Bit Greater Equal 0 Symbol >=0 or negation >=0 / Description >=0 ---| |--. Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Example I 0.0 is set if the function is properly executed and the result is not greater than or equal to "0".0 IW0 IW2 SUB_I ENO EN IN1 OUT IN2 >=0 Q 4.0.Status Bit Instructions 12. If the value of IW0 is higher or equal to the value of IW2.0 is set if the function is properly executed and the result is greater than or equal to "0".(Result Bit Greater Equal 0) or >=0 ---| / |--. the result of the scan is linked to the RLO by AND.IW2" is greater than or equal to "0". Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 12-11 . The instructions scan the condition code bits CC 1 and CC 0 in the status word in order to determine the relation to "0".0 IW0 IW2 SUB_I ENO EN IN1 OUT IN2 >=0 Q 4. Q4. Used in series. used in parallel. I 0.(Negated Result Bit Greater Equal 0) contact symbols are used to recognize if the result of a math function is greater than or equal to "0".0 S MW10 The box is activated by signal state "1" at I0. it is linked to the RLO by OR.0 S MW10 Q4.

0 IW0 IW2 SUB_I ENO EN IN1 OUT IN2 <=0 Q 4. it is linked to the RLO by OR. the result of the scan is linked to the RLO by AND.0 S MW10 Q4. The instructions scan the condition code bits CC 1 and CC 0 in the status word in order to determine the relation of the result to "0". used in parallel.0 IW0 IW2 SUB_I ENO EN IN1 OUT IN2 <=0 Q 4.Result Bit Less Equal 0 Symbol <=0 or negation <=0 / Description <=0 ---| |--. If the value of IW0 is less than or equal to the value of IW2 the result of the math function "IW0 .IW2" is less than or equal to "0".0 is set if the function is properly executed and the result is not less than or equal to "0". 12-12 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .(Result Bit Less Equal 0) or <=0 ---| / |--.11 <=0 ---| |--.0 is set if the function is well properly executed and the result is less than or equal to "0". Q4. I 0.0.(Negated Result Bit Less Equal 0) contact symbols are used to recognize if the result of a math function is less than or equal to "0". Used in series. Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Examples I 0.Status Bit Instructions 12.0 S MW10 The box is activated by signal state "1" at I0.

The following timer instructions are available: • • • • • • • • • • S_PULSE Pulse S5 Timer S_PEXT S_ODT S_ODTS Extended Pulse S5 Timer On-Delay S5 Timer Retentive On-Delay S5 Timer S_OFFDT Off-Delay S5 Timer ---( SP ) ---( SE ) ---( SD ) ---( SS ) ---( SA ) Pulse Timer Coil Extended Pulse Timer Coil On-Delay Timer Coil Retentive On-Delay Timer Coil Off-Delay Timer Coil Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 13-1 .13 Timer Instructions 13.1 Overview of Timer Instructions Description You can find information for setting and selecting the correct time under "Location of a Timer in Memory and Components of a Timer".

2 Location of a Timer in Memory and Components of a Timer Area in Memory Timers have an area reserved for them in the memory of your CPU. and 18 seconds Time Base Bits 12 and 13 of the timer word contain the time base in binary code. - The maximum time value that you can enter is 9. This memory area reserves one 16-bit word for each timer address. The time value specifies a number of units. M = minutes. Decrementing continues until the time value is equal to zero. and the value is rounded to the next lower number with that time base. The time base is selected automatically. This function of your CPU in the RUN mode decrements a given time value by one unit at the interval designated by the time base until the time value is equal to zero. The smallest time base is 10 ms. Please refer to your CPU’s technical information to establish the number of timer words available. You can pre-load a time value using either of the following formats: • W#16#wxyz - Where w = the time base (that is. S = seconds. The ladderlogic instruction set supports 256 timers. You can load a time value into the low word of accumulator 1 in binary. Time updating decrements the time value by one unit at an interval designated by the time base. 13-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . or 2H_46M_30S. The following functions have access to the timer memory area: • • Timer instructions Updating of timer words by means of clock timing.990 seconds. the time interval or resolution) Where xyz = the time value in binary coded decimal format • S5T#aH_bM_cS_dMS - Where H = hours. b.Timer Instructions 13. hexadecimal. The time base defines the interval at which the time value is decremented by one unit. the largest is 10 s. and MS = milliseconds. S5TIME#4S = 4 seconds s5t#2h_15m = 2 hours and 15 minutes S5T#1H_12M_18S = 1 hour. Time Value Bits 0 through 9 of the timer word contain the time value in binary code. d are defined by the user. or binary coded decimal (BCD) format. c. a. 12 minutes.

for which you can indicate a word location. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 13-3 .Timer Instructions Time Base 10 ms 100 ms 1s 10 s Binary Code for the Time Base 00 01 10 11 Values that exceed 2h46m30s are not accepted.... The BCD output provides the time base and the time value in binary coded decimal (BCD) format.. BI and BCD.. the contents of the timer cell are used as the time value. Reading the Time and the Time Base Each timer box provides two outputs. x x 1 0 0 0 1 0 . Bits 12 and 13 hold the time base in binary code..1 second 1 second 10 seconds Range 10MS to 9S_990MS 100MS to 1M_39S_900MS 1S to 16M_39S 10S to 2H_46M_30S Bit Configuration in the Time Cell When a timer is started. A value whose resolution is too high for the range limits (for example.8 7. The general format for S5TIME has limits to range and resolution as shown below: Resolution 0. The following figure shows the contents of the timer cell loaded with timer value 127 and a time base of 1 second: 15. Bits 0 through 11 of the timer cell hold the time value in binary coded decimal format (BCD format: each set of four bits contains the binary code for one decimal value). The BI output provides the time value in binary format.0 1 Time base 1 second Time value in BCD (0 to 999) Irrelevant: These bits are ignored when the timer is started. 1 0 0 2 1 0 0 1 7 1 ...01 second 0. 2h10ms) is truncated down to a valid resolution.

0 S_ODT t Q 4.0 S_ODTS t Q 4.Timer Instructions Choosing the right Timer This overview is intended to help you choose the right timer for your timing job. The output signal stays at 1 for a shorter period if the input signal changes to 0.0 S_PEXT t Q 4. The output signal changes to 1 only when the programmed time has elapsed and the input signal is still 1.0 S_OFFDT t Timer S_PULSE Pulse timer S_PEXT Extended pulse timer S_ODT On-delay timer S_ODTS Retentive on-delay timer S_OFFDT Off-delay timer Description The maximum time that the output signal remains at 1 is the same as the programmed time value t. regardless of how long the input signal stays at 1. I 0. 13-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . The output signal remains at 1 for the programmed length of time. The output signal changes to 1 when the input signal changes to 1 or while the timer is running. The time is started when the input signal changes from 1 to 0.0 S_PULSE t Q 4. regardless of how long the input signal stays at 1. The output signal changes from 0 to 1 only when the programmed time has elapsed.0 Q 4.

M. Q. Q. The timer runs as long as the signal state at input S is "1". L. BCD format Status of the timer Description S_PULSE (Pulse S5 Timer) starts the specified timer if there is a positive edge at the start (S) input. If there is a change from "1" to "0" at the S input before the time interval has elapsed the timer will be stopped. L. S TW R DUAL DEZ Q Data Type TIMER BOOL S5TIME BOOL WORD WORD BOOL Memory Area Description T I. A signal change is always necessary in order to enable a timer. D Timer identification number. The current time value is the initial TV value minus the time elapsed since the timer was started. M. The time value at BI is binary coded. Q. S_IMPULS S TW R Q DUAL DEZ Parameter English T no. Q. M. M. D I. The current time and the time base are also set to zero. range depends on CPU Start input Preset time value Reset input Remaining time value. Q. D I. Logic "1" at the timer’s R input has no effect if the timer is not running. S_PULSE S TV R Q BI BCD German T-Nr. is the time value specified by input TV. L. D I. The current time value can be scanned at the outputs BI and BCD. The timer is reset when the timer reset (R) input changes from "0" to "1" while the timer is running.Timer Instructions 13. The signal state at output Q is "1" as long as the timer is running. M. M. L. In this case the signal state at output Q is "0". however. S TV R BI BCD Q Parameter German T-Nr. D I. D I. integer format Remaining time value. L. Q. the longest period. at BCD it is BCD coded.3 Symbol S_PULSE Pulse S5 Timer English T no. L. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 13-5 .

The timer will continue to run for the specified time of two seconds (2 s) as long as I0.1 If the signal state of input I0. the time is reset.0 changes from "1" to "0" before the timer has expired the timer will be stopped. If the signal state of input I0.0 is "1".0 I 0. If the signal state of I0.1 changes from "0" to "1" while the timer is running. 13-6 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . The output Q4.0 Q 4.0 changes from "0" to "1" (positive edge in RLO).Timer Instructions Timing Diagram Pulse timer characteristics: t RLO at S input t t RLO at R input Timer running Scan for "1" Scan for "0" t = Programmed time Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Example T5 S_PULSE Q S S5TIME#2S TV R BI BCD I 0.0 is logic "1" as long as the timer is running and "0" if the time has elapsed or was reset. the timer T5 will be started.

Q. L. The current time value can be scanned at the outputs BI and BCD. S TV R BI BCD Q Parameter German T-Nr. M. Q. D I. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 13-7 . BCD format Status of the timer Description S_PEXT (Extended Pulse S5 Timer) starts the specified timer if there is a positive edge at the start (S) input. M. Q. The time value at BI is binary coded. M. See also "Location of a Timer in Memory and Components of a Timer". at BCD is BCD coded. range depends on CPU Start input Preset time value Reset input Remaining time value. L. D I. L. L. M.Timer Instructions 13. S TW R DUAL DEZ Q Data Type TIMER BOOL S5TIME BOOL WORD WORD BOOL Memory Area Description T I. The current time value is the initial TV value minus the time elapsed since the timer was started. M. S_PEXT S TV R Q BI BCD German T-Nr. D Timer identification number. L. The signal state at output Q is "1" as long as the timer is running. The timer will be restarted ("re-triggered") with the preset time value if the signal state at input S changes from "0" to "1" while the timer is running. The current time and the time base are set to zero. D I. Q.4 Symbol S_PEXT Extended Pulse S5 Timer English T no. D I. Q. The timer runs for the preset time interval specified at input TV even if the signal state at the S input changes to "0" before the time interval has elapsed. D I. S_VIMP S TW R Q DUAL DEZ Parameter English T no. integer format Remaining time value. Q. L. M. The timer is reset if the reset (R) input changes from "0" to "1" while the timer is running. A signal change is always necessary in order to enable a timer.

0 changes from "0" to "1" (positive edge in RLO).1 S5TIME#2S TV R Q BI BCD I 0.0 is logic "1" as long as the timer is running. the timer T5 will be started.0 Q 4. 13-8 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . The output Q4. If the signal state of I0. The timer will continue to run for the specified time of two seconds (2 s) without being affected by a negative edge at input S.0 changes from "0" to "1" before the timer has expired the timer will be re-triggered.0 If the signal state of input I0.Timer Instructions Timing Diagram Extended pulse timer characteristics: t RLO at S input t t t RLO at R input Timer running Scan for "1" Scan for "0" t = Programmed time Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Example T5 S_PEXT S I 0.

The signal state at output Q is "1" when the timer has elapsed without error and the signal state at the S input is still "1". Q. The current time value is the initial TV value minus the time elapsed since the timer was started. D I.5 Symbol S_ODT On-Delay S5 Timer English T no. Q. M. the timer is stopped. Q. L. L. When the signal state at input S changes from "1" to "0" while the timer is running. The timer is also reset if there is a logic "1" at the R input while the timer is not running and the RLO at input S is "1". M. L. See also "Location of a Timer in Memory and Components of a Timer". Q. integer format Remaining time value. The time value at BI is binary coded. M.Timer Instructions 13. The timer is reset if the reset (R) input changes from "0" to "1" while the timer is running. S TV R BI BCD Q Parameter German T-Nr. Q. A signal change is always necessary in order to enable a timer. The current time and the time base are set to zero. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 13-9 . Q. S_EVERZ S TW R Q DUAL DEZ Parameter English T no. L. S_ODT S TV R Q BI BCD German T-Nr. The signal state at output Q is then "0". S TW R DUAL DEZ Q Data Type TIMER BOOL S5TIME BOOL WORD WORD BOOL Memory Area Description T I. The current time value can be scanned at the outputs BI and BCD. The timer runs for the time interval specified at input TV as long as the signal state at input S is positive. D I. D I. D I. D I. L. BCD format Status of the timer Description S_ODT (On-Delay S5 Timer) starts the specified timer if there is a positive edge at the start (S) input. M. M. at BCD is BCD coded. range depends on CPU Start input Preset time value Reset input Remaining time value. D Timer identification number. M. In this case the signal state of output Q is "0". L.

the output Q4.0 will be "0" (if the signal state of I0.0 If the signal state of I0.0 changes from "0" to "1" (positive edge in RLO). the timer T5 will be started. 13-10 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . the time is reset regardless of whether the timer is running or not).0 Q 4.Timer Instructions Timing Diagram On-Delay timer characteristics: t RLO at S input t t RLO at R input Timer running Scan for "1" Scan for "0" t = Programmed time Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Example T5 S_ODT S I 0. the timer is stopped and Q4.0 is still "1". If the time of two seconds elapses and the signal state at input I0. If the signal state of I0.0 will be "1".0 changes from "1" to "0".1 changes from "0" to "1".1 S5TIME#2S TV R Q BI BCD I 0.

L. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 13-11 . L. Q. S TV R BI BCD Q Parameter German T-Nr. range depends on CPU Start input Preset time value Reset input Remaining time value. The timer will be restarted (re-triggered) with the specified time if the signal state at input S changes from "0" to "1" while the timer is running. L. D I.6 Symbol S_ODTS Retentive On-Delay S5 Timer English T no. M. D I. S_SEVERZ S TW R Q DUAL DEZ Parameter English T no. D Timer identification number. BCD format Status of the timer Description S_ODTS (Retentive On-Delay S5 Timer) starts the specified timer if there is a positive edge at the start (S) input. D I. M. L. The current time value can be scanned at the outputs BI and BCD. L. The timer is reset if the reset (R) input changes from "0" to "1" without regard to the RLO at the S input. The timer runs for the time interval specified at input TV even if the signal state at input S changes to "0" before the time interval has elapsed. D I. A signal change is always necessary in order to enable a timer. The current time value is the initial TV value minus the time elapsed since the timer was started. L. Q.Timer Instructions 13. The signal state at output Q is "1" when the timer has elapsed without regard to the signal state at input S. Q. S TW R DUAL DEZ Q Data Type TIMER BOOL S5TIME BOOL WORD WORD BOOL Memory Area Description T I. Q. M. M. S_ODTS S TV R Q BI BCD German T-Nr. The time value at BI is binary coded. Q. D I. at BCD it is BCD coded. M. Q. integer format Remaining time value. The signal state at output Q is then "0". M.

) 13-12 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .0 Q 4. the timer T5 will be started.0 I 0. The timer runs without regard to a signal change at I0.1 changes from "0" to "1". the timer will be re-triggered. The output Q4.0 will be "1" if the timer elapsed. If the signal state at I0.Timer Instructions Timing Diagram Retentive On-Delay timer characteristics: t RLO at S input t t t RLO at R input Timer running Scan for "1" Scan for "0" t = Programmed time Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Example T5 S_ODTS Q S S5TIME#2S TV R BI BCD I 0. (If the signal state of input I0.0 changes from "0" to "1" (positive edge in RLO). the time will be reset irrespective of the RLO at S.0 from "1" to "0".1 If the signal state of I0.0 changes from "0" to "1" before the timer has expired.

L. D I. Q. The signal state at output Q is "1" if the signal state at the S input is "1" or while the timer is running. Q. Q. S TV R BI BCD Q Parameter German T-Nr. The current time value can be scanned at the outputs BI and BCD.Timer Instructions 13. S_AVERZ S TW R Q DUAL DEZ Parameter English T no. D I. BCD format Status of the timer Description S_OFFDT (Off-Delay S5 Timer) starts the specified timer if there is a negative edge at the start (S) input. The timer is reset when the reset (R) input changes from "0" to "1" while the timer is running. M. M. Q. D Timer identification number. integer format Remaining time value. at BCD it is BCD coded. L. D I. L.7 Symbol S_OFFDT Off-Delay S5 Timer English T no. L. range depends on CPU Start input Preset time value Reset input Remaining time value. L. M. A signal change is always necessary in order to enable a timer. L. The current time value is the initial TV value minus the time elapsed since the timer was started. S_OFFDT S TV R Q BI BCD German T-Nr. The timer is not restarted until the signal state at input S changes again from "1" to "0". D I. S TW R DUAL DEZ Q Data Type TIMER BOOL S5TIME BOOL WORD WORD BOOL Memory Area Description T I. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 13-13 . D I. The time value at BI is binary coded. Q. M. M. The timer is reset when the signal state at input S goes from "0" to "1" while the timer is running. M. Q.

0 is "1" or the timer is running.0 changes from "1" to "0".0 Q 4. 13-14 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .1 If the signal state of I0. the timer is started.0 I 0. the timer is reset).0 is "1" when I0. (if the signal state at I0.Timer Instructions Timing Diagram Off-Delay timer characteristics: t RLO at S input t t t RLO at R input Timer running Scan for "1" Scan for "0" t = Programmed time Status word BR writes: CC 1 CC 0 OV OS OR x STA x RLO x /FC 1 Example T5 S_OFFDT Q S S5TIME#2S TV R BI BCD I 0. Q4.1 changes from "0" to "1" while the time is running.

8 Symbol ---( SP ) Pulse Timer Coil English <T no.. range depends on CPU Preset time value Description ---( SP ) (Pulse Timer Coil) starts the specified timer with the <time value> when there is a positive edge on the RLO state. If there is a change from "1" to "0" in the RLO before the time value has elapsed. L.> ---( SI ) <time value> Parameter <T no. the timer will stop. Status word BR writes: CC 1 CC 0 OV OS OR 0 STA RLO /FC 0 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 13-15 .> ---( SP ) <time value> German <T no. The signal state of the counter is ”1” as long as the timer is running. D Description Timer identification number. In this case. Q. See also "Location of a Timer in Memory and Components of a Timer" and S_PULSE (Pulse S5 Timer).Timer Instructions 13. The timer continues to run for the specified time interval as long as the RLO remains positive ("1"). M.> <time value> Data Type TIMER S5TIME Memory Area T I. a scan for "1" always produces the result "0".

0 T5 SP S5T#2S Network 2 T5 Q 4. The signal state of output Q4. The timer continues to run with the specified time of two seconds as long as the signal state of input I0.0 Network 3 I 0. 13-16 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . A signal state change from "0" to "1" at input I0. the timer stops.1 T5 R If the signal state of input I0.1 will reset timer T5 which stops the timer and clears the remaining portion of the time value to "0". If the signal state of input I0.0 is "1". the timer T5 is started.0 changes from "0" to "1" (positive edge in RLO).0 is "1" as long as the timer is running.Timer Instructions Example Network 1 I 0.0 changes from "1" to "0" before the specified time has elapsed.

M.> ---( SE ) <time value> German <T no> ---( SV ) <time value> Parameter <T no. The signal state of the counter is ”1” as long as the timer is running. Status word BR writes: CC 1 CC 0 OV OS OR 0 STA RLO /FC 0 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 13-17 . The timer will be restarted (re-triggered) with the specified time value if the RLO changes from "0" to "1" while the timer is running. The timer continues to run for the specified time interval even if the RLO changes to "0" before the timer has expired. Q. See also "Location of a Timer in Memory and Components of a Timer" and S_PEXT (Extended Pulse S5 Timer).> <time value> Data Type TIMER S5TIME Memory Area T I.Timer Instructions 13. range depends on CPU Preset time value Description ---( SE ) (Extended Pulse Timer Coil) starts the specified timer with the specified <time value> when there is a positive edge on the RLO state. D Description Timer identification number.9 Symbol ---( SE ) Extended Pulse Timer Coil English <T no. L.

0 changes from "0" to "1" before the timer has expired.0 T5 SE S5T#2S Network 2 T5 Q A. If the signal state of I0. The timer continues to run without regard to a negative edge of the RLO.0 Network 3 I 0.Timer Instructions Example Network 1 I 0. 13-18 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .0 changes from "0" to "1" (positive edge in RLO). the timer is re-triggered. the timer T5 is started.1 T5 R If the signal state of input I0.1 will reset timer T5 which stops the timer and clears the remaining portion of the time value to "0".0 is "1" as long as the timer is running. The signal state of output Q4. A signal state change from "0" to "1" at input I0.

a scan for "1" always produces the result "0". the timer is reset.> ---( SE ) <time value> Parameter <T no. D Description Timer identification number. The signal state of the timer is "1" when the <time value> has elapsed without error and the RLO is still "1". When the RLO changes from "1" to "0" while the timer is running.> <time value> Data Type TIMER S5TIME Memory Area T I. See also "Location of a Timer in Memory and Components of a Timer" and S_ODT (On-Delay S5 Timer). Status word BR writes: CC 1 CC 0 OV OS OR 0 STA RLO /FC 0 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 13-19 . range depends on CPU Preset time value Description ---( SD ) (On Delay Timer Coil) starts the specified timer with the <time value> if there is a positive edge on the RLO state. Q.> ---( SD ) <time value> German <T no. M.Timer Instructions 13.10 ---( SD ) On-Delay Timer Coil Symbol English <T no. L. In this case.

0 is still "1".0 Network 3 I 0. A signal state change from "0" to "1" at input I0. If the signal state of input I0.0 changes from "1" to "0". 13-20 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . the signal state of output Q4.1 will reset timer T5 which stops the timer and clears the remaining portion of the time value to "0".Timer Instructions Example Network 1 I 0. If the time elapses and the signal state of input I0.0 will be "1".1 T5 R If the signal state of input I0. the timer remains idle and the signal state of output Q4.0 T5 SD S5T#2S Network 2 T5 Q A.0 changes from "0" to "1" (positive edge in RLO). the timer T5 is started.0 will be "0".

See also "Location of a Timer in Memory and Components of a Timer" and S_ODTS (Retentive On-Delay S5 Timer). Only a reset causes the signal state of the timer to be set to "0". range depends on CPU Preset time value Description ---( SS ) (Retentive On-Delay Timer Coil) starts the specified timer if there is a positive edge on the RLO state.> ---( SS ) <time value> Parameter <T no.Timer Instructions 13.11 ---( SS ) Retentive On-Delay Timer Coil Symbol English <T no. D Description Timer identification number. The signal state of the timer is "1" if the time value has elapsed.> ---( SS ) <time value> German <T no.> <time value> Data Type TIMER S5TIME Memory Area T I. A restart of the timer is only possible if it is reset explicitly. M. Status word BR writes: CC 1 CC 0 OV OS OR 0 STA RLO /FC 0 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 13-21 . Q. L. The timer restarts with the specified time value if the RLO changes from "0" to "1" while the timer is running.

0 changes from "0" to "1" before the timer has expired. 13-22 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .Timer Instructions Example Network 1 I 0.0 will be "1" if the timer elapsed. If the signal state of input I0.1 will reset timer T5.0 Network 3 I 0. which stops the timer and clears the remaining portion of the time value to "0". A signal state "1" at input I0.0 T5 SS S5T#2S Network 2 T5 Q A. the timer is re-triggered.1 T5 R If the signal state of input I0.0 changes from "0" to "1" (positive edge in RLO). the timer T5 is started. The output Q4.

L. D Description Timer identification number. The timer is always restarted when the RLO changes from "1" to "0".> <time value> Data Type TIMER S5TIME Memory Area T I.> ---( SA ) <time value> Parameter <T no. Status word BR writes: CC 1 CC 0 OV OS OR 0 STA RLO /FC 0 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 13-23 .12 ---( SF ) Off-Delay Timer Coil Symbol English <T no. See also "Location of a Timer in Memory and Components of a Timer" and S_OFFDT (Off-Delay S5 Timer). M. Q. range depends on CPU Preset time value Description ---( SF ) (Off-Delay Timer Coil) starts the specified timer if there is a negative edge on the RLO state.Timer Instructions 13. The timer is reset when the RLO goes from "0" to "1" while the timer is running.> ---( SF ) <time value> German <T no. The timer is "1" when the RLO is "1" or as long as the timer is running during the <time value> interval.

0 is "1" or the timer is running.0 Network 3 I 0. 13-24 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .Timer Instructions Example Network 1 I 0.0 T5 SF S5T#2S Network 2 T5 Q A.0 is "1" when input I0.1 T5 R If the signal state of input I0.0 changes from "1" to "0" the timer is started. A signal state change from "0" to "1" at input I0. The signal state of output Q4.1 will reset timer T5 which stops the timer and clears the remaining portion of the time value to "0".

bit CC 1 of the status word is set to "0". The following word logic instructions are available: • • • • • • WAND_W WOR_W WXOR_W (Word) AND Word (Word) OR Word (Word) Exclusive OR Word WAND_DW (Word) AND Double Word WOR_DW (Word) OR Double Word WXOR_DW (Word) Exclusive OR Double Word Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 14-1 . bit CC 1 of the status word is set to "1". If the result at output OUT does not equal 0.1 Overview of Word logic instructions Description Word logic instructions compare pairs of words (16 bits) and double words (32 bits) bit by bit. according to Boolean logic. If the result at output OUT does equal 0.14 Word Logic Instructions 14.

D Description Enable input Enable output First value for logic operation Second value for logic operation Result word of logic operation Description WAND_W (AND Words) is activated by signal state "1" at the enable (EN) input and ANDs the two word values present at IN1 and IN2 bit by bit. The values are interpreted as pure bit patterns. Status word BR writes: 1 CC 1 x CC 0 0 OV 0 OS OR x STA 1 RLO 1 /FC 1 Example I 0. Q. Q.0 is "1" if the instruction is executed. Q. L. ENO has the same logic state as EN. Only bits 0 to 3 of MW0 are relevant. 14-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . M. The result can be scanned at the output OUT. D I. M. Q.0 MW0 2#0000000000001111 WAND_W Q 4.0 MW2 EN IN1 IN2 ENO OUT The instruction is executed if I0. D I.0 is "1". D I. L. M. Q.Word Logic Instructions 14. M. L. the rest of MW0 is masked by the IN2 word bit pattern: MW0 IN2 MW0 AND IN2 = MW2 = = = 01010101 01010101 00000000 00001111 00000000 00000101 Q4. D I. M.2 Symbol WAND_W (Word) AND Word WAND_W EN IN1 IN2 ENO OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL WORD WORD WORD Memory Area I. L. L.

Q.Word Logic Instructions 14.0 MW2 EN IN1 IN2 ENO OUT The instruction is executed if I0. Q. all other MW0 bits are not changed. D I. M. MW0 IN2 MW0 OR IN2=MW2 = = = 01010101 01010101 00000000 00001111 01010101 01011111 Q4. M. D I. The result can be scanned at the output OUT. D I. D I.3 Symbol WOR_W (Word) OR Word WOR_W EN IN1 IN2 ENO OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL WORD WORD WORD Memory Area I. M. M. Q.0 MW0 2#0000000000001111 WOR_W Q 4. Bits 0 to 3 are set to "1". L. Q. M. L. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 14-3 . Q. L. L. ENO has the same logic state as EN. D Description Enable input Enable output First value for logic operation Second value for logic operation Result word of logic operation Description WOR_W (OR Words) is activated by signal state "1" at the enable (EN) input and ORs the two word values present at IN1 and IN2 bit by bit.0 is "1". Status word BR writes: 1 CC 1 x CC 0 0 OV 0 OS OR x STA 1 RLO 1 /FC 1 Example I 0. The values are interpreted as pure bit patterns.0 is "1" if the instruction is executed. L.

D I.Word Logic Instructions 14.0 MD4 EN IN1 IN2 ENO OUT The instruction is executed if I0. M. L. Q. L. L. The values are interpreted as pure bit patterns.0 is "1" if the instruction is executed. Q. M. M. Q.4 Symbol WAND_DW (Word) AND Double Word WAND_DW EN IN1 IN2 ENO OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL DWORD DWORD DWORD Memory Area I. Only bits 0 and 11 of MD0 are relevant. 14-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . The result can be scanned at the output OUT.0 MD0 DW#16#FFF WAND_DW Q 4. ENO has the same logic state as EN. D I.0 is "1". D I. L. L. D I. M. D Description Enable input Enable output First value for logic operation Second value for logic operation Result double word of logic operation Description WAND_DW (AND Double Words) is activated by signal state "1" at the enable (EN) input and ANDs the two word values present at IN1 and IN2 bit by bit. M. Status word BR writes: 1 CC 1 x CC 0 0 OV 0 OS OR x STA 1 RLO 1 /FC 1 Example I 0. the rest of MD0 is masked by the IN2 bit pattern: MD0 IN2 MD0 AND IN2 = MD4 = = = 01010101 01010101 01010101 01010101 00000000 00000000 00001111 11111111 00000000 00000000 00000101 01010101 Q4. Q. Q.

The result can be scanned at the output OUT. L.0 MD4 EN IN1 IN2 ENO OUT The instruction is executed if I0. Status word BR writes: 1 CC 1 x CC 0 0 OV 0 OS OR x STA 1 RLO 1 /FC 1 Example I 0. M. the remaining MD0 bits are not changed: MD0 IN2 MD0 OR IN2 = MD4 = = = 01010101 01010101 01010101 01010101 00000000 00000000 00001111 11111111 01010101 01010101 01011111 11111111 Q4. Q.Word Logic Instructions 14. D I. M. M. ENO has the same logic state as EN. M. D Description Enable input Enable output First value for logic operation Second value for logic operation Result double word of logic operation Description WOR_DW (OR Double Words) is activated by signal state "1" at the enable (EN) input and ORs the two word values present at IN1 and IN2 bit by bit. D I.0 is "1" if the instruction is executed. D I. L. M. The values are interpreted as pure bit patterns.0 is "1". Q.0 MD0 DW#16#FFF WOR_DW Q 4. Bits 0 to 11 are set to "1". D I. L. Q. L. Q. L.5 Symbol WOR_DW (Word) OR Double Word WOR_DW EN IN1 IN2 ENO OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL DWORD DWORD DWORD Memory Area I. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 14-5 . Q.

L. L. Q. 14-6 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .0 MW0 2#0000000000001111 WXOR_W Q 4.Word Logic Instructions 14. Q. L. L. M. M. M.0 MW2 EN IN1 IN2 ENO OUT The instruction is executed if I0. M. M. Status word BR writes: 1 CC 1 x CC 0 0 OV 0 OS OR x STA 1 RLO 1 /FC 1 Example I 0. The result can be scanned at the output OUT. Q. ENO has the same logic state as EN. Q. D I.0 is "1" if the instruction is executed. D I. D I.0 is "1": MW0 IN2 MW0 XOR IN2 = MW2 = = = 01010101 01010101 00000000 00001111 01010101 01011010 Q4. L. D Description Enable input Enable output First value for logic operation Second value for logic operation Result word of logic operation Description WXOR_W (Exclusive OR Word) is activated by signal state "1" at the enable (EN) input and XORs the two word values present at IN1 and IN2 bit by bit. Q. D I. The values are interpreted as pure bit patterns.6 Symbol WXOR_W (Word) Exclusive OR Word WXOR_W EN IN1 IN2 ENO OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL WORD WORD WORD Memory Area I.

Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 14-7 . D I. M. M. Q. L. Q. M. ENO has the same logic state as EN. Status word BR writes: 1 CC 1 x CC 0 0 OV 0 OS OR x STA 1 RLO 1 /FC 1 Example I 0.0 is "1" if the instruction is executed. M. D I. L. Q. Q.0 MD4 EN IN1 IN2 ENO OUT The instruction is executed if I0. The values are interpreted as pure bit patterns. Q.7 Symbol WXOR_DW (Word) Exclusive OR Double Word WXOR_DW EN IN1 IN2 ENO OUT Parameter EN ENO IN1 IN2 OUT Data Type BOOL BOOL DWORD DWORD DWORD Memory Area I.0 MD0 DW#16#FFF WXOR_DW Q 4. L. D I. M. L. D Description Enable input Enable output First value for logic operation Second value for logic operation Result double word of logic operation Description WXOR_DW (Exclusive OR Double Word) is activated by signal state "1" at the enable (EN) input and XORs the two word values present at IN1 and IN2 bit by bit.Word Logic Instructions 14. L. D I. The result can be scanned at the output OUT.0 is "1": MD0 IN2 MW2 = MD0 XOR IN2 = = = 01010101 01010101 01010101 01010101 00000000 00000000 00001111 11111111 01010101 01010101 01011010 10101010 Q4.

Word Logic Instructions 14-8 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

A Overview of All LAD Instructions A.1 LAD Instructions Sorted According to English Mnemonics (International) Description Normally Open Contact (Address) Normally Closed Contact (Address) Output Coil Midline Output Result Bit Equal 0 Result Bit Greater Than 0 Result Bit Greater Equal 0 Result Bit Less Equal 0 Result Bit Less Than 0 Result Bit Not Equal 0 Establish the Absolute Value of a Floating-Point Number Establish the Arc Cosine Value Add Double Integer Add Integer Add Real Establish the Arc Sine Value Establish the Arc Tangent Value BCD to Double Integer BCD to Integer Exception Bit Binary Result Call FC SFC from Coil (without Parameters) Call FB from Box Call FC from Box Call System FB from Box English German Program Elements Mnemonics Mnemonics Catalog ---| |-----|/|-----( ) ---(#)--==0 ---| |-->0 ---| |-->=0 ---| |--<=0 ---| |--<0 ---| |--<>0 ---| |--ABS ACOS ADD_DI ADD_I ADD_R ASIN ATAN BCD_DI BCD_I BR ---| |------(CALL) CALL_FB CALL_FC CALL_SFB ---| |-----|/|-----( ) ---(#)--==0 ---| |-->0 ---| |-->=0 ---| |--<=0 ---| |--<0 ---| |--<>0 ---| |--ABS ACOS ADD_DI ADD_I ADD_R ASIN ATAN BCD_DI BCD_I BIE ---| |------(CALL) CALL_FB CALL_FC CALL_SFB Bit logic Instruction Bit logic Instruction Bit logic Instruction Bit logic Instruction Status bits Status bits Status bits Status bits Status bits Status bits Floating point Instruction Floating point Instruction Integer Math Instruction Integer Math Instruction Floating point Instruction Floating point Instruction Floating point Instruction Convert Convert Status bits Program control Program control Program control Program control Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 A-1 .

<=) Compare Integer (==. >. <>. >=. >. >. <>. >=. <. <.Overview of All LAD Instructions English German Program Elements Mnemonics Mnemonics Catalog CALL_SFC ----(CD) CEIL CMP >=D CMP >=I CMP >=R COS ----(CU) DI_BCD DI_R DIV_DI DIV_I DIV_R EXP FLOOR I_BCD I_DI INV_I INV_DI ---(JMP) ---(JMP) ---(JMPN) LABEL LN ---(MCR>) ---(MCR<) ---(MCRA) ---(MCRD) MOD_DI MOVE MUL_DI MUL_I MUL_R ---( N )--CALL_SFC ----(ZR) CEIL CMP >=D CMP >=I CMP >=R COS ---( ZV ) DI_BCD DI_R DIV_DI DIV_I DIV_R EXP FLOOR I_BCD I_DI INV_I INV_DI ---(JMP) ---(JMP) ---(JMPN) LABEL LN ---(MCR>) ---(MCR<) ---(MCRA) ---(MCRD) MOD_DI MOVE MUL_DI MUL_I MUL_R ---( N )--Program control Counters Convert Compare Compare Compare Floating point Instruction Counters Convert Convert Integer Math Instruction Integer Math Instruction Floating point Instruction Floating point Instruction Convert Convert Convert Convert Convert Jumps Jumps Jumps Jumps Floating point Instruction Program control Program control Program control Program control Integer Math Instruction Move Integer Math Instruction Integer Math Instruction Floating point Instruction Bit logic Instruction Description Call System FC from Box Down Counter Coil Ceiling Compare Double Integer (==. <=) Establish the Cosine Value Up Counter Coil Double Integer to BCD Double Integer to Floating-Point Divide Double Integer Divide Integer Divide Real Establish the Exponential Value Floor Integer to BCD Integer to Double Integer Ones Complement Integer Ones Complement Double Integer Unconditional Jump Conditional Jump Jump-If-Not Label Establish the Natural Logarithm Master Control Relay Off Master Control Relay On Master Control Relay Activate Master Control Relay Deactivate Return Fraction Double Integer Assign a Value Multiply Double Integer Multiply Integer Multiply Real Negative RLO Edge Detection Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 A-2 . <. >=. <=) Compare Real (==. <>.

Overview of All LAD Instructions English German Program Elements Mnemonics Mnemonics Catalog NEG NEG_DI NEG_I NEG_R ---| NOT |-----( OPN ) OS ---| |--OV ---| |-----( P )--POS ---( R ) ---(RET) ROL_DW ROR_DW ROUND RS ---( S ) ---( SAVE ) ---( SC ) S_CD S_CU S_CUD ---( SD ) ---( SE ) ---( SF ) SHL_DW SHL_W SHR_DI SHR_DW SHR_I SHR_W SIN S_ODT S_ODTS S_OFFDT ---( SP ) S_PEXT S_PULSE SQR NEG NEG_DI NEG_I NEG_R ---| NOT |-----( OPN ) OS ---| |--OV ---| |-----( P )--POS ---( R ) ---(RET) ROL_DW ROR_DW ROUND RS ---( S ) ---( SAVE ) ---( SZ ) Z_RUECK Z_VORW ZAEHLER ---( SE ) ---( SV ) ---( SA ) SHL_DW SHL_W SHR_DI SHR_DW SHR_I SHR_W SIN S_EVERZ S_SEVERZ S_AVERZ ---( SI ) S_VIMP S_IMPULS SQR Bit logic Instruction Convert Convert Convert Bit logic Instruction DB call Status bits Status bits Bit logic Instruction Bit logic Instruction Bit logic Instruction Program control Shift/Rotate Shift/Rotate Convert Bit logic Instruction Bit logic Instruction Bit logic Instruction Counters Counters Counters Counters Timers Timers Timers Shift/Rotate Shift/Rotate Shift/Rotate Shift/Rotate Shift/Rotate Shift/Rotate Floating point Instruction Timers Timers Timers Timers Timers Timers Floating point Instruction Description Address Negative Edge Detection Twos Complement Double Integer Twos Complement Integer Negate Floating-Point Number Invert Power Flow Open Data Block: DB or DI Exception Bit Overflow Stored Exception Bit Overflow Positive RLO Edge Detection Address Positive Edge Detection Reset Coil Return Rotate Left Double Word Rotate Right Double Word Round to Double Integer Reset-Set Flip Flop Set Coil Save RLO into BR Memory Set Counter Value Down Counter Up Counter Up-Down Counter On-Delay Timer Coil Extended Pulse Timer Coil Off-Delay Timer Coil Shift Left Double Word Shift Left Word Shift Right Double Integer Shift Right Double Word Shift Right Integer Shift Right Word Establish the Sine Value On-Delay S5 Timer Retentive On-Delay S5 Timer Off-Delay S5 Timer Pulse Timer Coil Extended Pulse S5 Timer Pulse S5 Timer Establish the Square Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 A-3 .

Overview of All LAD Instructions English German Program Elements Mnemonics Mnemonics Catalog SQRT SR ---( SS ) SUB_DI SUB_I SUB_R TAN TRUNC UO ---| |--WAND_DW WAND_W WOR_DW WOR_W WXOR_DW WXOR_W SQRT SR ---( SS ) SUB_DI SUB_I SUB_R TAN TRUNC UO ---| |--WAND_DW WAND_W WOR_DW WOR_W WXOR_DW WXOR_W Floating point Instruction Bit logic Instruction Timers Integer Math Instruction Integer Math Instruction Floating point Instruction Floating point Instruction Convert Status bits Word logic Instruction Word logic Instruction Word logic Instruction Word logic Instruction Word logic Instruction Word logic Instruction Description Establish the Square Root Set-Reset Flip Flop Retentive On-Delay Timer Coil Subtract Double Integer Subtract Integer Subtract Real Establish the Tangent Value Truncate Double Integer Part Exception Bit Unordered AND Double Word AND Word OR Double Word OR Word Exclusive OR Double Word Exclusive OR Word A-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

<=) Compare Integer (==. <. <. >. >=. <>. >. <. >. <=) Establish the Cosine Value Double Integer to BCD German English Program Mnemonics Mnemonics Elements Catalog ---| |-----|/|-----( ) ---(#)--==0 ---| |-->0 ---| |-->=0 ---| |--<=0 ---| |--<0 ---| |--<>0 ---| |--ABS ACOS ADD_DI ADD_I ADD_R ASIN ATAN BCD_DI BCD_I BIE ---| |------(CALL) CALL_FB CALL_FC CALL_SFB CALL_SFC CEIL CMP >=D CMP >=I CMP >=R COS DI_BCD ---| |-----|/|-----( ) ---(#)--==0 ---| |-->0 ---| |-->=0 ---| |--<=0 ---| |--<0 ---| |--<>0 ---| |--ABS ACOS ADD_DI ADD_I ADD_R ASIN ATAN BCD_DI BCD_I BR ---| |------(CALL) CALL_FB CALL_FC CALL_SFB CALL_SFC CEIL CMP >=D CMP >=I CMP >=R COS DI_BCD Bit logic Instruction Bit logic Instruction Bit logic Instruction Bit logic Instruction Status bits Status bits Status bits Status bits Status bits Status bits Floating point Instruction Floating point Instruction Integer Math Instruction Integer Math Instruction Floating point Instruction Floating point Instruction Floating point Instruction Convert Convert Status bits Program control Program control Program control Program control Program control Convert Compare Compare Compare Floating point Instruction Convert Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 A-5 . >=. <>. <>. >=. <=) Compare Real (==.2 LAD Instructions Sorted According to German Mnemonics (SIMATIC) Description Normally Open Contact (Address) Normally Closed Contact (Address) Output Coil Midline Output Result Bit Equal 0 Result Bit Greater Than 0 Result Bit Greater Equal 0 Result Bit Less Equal 0 Result Bit Less Than 0 Result Bit Not Equal 0 Establish the Absolute Value of a Floating-Point Number Establish the Arc Cosine Value Add Double Integer Add Integer Add Real Establish the Arc Sine Value Establish the Arc Tangent Value BCD to Double Integer BCD to Integer Exception Bit Binary Result Call FC SFC from Coil (without Parameters) Call FB from Box Call FC from Box Call System FB from Box Call System FC from Box Ceiling Compare Double Integer (==.Overview of All LAD Instructions A.

Overview of All LAD Instructions German English Program Mnemonics Mnemonics Elements Catalog DI_R DIV_DI DIV_I DIV_R EXP FLOOR I_BCD I_DI INV_I INV_DI ---(JMP) ---(JMP) ---(JMPN) LABEL LN ---(MCR>) ---(MCR<) ---(MCRA) ---(MCRD) MOD_DI MOVE MUL_DI MUL_I MUL_R ---( N )--NEG NEG_DI NEG_I NEG_R ---| NOT |-----( OPN ) OS ---| |--OV ---| |-----( P )--DI_R DIV_DI DIV_I DIV_R EXP FLOOR I_BCD I_DI INV_I INV_DI ---(JMP) ---(JMP) ---(JMPN) LABEL LN ---(MCR>) ---(MCR<) ---(MCRA) ---(MCRD) MOD_DI MOVE MUL_DI MUL_I MUL_R ---( N )--NEG NEG_DI NEG_I NEG_R ---| NOT |-----( OPN ) OS ---| |--OV ---| |-----( P )--Convert Integer Math Instruction Integer Math Instruction Floating point Instruction Floating point Instruction Convert Convert Convert Convert Convert Jumps Jumps Jumps Jumps Floating point Instruction Program control Program control Program control Program control Integer Math Instruction Move Integer Math Instruction Integer Math Instruction Floating point Instruction Bit logic Instruction Bit logic Instruction Convert Convert Convert Bit logic Instruction DB call Status bits Status bits Bit logic instructio Description Double Integer to Floating-Point Divide Double Integer Divide Integer Divide Real Establish the Exponential Value Floor Integer to BCD Integer to Double Integer Ones Complement Integer Ones Complement Double Integer Conditional Jump Unconditional Jump Jump-If-Not Label Establish the Natural Logarithm Master Control Relay Off Master Control Relay On Master Control Relay Activate Master Control Relay Deactivate Return Fraction Double Integer Assign a Value Multiply Double Integer Multiply Integer Multiply Real Negative RLO Edge Detection Address Negative Edge Detection Twos Complement Double Integer Twos Complement Integer Negate Floating-Point Number Invert Power Flow Open Data Block: DB or DI Exception Bit Overflow Stored Exception Bit Overflow Positive RLO Edge Detection A-6 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

Overview of All LAD Instructions German English Program Mnemonics Mnemonics Elements Catalog POS ---( R ) ---(RET) ROL_DW ROR_DW ROUND RS ---( S ) ---( SA ) ---( SAVE ) S_AVERZ ---( SE ) S_EVERZ SHL_DW SHL_W SHR_DI SHR_DW SHR_I SHR_W ---( SI ) S_IMPULS SIN SQR SQRT SR ---( SS ) S_SEVERZ SUB_DI SUB_I SUB_R ---( SV ) S_VIMP ---( SZ ) TAN TRUNC UO ---| |--POS ---( R ) ---(RET) ROL_DW ROR_DW ROUND RS ---( S ) ---( SF ) ---( SAVE ) S_OFFDT ---( SD ) S_ODT SHL_DW SHL_W SHR_DI SHR_DW SHR_I SHR_W ---( SP ) S_PULSE SIN SQR SQRT SR ---( SS ) S_ODTS SUB_DI SUB_I SUB_R ---( SE ) S_PEXT ---( SC ) TAN TRUNC UO ---| |--Bit logic Instruction Bit logic Instruction Program control Shift/Rotate Shift/Rotate Convert Bit logic Instruction Bit logic Instruction Timers Bit logic Instruction Timers Timers Timers Shift/Rotate Shift/Rotate Shift/Rotate Shift/Rotate Shift/Rotate Shift/Rotate Timers Timers Floating point Instruction Floating point Instruction Floating point Instruction Bit logic Instruction Timers Timers Integer Math Instruction Integer Math Instruction Floating point Instruction Timers Timers Counters Floating point Instruction Convert Status bits Description Address Positive Edge Detection Reset Coil Return Rotate Left Double Word Rotate Right Double Word Round to Double Integer Reset-Set Flip Flop Set Coil Off-Delay Timer Coil Save RLO into BR Memory Off-Delay S5 Timer On-Delay Timer Coil On-Delay S5 Timer Shift Left Double Word Shift Left Word Shift Right Double Integer Shift Right Double Word Shift Right Integer Shift Right Word Pulse Timer Coil Pulse S5 Timer Establish the Sine Value Establish the Square Establish the Square Root Set-Reset Flip Flop Retentive On-Delay Timer Coil Retentive On-Delay S5 Timer Subtract Double Integer Subtract Integer Subtract Real Extended Pulse Timer Coil Extended Pulse S5 Timer Set Counter Value Establish the Tangent Value Truncate Double Integer Part Exception Bit Unordered Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 A-7 .

Overview of All LAD Instructions German English Program Mnemonics Mnemonics Elements Catalog WAND_DW WAND_W WOR_DW WOR_W WXOR_DW WXOR_W ZAEHLER ----(ZR) Z_RUECK ---( ZV ) Z_VORW WAND_DW WAND_W WOR_DW WOR_W WXOR_DW WXOR_W S_CUD ----(CD) S_CD ----(CU) S_CU Word logic Instruction Word logic Instruction Word logic Instruction Word logic Instruction Word logic Instruction Word logic Instruction Counters Counters Counters Counters Counters Description AND Double Word AND Word OR Double Word OR Word Exclusive OR Double Word Exclusive OR Word Up-Down Counter Down Counter Coil Down Counter Up Counter Coil Up Counter A-8 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .

This chapter provides the following examples of practical applications of the ladder logic instructions: • • • • • • Controlling a conveyor belt using bit logic instructions Detecting direction of movement on a conveyor belt using bit logic instructions Generating a clock pulse using timer instructions Keeping track of storage space using counter and comparison instructions Solving a problem using integer math instructions Setting the length of time for heating an oven Instructions Used Mnemonik WAND_W WOR_W --.( SE ) Program Elements Catalog Word logic instruction Word logic instruction Counters Counters Bit logic instruction Bit logic instruction Bit logic instruction Floating-Point instruction Floating-Point instruction Floating-Point instruction Compare Bit logic instruction Bit logic instruction Bit logic instruction Jumps Program control Move Timers Description (Word) And Word (Word) Or Word Down Counter Coil Up Counter Coil Reset Coil Set Coil Positive RLO Edge Detection Add Integer Divide Integer Multiply Integer Compare Integer Normally Open Contact Normally Closed Contact Output Coil Jump-If-Not Return Assign a Value Extended Pulse Timer Coil Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 B-1 .( CD ) --. CMP >=I ––| |–– ––| / |–– ––( ) ---( JMPN ) ---( RET ) MOVE --.1 Overview of Programming Examples Practical Applications Each ladder logic instruction described in this manual triggers a specific operation. you can accomplish a wide variety of automation tasks.( CU ) ---( R ) ---( S ) ---( P ) ADD_I DIV_I MUL_I CMP <=I.B Programming Examples B. When you combine these instructions into a program.

Sensor S5 MOTOR_ON S1 S2 O Start O Stop S3 S4 O Start O Stop Absolute and symbolic Programming You can write a program to control the conveyor belt using absolute values or symbols that represent the various components of the conveyor system.3 I 1. sensor S5 stops the belt when an item on the belt reaches the end. There are two push button switches at the beginning of the belt: S1 for START and S2 for STOP. You need to make a symbol table to correlate the symbols you choose with absolute values (see the STEP 7 Online Help).2 I 1.4 I 1.0 S1 S2 S3 S4 S5 MOTOR_ON B-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .4 I 1.3 I 1.2 Example: Bit Logic Instructions Example 1: Controlling a Conveyor Belt The following figure shows a conveyor belt that can be activated electrically. Also.5 Q 4.5 Q 4.1 I 1. There are also two push button switches at the end of the belt: S3 for START and S4 for STOP.Programming Examples B.1 I 1.2 I 1. It it possible to start or stop the belt from either end.0 Symbol S1 S2 S3 S4 S5 MOTOR_ON Symbol Table I 1. System Component Push Button Start Switch Push Button Stop Switch Push Button Start Switch Push Button Stop Switch Sensor Motor Absolute Address I 1.

S1 I 1.3 Network 2: Pressing either stop switch or opening the normally closed contact at the end of the belt turns the motor off. S2 I 1.4 S5 I 1.Programming Examples Ladder Logic Program to control the conveyor belt Network 1: Pressing either start switch turns the motor on.5 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 B-3 .0 S S3 I 1.2 Q 4.0 R S4 I 1.1 Q 4.

0 I 0. Q 4. System Component Photoelectric barrier 1 Photoelectric barrier 2 Display for movement to left Pulse memory bit 1 Pulse memory bit 2 Absolute Address I 0.0 M 0.0 B-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .1 Q 4.1 Symbol PEB1 PEB2 RIGHT LEFT PMB1 PMB2 Symbol Table I 0.1 M 0.Programming Examples Example 2: Detecting the Direction of a Conveyor Belt The following figure shows a conveyor belt that is equipped with two photoelectric barriers (PEB1 and PEB2) that are designed to detect the direction in which a package is moving on the belt.1 Q 4.0 PEB2 PEB1 Q 4.1 PEB1 PEB2 RIGHT LEFT PMB1 PMB2 Display for movement to right Q 4.1 Absolute and symbolic Programming You can write a program to activate a direction display for the conveyor belt system using absolute values or symbols that represent the various components of the conveyor system. You need to make a symbol table to correlate the symbols you choose with absolute values (see the STEP 7 Online Help).0 I 0. Each photoelectric light barrier functions like a normally open contact.1 M 0.0 M 0.0 Q 4.

the signal state at input I 0. at the same time. at the same time. PEB1 I 0. PEB2 I 0.0 and. PEB1 I 0.0 R LEFT Q 4. this means that there is a package between the barriers.1 PMB2 M 0.0 RIGHT Q 4.0 PMB1 M 0.Programming Examples Ladder Logic Program for Detecting the Direction of a Conveyor Belt Network 1: If there is a transition in signal state from 0 to 1 (positive edge) at input I 0.0 is 0.0 PEB2 I 0.1 RIGHT Q 4. then the package on the belt is moving to the right. then there is no package between the barriers. The direction pointer shuts off.1 S Network 2: If there is a transition in signal state from 0 to 1 (positive edge) at input I 0.1 R Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 B-5 . then the package on the belt is moving to the left.0 P PEB2 I 0.1 P PEB1 I 0. If one of the photoelectric light barriers is broken.0 S Network 3: If neither photoelectric barrier is broken.1 and.1 LEFT Q 4. the signal state at input I 0.1 is 0.

ADD_I EN MW100 1 IN1 IN2 ENO OUT MW100 B-6 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . however. load the time value 250 ms into T1 and start T1 as an extended-pulse timer. the memory word 100 is incremented by 1. illustrates the use of timer functions to generate a clock pulse. A clock pulse generator is common in a signalling system that controls the flashing of indicator lamps. you can implement the clock pulse generator function by using time-driven processing in special organization blocks.2 T1 SE S5T#250MS Network 2: The state of the timer is saved temporarily in an auxiliary memory marker. The example shown in the following ladder logic program. M0.3 Example: Timer Instructions Clock Pulse Generator You can use a clock pulse generator or flasher relay when you need to produce a signal that repeats periodically. M0. Ladder Logic Program to Generate a Clock Pulse (pulse duty factor 1:1) Network 1: If the signal state of timer T1 is 0.Programming Examples B. T1 M0.2 M001 JMP Network 4: When the timer T1 expires. jump to jump label M001. The sample program shows how to implement a freewheeling clock pulse generator by using a timer. When you use the S7-300.2 Network 3: If the signal state of timer T1 is 1.

Programming Examples Network 5: The MOVE instruction allows you to output the different clock frequencies at outputs Q12.2. The negated (inverted) RLO: 1 0 250 ms Every 250 ms the RLO bit is 0. the signal check made by ––| / |–– M0.2 produces a signal state of 1 only briefly. 1 0 250 ms As soon as the time runs out. The jump is ignored and the contents of memory word MW100 is incremented by 1. Because of this.7.0 through Q13. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 B-7 . the timer is restarted. M001 MOVE EN MW100 IN ENO OUT AW12 Signal Check A signal check of timer T1 produces the following result of logic operation (RLO) for opener M0.

5 0.Programming Examples Achieving a Specific Frequency From the individual bits of memory bytes MB101 and MB100 you can achieve the following frequencies: Bits of MB101/MB100 M 101.0002441 0.0 0.0625 0.6 M 101.5 s off) (1 s on / 1 s off) (2 s on / 2 s off) (4 s on / 4 s off) (8 s on / 8 s off) (16 s on / 16 s off) (32 s on / 32 s off) (64 s on / 64 s off) (128 s on / 128 s off) (256 s on / 256 s off) (512 s on / 512 s off) (1024 s on / 1024 s off) (2048 s on / 2048 s off) (4096 s on / 4096 s off) 16384 s (8192 s on / 8192 s off) Signal states of the Bits of Memory MB 101 Scan Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 Bit 7 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Time Value in ms 250 250 250 250 250 250 250 250 250 250 250 250 250 B-8 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .125 0.7 Frequency in Hz 2.1 M 100.0 M 101.7 M 100.015625 0.5 M 100.03125 0.2 M 100.0019531 0.0004882 0.0009765 0.0 M 100.2 M 101.5 M 101.3 M 100.0078125 0.6 M 100.0039062 0.000122 0.4 M 101.5 s 1s 2s 4s 8s 16 s 32 s 64 s 128 s 256 s 512 s 1024 s 2048 s 4096 s 8192 s (250 ms on / 250 ms off) (0.000061 Duration 0.3 M 101.25 0.5 s on / 0.0 1.1 M 101.4 M 100.

1 1 0 Time 0 250 ms 0.75 s 1 s 1.5 s Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 B-9 .Programming Examples Signal state of Bit 1 of MB 101 (M 101.5 s 0.25 s 1.1) Frequency = 1/T = 1/1 s = 1 Hz T M 101.

Conveyor belt 1 delivers packages to the storage area.Programming Examples B.0) Storage area not empty (Q 12. A display panel with five lamps indicates the fill level of the temporary storage area.4) Packages in I 12. Conveyor belt 2 transports packages from the temporary storage area to a loading dock where trucks take the packages away for delivery to customers. A photoelectric barrier at the end of conveyor belt 1 near the storage area determines how many packages are delivered to the storage area.2) Storage area 90% full (Q 15.1 Packages out Conveyor belt 1 Photoelectric barrier 1 Conveyor belt 2 Photoelectric barrier 2 B-10 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 .0 Temporary storage area for 100 packages I 12.4 Example: Counter and Comparison Instructions Storage Area with Counter and Comparator The following figure shows a system with two conveyor belts and a temporary storage area in between them.1) Storage area 50% full (Q 15. A photoelectric barrier at the end of conveyor belt 2 near the storage area determines how many packages leave the storage area to go to the loading dock. Display Panel Storage area empty (Q 12.3) Storage area Filled to capacity (Q 15.

Q12.1 Q 12. A signal change from “0” to “1” at input R resets the counter value to “0”.1 CD I 12.3 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 B-11 .0 indicates ”storage area empty”.2 S C#10 I 12. the indicator lamp for “storage area 90% full” is lit. C1 S_CUD CU I 12.2 Network 4: Network 4: If the counter value is greater than or equal to 90.Programming Examples Ladder Logic Program that Activates the Indicator Lamps on the Display Panel Network 1: Counter C1 counts up at each signal change from “0” to “1” at input CU and counts down at each signal change from “0” to “1” at input CD. CMP <= I 50 MW210 IN1 IN2 Q 15. With a signal change from “0” to ”1” at input S. the counter value is set to the value PV.1 indicates “storage area not empty”. Q 12. the indicator lamp for “storage area 50% full” is lit. CMP >= I MW210 90 IN1 IN2 Q 15.1 Network 3: If 50 is less than or equal to the counter value (in other words if the current counter value is greater than or equal to 50).3 R CV_BCD MW200 PV CV MW210 Q I 12.0 Q 12. MW200 contains the current counter value of C1.1 Network 2: Q12.

CMP >= I MW210 100 IN1 IN2 Q 15.Programming Examples Network 5: If the counter value is greater than or equal to 100.4 B. ADD_I EN IW0 DBW3 IN1 IN2 OUT ENO MW100 MW100 15 MUL_I EN IN1 IN2 OUT ENO MW102 MW102 MW0 DIV_I EN IN1 IN2 OUT MW4 ENO B-12 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . MW102 is divided by MW0 with the result stored in MW4. the indicator lamp for “storage area full” is lit. MW100 is then multiplied by 15 and the answer stored in memory word MW102.5 Example: Integer Math Instructions Solving a Math Problem The sample program shows you how to use three integer math instructions to produce the same result as the following equation: MW4 = ((IW0 + DBW3) x 15) / MW0 Ladder Logic Program Network 1: Open Data Block DB1. DB1 OPN Network 2: Input word IW0 is added to shared data word DBW3 (data block must be defined and opened) and the sum is loaded into memory word MW100.

. 1001 4 4 .6 Example: Word Logic Instructions Heating an Oven The operator of the oven starts the oven heating by pushing the start push button.3 Q 4.7 .0 to I 1.4 to I 1........0 0001 7.7 I 0. Thumbwheels for setting BCD digits Oven 4 Heat Q 4.0 to I 0. The value that the operator sets indicates seconds in binary coded decimal (BCD) format.0 0001 Bits IW0 Bytes IB1 System Component Start Push Button Thumbwheel for ones Thumbwheel for tes Thumbwheel for hundreds Heating starts Absolute Address I 0. The operator can set the length of time for heating by using the thumbwheel switches shown in the figure.Programming Examples B. XXXX IB0 Start push button I 0.0 7..7 I 1.3 I 1.0 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 B-13 .

I 0.0 Network 2: If the timer is running. The result is loaded into memory word MW1. setting bit 13 to 1 and resetting bit 12 to 0. The 16 bits of the thumbwheel inputs are combined with W#16#0FFF according to the (Word) And Word instruction. T1 RET Network 3: Mask input bits I 0.7 (that is.7 T1 SE MW2 B-14 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . WAND_W EN IW0 W#16#FFF IN1 IN2 ENO OUT MW1 MW1 W#16#2000 WOR_W EN IN1 IN2 ENO OUT MW2 Network 4: Start timer T 1 as an extended pulse timer if the start push button is pressed. loading as a preset value memory word MW2 (derived from the logic above). T1 Q 4.4 through I 0. then turn on the heater.Programming Examples Ladder Logic Program Network 1: If the timer is running. the Return instruction ends the processing here. These bits of the thumbwheel inputs are not used. reset them to 0). In order to set the time base of seconds. the preset value is combined with W#16#2000 according to the (Word) Or Word instruction.

ENO = EN. If EN and ENO are connected. Shift and rotate instructions. The EN/ENO mechanism is used for: • • • • • • • Math instructions. Block calls. Adder with EN and without ENO Connected 3. the following applies: ENO = EN AND NOT (box error) If no error occurs (box error = 0). Adder without EN and with ENO Connected 4. Transfer and conversion instructions. This mechanism is not used for: Comparisons. Counters. additional STL instructions are generated for the EN/ENO mechanism with dependency on the existing preceding and subsequent logic operations.C Working with Ladder Logic C. Adder with EN and with ENO Connected 2. Timers. The four possible cases are shown using the example of an adder: 1. Around the actual instructions in the box.1 EN/ENO Mechanism The enable (EN) and enable output (ENO) of FBD/LAD boxes is achieved by means of the BR bit. Adder without EN and without ENO Connected Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 C-1 .

0 JNB _001 L in1 L in2 +I T out AN OV SAVE CLR _001: A BR = Q 4. You cannot use the BR as a memory bit because it is constantly overwritten by the EN/ENO mechanism. Instead. In line 7 the program evaluates whether an error occurred during addition. the program does not jump. The fourth example shows that this is not automatically the case. At the end of the block program the following network: end: AN error SAVE Ensure that this network is processed in every case. the program jumps to line 10 and resumes with A BR. A NOT and a SET coil will be sufficient for this. Initialize this variable with 0. set this variable using the assistance of the EN/ENO mechanism.1 Adder with EN and with ENO Connected If the adder has an EN and an ENO connected. this is then stored in BR in line 8. meaning the addition is executed.0 // // // // // // // // // // EN connection Shift RLO into BR and jump if RLO = 0 Box parameter Box parameter Actual addition Box parameter Error recognition Save error in BR First check Shift BR into RLO Following line 1 the RLO contains the result of the preceding logic operation. In line 10 the BR is copied into the RLO again and 0 is thus assigned to the output. The BR bit is not changed by lines 10 and 11. the following STL instructions are triggered: 1 2 3 4 5 6 7 8 9 10 11 A I 0. • If the RLO = 0. Now the BR bit is copied back into the RLO in line 10 and thus the output shows whether the addition was successful or not. C. use a temporary variable in which you save any errors which occur.Working with Ladder Logic Note on Creating Your Own Blocks If you want to program blocks which you want to call in FBD or LAD. you must ensure that the BR bit is set when the block is exited. which means you must not use BEC within the block and skip this network. At each point in the block at which you think an unsuccessful instruction represents an error for the whole block.1. The JNB instruction copies the RLO into the BR bit and sets the first check bit. so it also shows whether the addition was successful. Line 9 sets the first check bit. The addition is not executed. • C-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . If the RLO = 1.

0 JNB _001 in1 L in2 // // // // // // EN connection Shift RLO into BR and jump if RLO = 0 Box parameter Box parameter Actual addition Box parameter Following line 1 the RLO contains the result of the preceding logic operation. The program does not evaluate whether an error occurred during addition. Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 C-3 . The RLO and BR are 0. this is then stored in BR in line 6. The BR bit is not changed by lines 8 and 9. the program does not jump. The RLO and BR are 1.Working with Ladder Logic C.1. meaning the addition is executed. The JNB instruction copies the RLO into the BR bit and sets the first check bit. In line 5 the program evaluates whether an error occurred during addition.0 T OV SAVE out in1 L in2 // // // // // // // // Box parameter Box parameter Actual addition Box parameter Error recognition Save error in BR First check Shift BR into RLO The addition is executed in every case. the following STL instructions are triggered: 1 2 3 4 5 6 7 8 9 L +I AN CLR A = Q BR 4. the program jumps to line 7 and the addition is not executed. If RLO was 1. so it also shows whether the addition was successful.2 Adder with EN and without ENO Connected If the adder has an EN but no ENO connected. Line 7 sets the first check bit.1. • • If the RLO = 0. Now the BR bit is copied back into the RLO in line 8 and thus the output shows whether the addition was successful or not.3 Adder without EN and with ENO Connected If the adder has no EN but an ENO connected. the following STL instructions are triggered: 1 2 3 4 5 6 7 A L +I _001: T NOP out 0 I 0. C.

outputs or peripheral I/Os are used as actual address of a function they are treated in a different way than the other addresses. the random value will be retained. with functions the value will be the value which happens to be in the L stack. Note the following points: • • • Initialize all OUTPUT parameters if possible. With functions a copy of the actual value lies in the local data stack.Working with Ladder Logic C. Prior to the call the INPUT values are copied into the instance DB or to the L stack. the current parameters are updated via the L stack.4 Adder without EN and without ENO Connected If the adder has no EN and no ENO connected. Try not to use any Set and Reset instructions. If the RLO has the value 0. The STL instructions required for this are in the calling block and remain hidden from the user. ensure that the parameters declared as OUTPUT are also written. Here. Otherwise the values output are random! With function blocks the value will be the value from the instance DB noted by the last call. inputs. After the call the OUTPUT values are copied back into the variables. C.2 Parameter Transfer The parameters of a block are transferred as a value. Caution When programming the called block. Within the called block you can only work on a copy. C-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261407-01 . Do not forget BEC and the effect of the MCR instructions. updates are carried out directly. Pointers are not copied. ensure that you do not skip any locations where OUTPUT parameters are written. These instructions are dependent on the RLO. the following STL instructions are triggered: 1 2 3 4 5 L T L in1 in2 +I out NOP 0 // // // // Box parameter Box parameter Actual addition Box parameter The addition is executed. If you jump within the block. Exception: If the corresponding formal parameter is an input parameter of the data type BOOL.1. not via L Stack. The RLO and the BR bit remain unchanged. Note If memory bits. With function blocks a copy of the actual parameter value in the instance data block is used in the called block.

..... 12-10 <0 ---| / |---........................................................................................................................................................ 12-10 = ==0 ---| |--...................1-2 ---| / |--.................................................................................................................................................................................................................................10-16...........................Index ( ---( ) ................................................................................ 8-15 Assign a Value.........C-4 Address Negative Edge Detection .........1-16 ---( P )--......................................................1-17 ---( R ).......................... 12-7 > >=0 ---| |--......................... 12-12 <=0 ---| / |--.........1-11 ---( SA ) .......................................14-4 (Word) AND Word ......................13-17 ---( SZ )............................................ 8-3 ADD_DI.................................................................6-2..................................... 12-8 <>0 ---| / |--......................................................10-20 ---(SAVE).........................................6-4 ---( N )--... 12-7 ==0 ---| / |--............ 8-16 Add Double Integer............................................ 8-17 | ---| |--......................................14-7 (Word) Exclusive OR Word ...............................13-23 ---( SC ) .................................................................................................. 7-3 ADD_R...... 12-9 A ABS .......................... 9-1 ATAN .10-2 ---(JMP)---...........4-10 ---( JMPN )............................................................................................13-23 ---( SI )....................... 12-1 --|NOT|-.............................................1-9 ---( S )..........4-12 ---( ZV )...................................................................................................................................................................14-5 (Word) OR Word .............................................12-1 ---| |--.........................................1-6 ---( # )---..............................................................1-8 ---( CD ) .................................................................................................................................... 12-9 >0 ---| / |---.............................. 6-3 ---(MCR<) ...................4-12 ---( CU ) ...................................................5-1 ---(RET) .....................................14-2 (Word) Exclusive OR Double Word ......4-10 ---(Call) ...........................................................................................................................................................................................1-18 (Word) AND Double Word.......... 12-11 >=0 ---| / |--.......................................................................................................4-9 ---( SD ) ................................. 13-19 ---( SF )........................................ 7-7 Add Integer ...........................................13-17.....................14-3 < <=0 ---| |--............................................................ 12-8 <0 ---| |---.................................................................13-15 ---( SP ) ............. 12-11 >0 ---| |---....................10-14 ---(MCR>) ........................... 8-7 ACOS..........................................................................................10-19 ---(OPN) ................................. 1-19 Address Positive Edge Detection...................1-3.........................................13-19 ---( SE ) ......................C-3 Adder without EN and with ENO Connected ..............................................1-5 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261254-01 Index-1 ...................................................... 1-20 ASIN ........................................................................14-6 (Word) OR Double Word ......10-18 ---(MCRD)................................................ 10-17 ---(MCRA).................................... 8-3 Adder with EN and with ENO Connected ........................................................ 12-12 <>0 ---| |--........................13-21 ---( SV ) ........C-2 Adder with EN and without ENO Connected .................................4-9 ---( ZR ) ................................................................13-15 ---( SS ) ...... 7-3 Add Real.....................C-3 Adder without EN and without ENO Connected... 7-7 ADD_I .......................................................

........................ 8-17 Establish the Cosine Value ..... 12-6 C Call Block from a Library........................................ 8-10 Establish the Natural Logarithm ............... 10-8 Call System FC from Box.. B-10 Integer Math Instructions ............................... 1-4 BR ---| |---..................................................................8-10 Extended Pulse S5 Timer................................................................. 4-7 Down Counter Coil........... 1-22 Immediate Write .... A-1 LAD Instructions Sorted According to German Mnemonics (SIMATIC) .................8-14 Evaluating the Bits of the Status Word with Integer Math Instructions......................................................................................... 3-5 BCD_I ....12-2 Exception Bit Overflow Stored..........................8-11 Location of a Timer in Memory and Components of a Timer ......................................................................... 4-12 J Jump Instructions ....................................6-5 LABEL ............ 8-15 Establish the Arc Tangent Value..............................................................8-2 Example Bit Logic Instructions ........12-5 EXP .........6-4 L Label ........... B-13 Exception Bit Binary Result ......................3-9 INV_I ..................................13-7 Extended Pulse Timer Coil .. 10-12 Call System FB from Box..................... 3-5 BCD to Integer ............................................................................................... A-5 LN..........................C-1............................................................3-16 I I_BCD... 8-8 Index-2 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261254-01 ......................................................................... 3-15 Ceiling.......................... 3-15 CMP ? D ...... 8-11 Establish the Sine Value ........................................................................................................................................................3-16 FLOOR ........... 7-10 Divide Integer..........................................................................................................................................................6-5 LAD Instructions Sorted According to English Mnemonics (International) ... 8-12 Establish the Square...................1-5 D DI_BCD...................................................... 8-13 Establish the Exponential Value ...................... B-2 Counter and Comparison Instructions ..3-4 Immediate Read ............................... 10-4 CALL_FC ....8-2 Floor ........................3-3 I_DINT .......... 10-6 Call FC SFC from Coil (without Parameters)............................. 3-2 BCD_DI........................... 10-12 Call FB from Box........... B-12 Timer Instructions............ C-2 Establish the Absolute Value of a Floating-Point Number .............. 6-3 COS ........................13-17 F Floating-Point Math Instructions ............................................................ 3-7 DIV_DI ........................12-6 Exception Bit Overflow ............................. 12-6 BR ---| / |---................................................... 8-6 Divide Double Integer ................................................................................ 2-4 Conditional Jump .................................................... 3-6 Double Integer to Floating-Point ............... 1-24 Important Notes on Using MCR Functions ............ 8-7 Establish the Arc Cosine Value. 7-6 DIV_R ............... 3-2 Bit Exclusive OR .......................................3-3 Integer to Double Integer.......................3-8 Invert Power Flow......................... 10-8 CALL_SFC...............................................6-5 Jump-If-Not..............................1-23........................................................8-9 Establish the Tangent Value................... 8-16 Establish the Arc Sine Value.........................................................................................................12-3 Exception Bit Unordered . 10-4 Call FC from Box...................................... 10-10 CEIL................ 2-3 CMP ? I...............................................................................10-13 Integer to BCD............................................................................................. 3-7 Down Counter ...... 7-6 Divide Real ................. 10-10 CALL_FB .................................................. 10-6 CALL_SFB...............Index B BCD to Double Integer........ 2-2 CMP ? R .................................................................1-21...................................... 10-2 Call Multiple Instance.................................................3-4 INV_DI................................................................................................................... 8-6 Double Integer to BCD............... 8-13 Establish the Square Root.......................................................................................................................................................................................................................... B-6 Word Logic Instructions ....................................................................13-2 E EN/ENO Mechanism....................................................................................... 7-10 DIV_I..................... 3-6 DI_REAL.................................................7-2 Evaluation of the Bits in the Status Word ......................

.................13-19 Ones Complement Double Integer .... 1-13 O Off-Delay S5 Timer.......................1-16 Normally Closed Contact (Address) .... 13-9 S_IMPULS ............................................................................................................ 12-11 Result Bit Greater Than 0 ................ 1-12 Result Bit Equal 0 ................................................. 14-1 Overview over Program Control Instructions 10-1 P Parameter Transfer...............8-5 Multiply Double Integer.......... 13-11 S_OFFDT ..........................................3-12 Negated Exception Bit Binary Result........................ 13-5 S_SEVERZ .3-12 Negate Floating-Point Number..............7-5 Multiply Real............................................................................. 12-12 Result Bit Less Than 0....................................... 1-14 Shift Left Double Word............ 12-8 Retentive On-Delay S5 Timer ...................... 11-11 Rotate Right Double Word ..................................................................... 11-12 ROR_DW.......... 1-11 Set Counter Value ................................................4-1 Overview of Floating-Point Math Instructions .......... 13-11 Retentive On-Delay Timer Coil ............................7-9 MUL_I...... 1-17 Practical Applications........................................... 4-7 S_CU ......... 11-13........12-8 Negative RLO Edge Detection ............................................................13-13 Off-Delay Timer Coil.................. 4-3 S_EVERZ ................................................1-2 R Reset Coil ................1-8 Mnemonics English (International) ...............................12-11 Negated Result Bit Greater Than 0 .............. 12-7 Result Bit Greater Equal 0 ........................................................8-1 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261254-01 S S_AVERZ ...................................................................................................................................... B-1 Pulse S5 Timer .............................. A-5 MOD_DI ........................................7-9 Multiply Integer.........................................................................................................................................10-16 Master Control Relay On.10-19 Master Control Relay Off.................................. 13-13 S_PEXT ............. 13-21 Return....12-3 Negated Exception Bit Unordered ...................... 13-9 S_ODTS ............ 11-11 Overview of Shift Instructions ....................12-12 Negated Result Bit Less Than 0............12-2 OV ---| / |--.....................3-8 Open Data Block DB or DI ...........................................................3-10 NEG_R..................... 3-13 RS..................................................................................1-1 Overview of Comparison Instructions........C-4 POS ......13-23 On-Delay S5 Timer........................................................................... 13-5 S_ODT..........................12-2 Negated Exception Bit Overflow Stored ... B-1 Overview of Rotate Instructions ....................................................... 13-7 S_PULSE............................................................................... 11-7 Index-3 ..............................................................1-19 NEG_DI......................10-14 Midline Output ...1-6 OV ---| |--.........................................12-10 Negated Result Bit Not Equal 0......................................5-1 OS ---| |--....................................................................12-9 Negated Result Bit Less Equal 0................7-11 MOVE................................................Index M Master Control Relay Activate........ 10-20 Return Fraction Double Integer...................................................... 4-5 S_CUD........................................................................................7-5 MUL_R .................................................................................................. 7-11 ROL_DW .........8-5 Overview of Integer Math Instructions ......... 4-9 Set-Reset Flip Flop ..12-2 Overview of Bit Logic Instructions ........................................................................................... 13-1 Overview of Word Logic Instructions ............................................................12-7 Negated Result Bit Greater Equal 0 .................. 12-10 Result Bit Not Equal 0.........................12-5 Negated Result Bit Equal 0 ............................... 13-7 Save RLO into BR Memory....................................................3-11 NEG_I .......... 13-13 S_CD .............12-3 Output Coil ........... 13-11 S_VIMP..................................................... 1-18 Set Coil .......................................... 6-1 Overview of Programming Examples................................................................................................................................................................................9-2 MUL_DI ........................... A-1 German (SIMATIC) ............................12-6 Negated Exception Bit Overflow............................................ 11-14 Rotate Left Double Word ............ 11-13 ROUND.................... 13-5 Pulse Timer Coil ....................................2-1 Overview of Conversion Instructions ....12-3 OS ---| / |--. 13-15 N NEG ................................................. 11-1 Overview of Timer Instructions ............................... 1-9 Reset-Set Flip Flop ................................................................................ 3-13 Round to Double Integer..................................................................10-18 Master Control Relay Deactivate.......................................................................3-1 Overview of Counter Instructions ...... 1-20 Positive RLO Edge Detection ....................3-9 Ones Complement Integer ............. 7-1 Overview of Logic Control Instructions ............................1-3 Normally Open Contact (Address)................13-9 On-Delay Timer Coil................ 12-9 Result Bit Less Equal 0..........................................

.................................................................................................................................................................... 11-6 SHR_DI........................................14-6 X XOR..... 7-4 Subtract Real ............................................14-7 WXOR_W.......1-4 T TAN.............................................................................12-5 UO ---| / |---... 11-4 SHR_DW ................................................................ 11-2 Shift Right Word......................Index Shift Left Word ........................................................................................................................................................................................................................ 11-7 SIN. 11-9......... 11-2................................. 3-14 Truncate Double Integer Part......................................4-3 Index-4 Ladder Logic (LAD) for S7-300 and S7-400 Programming A5E00261254-01 ................12-5 Up Counter ................6-2 UO ---| |---....................... 8-4 Subtract Double Integer ....................................4-5 Up Counter Coil..................................................................................... 7-8 Subtract Integer ........................................................ 11-3 SHR_W ..........................................................................................................14-2 WOR_DW . 11-9 Shift Right Integer ......................4-3 W WAND_DW ........4-10 Up-Down Counter........ 11-5 Shift Right Double Integer................... 1-14 SUB_DI......... 8-14 TRUNC ............................................................14-5 WOR_W ........................................................... 11-8 SHL_W ....................... 11-10 SHR_I .................................... 3-14 Twos Complement Double Integer.......... 3-10 Z Z_RUECK............ 11-5................. 8-4 U Unconditional Jump.............................. 8-9 SR... 11-6 SHL_DW ......................................................14-3 WXOR_DW ......................... 8-8 SQRT.................................................. 11-3 Shift Right Double Word ...........................................................................................4-5 ZÄHLER ........................................................ 7-4 SUB_R.................................................................................................................................................................................................................. 3-11 Twos Complement Integer....................................... 7-8 SUB_I .......14-4 WAND_W ..................4-7 Z_VORW ......................... 8-12 SQR .........................................................................................................