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4 Clock Gating Power optimization at high levels of abstraction has a significant impact on reduction of power in the final gate-level design. Clock gating is an important high-level technique for reducing the power consumption of a design.

2.4.1 Introduction to Clock Gating Clock gating applies to synchronous load-enable registers, which are groups of flip-flops that share the same clock and synchronous control signals and that are inferred from the same HDL variable. Synchronous control signals include synchronous load-enable, synchronous set, synchronous reset, and synchronous toggle.

In my Design implemented Integrated cell with latch-based clock gating. Which is effective in reducing the switching power and thereby reducing the Dynamic power of the Design.

2.4.2 LATCH BASED INTEGRATED CLOCK GATING The clock input to the register bank, ENCLK, is gated on or off by the AND gate. ENL is the enabling signal that controls the gating; it derives from the EN signal on the multiplexer shown in Figure 7-1 on page 7-4. The register bank is triggered by the rising edge of the ENCLK signal. The latch prevents glitches on the EN signal from propagating to the registers clock pin. When the CLK input of the 2-input AND gate is at logic state 1, any glitching of the EN signal could, without the latch, propagate and corrupt the register clock signal. The latch eliminates this possibility because it blocks signal changes when the clock is at logic state 1.

In latch-based clock gating, the AND gate blocks unnecessary clock pulses by maintaining the clock signals value after the trailing edge. For example, for flip-flops inferred by HDL constructs of rising-edge clocks, the clock gate forces the gated clock to 0 after the falling edge of the clock. By controlling the clock signal for the register bank, you can eliminate the need for reloading the same value in the register through multiple clock cycles. Clock gating inserts clock-gating circuitry into the register banks clock network, creating the control to eliminate unnecessary register activity

Figure Latch based clock gatng 2.4.3 Clock-Gating Conditions The register must satisfy all three of the following conditions before Power Compiler gates the clock signal of the registers: Enable condition This condition checks if the register banks synchronous load-enable signal is constant logic 1, reducible to logic 1, or logic 0. In these cases, the condition is false and the circuit is not gated. If the synchronous load-enable signal is not constant logic 1 or 0, the

condition is true and clock gating goes on to check the setup condition. The enable condition is the first condition clock gating checks. Setup condition This setup condition applies to latch-free clock gating only. It checks that the enable signal comes from a register that is clocked by the same clock as the register being gated. Clock gating checks this condition only if the register satisfies the enable condition. Width condition The width condition is the minimum number ofbits for gating registers or groups of registers with equivalent enable signals. The default value is 3. You can set the width condition by using the -minimum_bitwidthoption of the set_clock_gating_stylecommand. Clock gating checks this condition only if the register satisfies the enable condition and the setup condition. Enable Condition The enable condition of a register or clock gate is a combinational function of nets in the design. The enable condition of a register represents the states for which a clock signal must be passed to the register. The enable condition of a clock gate corresponds to the states for which a clock is passed to the registers in the fanout of the clock gate

2.4.4 Integrated Clock-Gating Cell Rising-Edge Latch-Based Integrated Cells The following integrated cells are latch-based

Figure :Rising Edge Latch Based Integrated Cell Library Description It is a description of an integrated clock-gating cell that demonstrates the following features: The clock_gating_integrated_cell attribute Appropriate clock-gating attributes on three pins Setup and hold arc on enable pin (EN) with respect to the clock pin (CP) Combinational arcs from enable pin (EN) and clock pin (CP) to the output pin (Z) State table and state function on the output pin (Z) Internal power table