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Expt No 1

Aim- The purpose of this experiment is to introduce you to the basics of circuit wiring, troubleshooting, positive/negative logic, threshold voltages, clock, delay concepts, and gate behavior. In this lab, you will test the behavior of several of the basic logic gates and you will connect several logic gates to create simple circuits and verify their truth table. Requirements: Power Supply (Figure L1.1a): All active electronic devices such as the integrated circuits used in digital electronics require a stable source of DC voltage to function properly. The power supply provides the proper level of dc voltage. It is very important that the correct voltage be set before connecting it to the ICs on your board or permanent damage can result. The power supply at your bench may have more than one output and normally will have a built in meter to help you set the voltage. Usually for all circuits power supply should be set to +5.0 V. Digital Multimeter (Figure L1.1b): the DMM is a multipurpose measuring instrument that combines in one instrument the characteristics of a dc and ac voltmeter, a ac and dc ammeter and ohmmeter. The DMM indicates the measured quantity as a digital number, avoiding the necessity to interpret the scales as was necessary on older instruments. You need to select the desired function by the switch provided. For current measurements a separate set of lead connections are made to the meter. The ohmmeter function of a DMM is used only in circuits that are not powered. Function Generator (Figure L1.1c): A function generator is used to produce signals required for testing various kinds of circuits. For digital circuits, a periodic rectangular pulse is the basic signal used for testing logic circuits. It is important that proper voltage be set up before connecting the function generator to the circuit or else damage may occur. Function generators normally have controls for adjusting the peak amplitude of a signal and may also have a means of adjusting the 0 volt level. Oscilloscope (Figure L1.1d): The oscilloscope is the most important test instrument for testing circuits and you should become completely familiar with its operations. Its a versatile test instrument letting you see a graph of the voltage as a function of time in a circuit and compare waves. Because an oscilloscope allows you to measure various parameters, it is considered to be an instrument capable of parametric measurements important in both digital and analog work. Nearly all complex digital circuits have specific timing requirement that can be readily measured with a two channel oscilloscope. There are two basic types of oscilloscope; analog and digital. Both types of scopes have four main control groups: display controls, vertical and horizontal control and trigger controls. Circuit board (protoboards): Circuit boards are convenient way to construct circuit for testing and experimenting. Most of them look like the one shown in the figure L1.2 . You will notice the top and bottom horizontal rows are connected as a continuous row. Vertical groups of five holes are connected together; the vertical group above the center strip is not connected to vertical group below the center strip. The holes are 0.1 inch apart, which is the same spacing as the pins on an integrated circuit DIP (Dual In-line Pins). Integrated circuits (ICs) are inserted to straddle the center; in this manner, wires can be connected to the pins of the IC by connecting them to the same vertical group as the desired pin.

Fig. L 1.1 Instruments

Fig. L 1.2 Breadboard

APPARATUS REQUIRED:

Sr No. 1. 2. 3. 4. 5. 6. 7. 8. 9. THEORY:

COMPONENT SPECIFICATION QTY AND GATE IC 7408 1 OR GATE IC 7432 1 NOT GATE IC 7404 1 NAND GATE 2 I/P IC 7400 1 NOR GATE IC 7402 1 X-OR GATE IC 7486 1 NAND GATE 3 I/P IC 7410 1 IC TRAINER KIT 1 PATCH CORD 14

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The output is high when both the inputs are high. The output is low level when any one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output is high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The output is low when the input is high.

NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low and any one of the input is low .The output is low level when both inputs are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The output is low when one or both inputs are high.

X-OR GATE:
The output is high when any one of the inputs is high. The output is low when both the inputs are low and both the inputs are high.

PROCEDURE:
(i) (ii) (iii) AND GATE: SYMBOL: PIN DIAGRAM: Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.

OR GATE:

NOT GATE: SYMBOL: PIN DIAGRAM:

X-OR GATE : SYMBOL : PIN DIAGRAM :

2-INPUT NAND GATE: SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

NOR GATE:

3 Input AND-

7420 Dual Four Input NAND Gate

7421 Dual Four Input AND Gate

7427 Triple Input NOR Gate

Result: The different ICs were studied and their truth table were verified.

EXPT NO: 2 DESIGN OF ADDER AND SUBTRACTOR AIM: To design and construct half adder, full adder, half subtractor and full subtractor circuits and verify the truth table using logic gates. THEORY: HALF ADDER: A half adder has two inputs for the two bits to be added and two outputs one from the sum S and other from the carry c into the higher adder position. Above circuit is called as a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate.

FULL ADDER: A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate. HALF SUBTRACTOR: The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input and two outputs. The outputs are difference and borrow. The difference can be applied using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter. FULL SUBTRACTOR: The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the logic circuit should have three inputs and two outputs. The two half subtractor put together gives a full subtractor .The first half subtractor will be C and A B. The output

will be difference output of full subtractor. The expression AB assembles the borrow output of the half subtractor and the second term is the inverted difference output of first X-OR.

LOGIC DIAGRAM: HALF ADDER

TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 CARRY 0 0 0 1 SUM 0 1 1 0

K-Map for SUM:

K-Map for CARRY:

SUM = AB + AB

CARRY = AB

LOGIC DIAGRAM: FULL ADDER FULL ADDER USING TWO HALF ADDER

TRUTH TABLE: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 CARRY 0 0 0 1 0 1 1 1 SUM 0 1 1 0 1 0 0 1

K-Map for SUM:

SUM = ABC + ABC + ABC + ABC K-Map for CARRY:

CARRY = AB + BC + AC LOGIC DIAGRAM: HALF SUBTRACTOR

TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 BORROW 0 1 0 0 DIFFERENCE 0 1 1 0

K-Map for DIFFERENCE:

DIFFERENCE = AB + AB K-Map for BORROW:

BORROW = AB LOGIC DIAGRAM: FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE: A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

BORROW 0 1 1 1 0 0 0 1

DIFFERENCE 0 1 1 0 1 0 0 1

K-Map for Difference:

Difference = ABC + ABC + ABC + ABC K-Map for Borrow:

Borrow = AB + BC + AC APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. 3. 4. COMPONENT AND GATE X-OR GATE NOT GATE OR GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7408 IC 7486 IC 7404 IC 7432 QTY. 1 1 1 1 1 23

PROCEDURE: (i) Connections are given as per circuit diagram. (ii) (iii) Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.

RESULT:

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER

AIM: To design and implement multiplexer and demultiplexer using logic gates and study of IC 74151, 74153 and IC 74155. THEORY: MULTIPLEXER: Multiplexer means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input line and n selection lines whose bit combination determine which input is selected. DEMULTIPLEXER: The function of Demultiplexer is in contrast to multiplexer function. It takes information from one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines enable only one gate at a time and the data on the data input line will pass through the selected gate to the associated data output line. BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE: S1 S0 INPUTS Y

0 0 1 1

0 1 0 1

D0 D0 S1 S0 D1 D1 S1 S0 D2 D2 S1 S0 D3 D3 S1 S0

Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0 CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE: S1 0 0 S0 0 1 Y = OUTPUT D0 D1

1 1

0 1

D2 D3

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE: S1 0 0 1 1 S0 0 1 0 1 INPUT X D0 = X S1 S0 X D1 = X S1 S0 X D2 = X S1 S0 X D3 = X S1 S0

Y = X S1 S0 + X S1 S0 + X S1 S0 + X S1 S0 LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE: INPUT S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 I/P 0 1 0 1 0 1 0 1 D0 0 1 0 0 0 0 0 0 D1 0 0 0 1 0 0 0 0 OUTPUT D2 0 0 0 0 0 1 0 0 D3 0 0 0 0 0 0 0 1

PIN DIAGRAM FOR IC 74153:

PIN DIAGRAM FOR IC 74151:

PIN DIAGRAM FOR IC 74155:

APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. 5. 6. 7. COMPONENT 3 I/P AND GATE OR GATE NOT GATE 4:1 MUX 8:1 MUX 8:1 DEMUX PATCH CORDS SPECIFICATION IC 7411 IC 7432 IC 7404 IC 74153 IC 74151 IC 74155 QTY. 2 1 1 1 1 1 32

PROCEDURE: (i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.

RESULT:

FLIPFLOPS

AIM: To study the working of R-S, J-K, D and T flip-flops. Requirements: Breadboard, Power supply, logic gates ICs 7400, 7402, 7476, LED. Theory: Flip-flops are the basic building blocks of sequential ckt. The clocked FFs change their o/p state depending upon i/p's at certain interval of time synchronized with the clock pulse applied to it. Different types of FFs are S-R, J-K, D & T . Their operations are described by the respective truth tables. MSI chip 7476 incorporates two negative edge triggered Master Slave JK flipflops. The J-K flipflop can be converted to D & T flipflop. Circuit Diagram: S-R Flipflop using NAND gate

J-K Flipflop using IC 7476

T Flipflop using IC 7476

D Flipflop using IC 7476

PROCEDURE: (i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.

Conclusion Result

SHIFT REGISTERS
AIM: To realize and study of Shift Register. 1) SISO (Serial in Serial out) 2) SIPO (Serial in Parallel out) 3) PIPO (Parallel in Parallel out) 4) PISO (Parallel in Serial out) COMPONENTS REQUIRED: IC 7474 D Flipflop, Patch Cords. TheoryA register is capable of shifting its binary information in one or both directions is known as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive common clock pulses which causes the shift in the output of the flip flop. The simplest possible shift register is one that uses only flip flop. The output of a given flip flop is connected to the input of next flip flop of the register. Each clock pulse shifts the content of register one bit position to right.

Pin

Description

Pin Diagram & Circuit Diagram


1

number
Clear 1 Input D1 Input Clock 1 input Preset 1 input Q1 output Complement Q1 output Ground Complement Q2 output Q2 output Preset 2 input Clock 2 input D2 input Clear 2 input
Power supply 2 3 4 5 6 7 8 9 10 11 12 13

7474 - Dual D Flip-Flop with Preset and Clear

Fig. 7474 Dual D Flipflop with Preset & Clear

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1) SERIAL IN SERIAL OUT (SISO) (Right Shift)

LOGIC DIAGRAM: SERIAL IN SERIAL OUT:

TRUTH TABLE:
CLK 1 2 Serial in 1 0 Serial out 0 0

3 4 5 6 7

0 1 X X X

0 1 0 0 1

LOGIC DIAGRAM: SERIAL IN PARALLEL OUT:

TRUTH TABLE:
OUTPUT CLK 1 2 3 4 DATA 1 0 0 1 QA 1 0 0 1 QB 0 1 0 0 QC 0 0 1 0 QD 0 0 1 1

LOGIC DIAGRAM: PARALLEL IN SERIAL OUT:

TRUTH TABLE: CLK 0 1 2 3 Q3 1 0 0 0 Q2 0 0 0 0 Q1 0 0 0 0 Q0 1 0 0 0 O/P 1 0 0 1

LOGIC DIAGRAM: PARALLEL IN PARALLEL OUT:

TRUTH TABLE: DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD 1 2 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0

PROCEDURE: Check all the components for their working. Insert the appropriate IC into the IC base. Make connections as shown in the circuit diagram. Verify the Truth Table and observe the outputs.

AGNEL INSTITUTE OF TECHNOLOGY AND DESIGN ASSAGAO, BARDEZ, GOA- 403507

ECE TIME-TABLE FILE 2013-2014


HOD: Prof. Laxmikant Bordekar Time-table incharge: Prof. Shrinivas Joshi