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HIGH SPEED AND LOW POWER DESIGN OF CONTENT‐ ADDRESSABLE MEMORY 

 

A thesis submitted to the  DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING  OF  BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY    in partial fulfillment of  the requirements for the  degree of  Bachelor of Science in Electrical and Electronic Engineering 
 

By  

MD. NAIMUL HASAN (0306017)  MD. TAUHIDUR RAHMAN (0306035)  MD. MEHEDI HASAN (0306071) 
 

Supervisor 

DR. A.B.M. HARUN‐UR RASHID 
Professor, Department of EEE,   BUET, Dhaka‐1000     

BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY 
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Declaration 
  We  hereby  declare  that  the  work  presented  in  this  thesis  entitled  “High  Speed  and  Low  Power  Design  of  Content‐Addressable  Memory”  is  the  outcome  of  the  investigation  carried  out  by  us  and  neither  this  thesis  nor  any  part  thereof  has  been  submitted  or  is  being  currently  submitted  anywhere  else  for  the  award  of  any  degree or diploma.       
              ……………………………….. 

…………………………………….   

………………………………… 

Md. Naimul Hasan  
(0306017)                 

Md. Tauhidur Rahman 
  (0306035)     

Md. Mehedi Hasan 
  (0306071) 

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Our parents.
           
iii   

  We would like to express our profound gratitude and appreciation to our  Thesis  supervisor.  Ataur  Rahman  Patwary.   We  would  like  to  thank  the  alumni  of  BUET  (also  members  of  Yahoo!  Group BUETian) for their help by providing a lot of necessary works. we would like to convey our gratitude to Almighty Allah without  whose wish nothing is possible. BUET for letting us to use the VLSI server  computer to simulate large HSpice file.  Professor  Dr.  Harun‐Ur  Rashid  for  his  benign  attitude  towards  us  and  whose  supervision  gave  us  the  opportunity  to  get  involved  in  this  state‐of‐the‐art  and  greatly  emerging  research  of  low‐power  and  high‐speed  design  of  circuits  specially  Content‐Addressable  Memory  (CAM).  B.   We  also  would  like  to  acknowledge  the  help  of  the  Department  of  Electrical and Electronic Engineering.  encouragement  and  constant  guidance  accelerated  the completion of this thesis.  USA  for  his  suggestions  and  different  kinds  of  help  to  complete  the  work.   We  also  would  like  to  express  our  special  thanks  to  Mr.  Oregon  State  University.  A.  M.  His  generous  help.  ACKNOWLEDGEMENTS    At first.               iv    .  School  of  Electrical  and  Computer  Engineering.

......................v List of Figures ………………………………………………………………………………viii List of Tables…………………………………………………………………………………........... 4 CHAPTER 2: DIFFERENT TYPES OF LOGIC ................1 INTRODUCTION .......1 Structure of NOR Cell ... 4 1................................................ 2 CORE CELLS AND MATCHLINE STRUCTURE .2................................................3 COMPLEMENTARY TRANSISTOR PULL-UP (CMOS) ..........4 THESIS ORGANIZATION ......... 9 2.................................................... 7 2.....................1 Components of Total Power Dissipation in CMOS Circuits ............4 Pseudo-nMOS logic .................... 7 2............................. 23 v    ............3 nMOS enhancement mode pull up .............................. 19 3.......................................... 19 3.................................... 7 2........2.......................................................... 16 CHAPTER 3: CONTENT ADDRESSABLE MEMORY (CAM) REVIEW .............................................4 DYNAMIC CIRCUITS.............................................................................................................. 8 2..................................................3 OBJECTIVES ................................. 7 2............................................................................................................................................................................................................................................................................2......................................................................... 2 1..............................................................................1 Load Resistance RL .......1 INTRODUCTION .. 11 2..2 MOTIVATIONS .............................. 22 3...............................3........ 10 2..........................2 RATIOED LOGIC........................................................................................................................ 2 1.............................................................2.........1 INTRODUCTION ............................................................................................................................................................................ 8 2........................xi Abstract………………………………………………………………………………………xii CHAPTER 1: INTRODUCTION ..... 9 2......................................... 3 1... 22 3........2 nMOS depletion mode transistor pull up ....CONTENTS  Page Declaration……………………………………………………………………………………ii Dedication……………………………………………………………………………………...............................................................2 Structure of NAND Cell ..............................................2.................2.................................iii Acknowledgement……………………………………………………………………………iv Contents………………………………………………………………………………………....5 DOMINO LOGIC .......................................................................

............................. 52 6................ 52 6...2 The sense amplifier ............................4 CORNER SIMULATION OF THE SCHEME ......................................4 LOW-SWING SCHEMES ................................................................1............................ 32 3..............................................................1 Conventional (Precharge-High) Matchline Sensing....... 41 4........3...........................5 CONCLUSION ........................................................ 46 5..........................................................1......... 44 5.............................................6 SELECTIVE-PRECHARGE SCHEME ................3 SIMULATION RESULTS AND ANALYSIS ........................ 27 3............................. 53 6............3 Charge Sharing.....3 MATCHLINE SENSING SCHEMES ...........................................................................................................................................................3............ 35 CHAPTER 4: PROPOSED CHARGING CONTROL SCHEME & SENSE AMPLIFIER ............ 37 4................ 34 3.............................................................3.................... 37 4.3 Ternary Cells ............................................................................................................................... 31 3..................... 27 3...................................................................................... 52 6................................................................................... 29 3................ 50 CHAPTER 6: PROPOSED CAM WITH IMPROVED NOISE MARGIN ........................................ 55 vi    ...........................................................3 SIMULATION RESULT............................................................2 Matchline power ......9 CONCLUSION ........................... 23 3..........1 INTRODUCTION .................................................................2 OPERATION OF THE SCHEME ......................................................................................................................................................................................... 25 3.................................... 44 5......1 INTRODUCTION .........................................................................2...2 PROPOSED ML CHARGING TECHNIQUE ....5 CURRENT-RACE SCHEME ...........1.......................................................................... 28 3.....4 CONCLUSION ..............2.....................................7 PIPELINING SCHEME .....................................................................................8 CURRENT-SAVING SCHEME ............................................................ 39 4.........1 Basic Operation ........................2......................................................................................2 PROPOSED CHARGE CONTROLLING SCHEME .................. 30 3.1......................................4 Power Consumption .............1 INTRODUCTION .....................................................................1 Charging controller.........3........ 42 CHAPTER 5: PROPOSED SIMPLIFIED DESIGN OF CHARGING CONTROLLER ............................................................. 25 3............. 37 4........................... 26 3.........................................................3 SIMULATION RESULTS AND ANALYSIS .......................................................... 48 5.... 54 6................................3..CONTENTS (Continued) Page 3.............................................................................................................

61 Bibliography .........3.. 1 CONCLUSION ........................... 128 B................. Input File ..................... 122 A...............................................................................................................................................................................................................................................................................................................................3............... 57 CHAPTER 7: Conclusion .......................................... 124 APPENDIX B............................................ 135 vii    ................................................................2 HSPICE CODE FOR SIMPLIFIED DESIGN OF CHARGING CONTROLLER .............................................................................2 INSTALLATION AND USAGE OF HSPICE 2007 .............................................................4 References...........................................1..........4 CONCLUSION ......................3........................................................... 59 7............................................... Element Description .........1 INTRODUCTION ................................................................................3.................................................................................................. 134 B..3 BASIC RULES OR QUICK MANUAL [2] .................2 FUTURE WORK ........................................................................... 59 7.............................................................................................................................................................3 HSPICE CODE FOR IMPROVED NOISE SCHEME [CHAPTER 6] ....... 128 B.. 131 B...................... 69 RESEARCH PAPERS FROM THIS THESIS .............. 71 A.... 131 B.....CONTENTS (Continued) Page 6............3....... 59 Reference ......... 70 APPENDIX A .................................... 71 A...... Analysis .....................................................................................................2..............................................................................................................................................................................................1 HSPICE CODE FOR CHARGING CONTROL SCHEME................................. 132 B................... 128 B.......................................................................

......................  9  Fig.........  12  Fig............................................................LIST OF FIGURES PAGE Fig................................. 6: CMOS inverter current versus Vin .......... 3: CAM core cells for (a) 10-T NOR-type CAM and (b) 9-T NAND-type CAM...................... 21  Fig..................................................................... ..................................................................................  8  Fig....................... ...................... 3........................................ match lines and encoder ........................................... 15: Weak keeper implementation ... 1: Resistor Pull-up ...........................  17  Fig.......... 2.................. ..... ...................  14  Fig... 3: nMOS enhancement mode pull up ................................................... 3..... 7: Two possible configurations for the NOR cell: (a) the stored bit is connected to the bottom transistors of the pulldown pair.................................................. [34]  ..................................... 2........................  13  Fig.................................. and (b) the stored bit is connected to the top transistors of the pulldown pair..... 2.................  7  Fig................................ The cells are shown using SRAM-based data-storage cells. 13  Fig..... 14: Standard Domino Logic circuit .............................. 2..................... 2................................... 24  Fig..............  9  Fig...... 7: Precharge and evaluation of dynamic gates....................................... 10: Generalized footed gates................. 2: Profile of CAM capacity (log scale) versus year of publication [33]–[40] ................................. 4: Structure of Ternary core cells for (a) NOR-type (b) NAND-type CAM [41]....... 2................ 2..............  11  Fig...........  20  Fig..........................................  16  Fig................. 3................................................................................ 8: Footed dynamic inverter ................................. 6: Matchline power for NAND and NOR architecture [33]  ...... 2..... 3............................ .. 5: Complementary transistor pull-up (CMOS) .......... 12: Monotonicity problem ................ 5: (a) the schematic with precharge circuitry for matchline sensing using the precharge-high scheme........ 2........ 1: Simple schematic model of a 4x3 CAM array showing the core memory cells................................. 27  Fig... ........... [42]........ 2..............  8  Fig.. 2.................. 26  Fig.......... and (b) the corresponding timing diagram showing relative signal transitions............ 4: Pseudo-nMOS Logic ............................ differential search lines...................... 2............................................................. 3... 3.. 2: nMOS depletion mode transistor pull up ......................... 2.. 13: Incorrect connection of dynamic gates................................... 28  viii    ............  22  Fig..  15  Fig.................  12  Fig......... 2.......................................................................................................................... 11: Logical effort of footed and unfooted dynamic gates ........................... 2.............  10  Fig.. 3.......................... 9: Unfooted dynamic gates.............. ............................

............................ ..................  48  Fig................ 1: Structure of the CAM of the proposed scheme: (a) basic architecture and (b) NOR-type TCAM cell used in the scheme........ 31  Fig......................................... MLC and MLP..... 3.......................................................................................... 6: Corner Simulation results for SLH (when threshold voltage= +10%... 5...  53  Fig..................................... and (b) a miss case where the third stage results in a miss and turns off the subsequent stages.......... ML2 (two-bit miss)..... 2: Structure of the CAM array with the proposed scheme: (a) the basic architecture and (b) internal circuit of the NOR-type TCAM cell used in this scheme............ Here the usual SRAM access transistor and associated bitlines are omitted for simplicity...........................VDD=+5%........... 5........................ 12: Simulated wave forms in the pipelined match-line architecture for (a) the full-match case consisting of a match in every stage..... 3.. 10: Sample implementation of the selective-precharge matchline technique [52].............................. 4: Simulation results of the proposed CAM showing voltages ML0 (fully matched).... 2: Internal circuitry of improved Charging ....................................... 6......................... 4........ .............................. ML2 (two-bit miss)...... 32  Fig.. 5: Corner Simulation results for FHL (when threshold voltage= -10%................... MLC and MLP....................................................................... ........... 33  Fig........ 5........... 4....................................................... and temparature=343K)  ...... 3: Proposed sense amplifier (SA) ....................................................... ................. 29  Fig..... 9: (a) Circuit implementation including precharge circuitry and (b) a timing diagram for a single search cycle......... 3......... 4................. ................ 6..  45  Fig..................................... .. 13: Current-saving matchline-sensing scheme ....................[58] .................... 4.....................  38  Fig....................... ML1 (onebit miss)...... 3.......  53  Fig...... ..  42  Fig....................... 3..................... 47  Fig............ 3: The ML charging unit proposed in this work and the sensing unit proposed in [84].............. 1: Simplified conventional CAM architecture .............................  42  Fig...............................  . 8: Low-swing matchline sensing scheme of [33].  40  Fig...... 11: Pipelined matchlines reduce power by shutting down after a miss in a stage ........................................................................ 4...........................................  41  Fig...........  33  Fig......... 4: Simulation results of the proposed CAM showing voltages ML0 (fully matched)............... ........ 4............................................. 1: Structure of the CAM array. For current-race matchline sensing [51]...................  34  Fig... 47  Fig........................................  54  ix    ... 6............................................. 3: Waveforms for CAM  ..................  39  Fig... 5............................................. ML1 (onebit miss).................  .......... and temparature=273K)  ..LIST OF FIGURES PAGE Fig...........................VDD=-5%... 2: Internal circuit of the charging controller.......... 3...

.................................................LIST OF FIGURES PAGE Fig............. ............... 5: Charging in different match-lines. 6.. ..........................  55  Fig...................................... . 56  x    ............ 6: Controlled signals and output of each match-line............  55  Fig......... 6............................ 4: Conventional sense amplifier......................... 6.........................

......................................................................................  24  Table 3........  41  Table 5........................... 1: Comparison of Different Schemes with improved noise margin scheme ......................... 56  Table 6..........  24  Table 3.......................................... 1: Truth Table for NOR Cell  .....LIST OF TABLES PAGE  Table 3.......................................................  49  Table 6............... 1: Comparison of Different Schemes ................ 57  xi    ............................. 1: Comparison of Different Schemes ................................. 2: Comparison of Noise Immunity of different schemes .............................................. 3: Comparison between the schemes[62] ........................................................ 2: Truth Table for NAND Cell...................................................  35  Table 4...........................

In the first technique. For the second simplified scheme. This reduces the power consumption greatly. The purpose of this dissertation is the same i. We also hope that we would get some good alternatives for existing CAM after fabrication of the chip. the power consumption is very low.e. to find a way to design digital circuit specifically Content-Addressable Memory (CAM) which needs low power and operates in higher speed with maintaining the noise immunity. We can say that this dissertation provides some good schemes for the content addressable memory. All the schemes (conventional current saving and current race scheme also) are simulated in TSMC 0. For first charging control technique. This dissertation presents three techniques to increase speed and reduce the energy per bit per search. In the second scheme. simulation shows that the match-line energy reduction is 57% and 54% compared to the current-race and current-saving schemes respectively and 55% compared to the conventional current-race scheme while speed of operation is increased by over 3 times.18 µm technology with 64 x 72 Ternary CAM. In the third scheme with high noise margin. xii    . to design the circuits more efficiently which needs less power and operate in higher speed. Most of the matchlines are not charged so much. The more accurate result can be obtained by doing Layout of the proposed schemes. We hope that the proper layout of the schemes would provide good results also. the charging of fully matched matchline is reduced from VDD to VDD/3 and this voltage is sensed by our proposed sense amplifier. So in most of the matchlines. The third scheme provides very good noise margin with maintaining sufficient energy reduction and speed of operation.ABSTRACT The growing market demand of the integrated circuits and energy crisis in the whole world accelerate the researchers to find out new process technology with smaller transistors. the energy efficiency is little bit lower. Content-addressable memory (CAM) is an attractive component in network routers for packet forwarding and packet classification and also in other applications that require high-speed searches. only probable matched matchlines are charged to almost VDD. the charging controller is made simple (to get a low cost circuit) with the cost of some energy.

CHAPTER 1  INTRODUCTION  1    .

CAMs can be used in a wide variety of applications requiring high search speeds. a message such an as e-mail or a Web page is transferred by first breaking up the message into small data packets of a few hundred bytes. CAMs have a single clock cycle throughput making them faster than other hardware. and returns the address of the matching data.  The two main strategies available for implementing a CAM with a neural network architecture. Lempel–Ziv compression.and software-based search systems. These packets are routed from the source. To implement inverted polarity it is required to duplicate several circuit parts using inverted polarities of inputs and 2    . and reassembled at the destination to reproduce the original message. However. then. Two-stage CAMs are much more efficient. CAM is also used in neural networks. These applications include cache memory. in order to choose the appropriate one. Perceptron and least-mean squares algorithms need to be modified if they are to cope with corrupted input patterns. and in particular their ability to retrieve patterns from corrupted input data. The primary commercial application of CAMs today is to classify and forward Internet protocol (IP) packets in network routers.CHAPTER 1 INTRODUCTION     1. but the optimal classifier for the type of problem under consideration is the minimum-distance classifier (or Hamming network for binary patterns). such as the threshold algorithm which is described. Hough transformation. The storage capacity of the Hopfield network is very poor although it can be improved with the use of an iterative algorithm.1 INTRODUCTION       A CONTENT-ADDRESSABLE memory (CAM) compares input search data against a table of stored data. provided that an appropriate algorithm is used for the input classification stage. The function of a router is to compare the destination address of a packet to all possible routes. However. and image coding [1]. Huffman coding/decoding. feedback networks and two-stage CAMs. Dynamic CMOS logic in general and domino logic in particular has a number of advantages to design high speed and low power CMOS circuits. through the intermediate nodes of the network (called routers). the main difficulty with domino logic is that it can implement only non-inverted logic. A CAM is a good choice for implementing this lookup operation due to its fast search capability. In networks like the Internet. sending each data packet individually through the network. parametric curve extraction. the possibility of generating spurious patterns always remains with feedback networks. and.

two design parameters that designers strive to reduce. we have selected the current-race and current-saving scheme. The current-saving scheme is the improved version of current race scheme which allocates less power to match decision involving a large number of mismatched bits. there is almost a 50% reduction in SL power consumption [1]. all parts of the gate that follows an inverter has to be implemented again with opposite polarities of inputs. without sacrificing speed or area. is the main thread of recent research in large-capacity CAMs. clock skew etc. The literature shows that a major portion of power is consumed in Match lines (ML) and search lines (SL). the charging of fully matched matchline is reduced from VDD to VDD/3 and this voltage is sensed by our proposed sense amplifier. The low-swing scheme reduces the ML power by reducing the ML voltage. compared to the precharge-high matchline-sensing schemes that have an SL precharge phase. The selective precharge scheme reduces match-line power consumption by breaking the search into two segments and observing that the second segment is rarely activated. current-saving scheme [8]. As domino logic cannot implement inverters driving other domino gates. [11]. As CAM applications grow. about 50% of the search data bits toggle from cycle to cycle. [7].hence increasing area and power dissipation. Another difficulty with the domino logic is that it can only implement non-inverting functions. selective precharge scheme [6]. This reduces the power 3    . Another thing is that pre-charging the matchline eliminates the need of searchline precharge. However. A lot of researches have been done to reduce the ML and SL power consumption. [6]. [5]. In our proposed schemes. in our proposed charging control scheme. it is simple to realize gate with both inverted and non-inverted logic unlike dynamic CMOS logic [2]. on the other hand. The current-race scheme limits the ML voltage swing by VDD/2 and precharges the MLs to ground instead of VDD. demanding larger CAM sizes. compared to the precharge-high scheme [10]. In our scheme.2 MOTIVATIONS    The speed of a CAM comes at the cost of increased silicon area and power consumption. [9] etc. [4]. domino circuits have some inherent problems like charge sharing. the match-lines are precharged to ground at precharge stage unlike the conventional precharge high scheme so that power consumption in the matchlines is low. Secondly. The advantages of domino logic may come into question when there is a large number of inverters and having trapped in points where substantial duplication of domino gates is unavoidable. the power problem is further exacerbated. which increases area and power dissipation. Domino logic is known as a better logic for implementing high-speed CMOS circuits. Reducing power consumption. Previous works present some schemes such that low-swing scheme [3]. current-race scheme [7]. With static CMOS logic. So in the typical case. So to compare our proposed schemes. clock routing overhead. 1. It is reported in a survey [1] that the current saving scheme consumes less power than other schemes [10]. there is a 50% reduction in searchline power. as SL is not precharged.

4 THESIS ORGANIZATION  Continued increase in leakage current of the transistors with the advancement of process technology. a scheme named charging control scheme is proposed. one of our objectives was to design the charging controller intelligently. the higher the power consumption. the higher the matchline voltage. power consumption is very low. Chapter 3 underscores the significance of previous schemes and compares their performances and structure in details to reduce power consumption. In the scheme with high noise margin. Japan. This work is also accepted and presented in International Conference on Solid State Device and Materials (SSDM) 2008. our objective was to charge the matchline as VDD/3 and design a sense amplifier which can sense this voltage as a high. So in most of the matchlines. In this chapter. performance and noise robustness. impacts the leakage power and noise sensitivity of dynamic circuits more than those of static circuits. the charging controller is responsible for most of the power consumption. On the other hand. Tsukuba. So.consumption greatly. As CAM is based on dynamic logic investigation of dynamic logic is very important.   1. As satisfactory works is present on CAM cells. We specifically tried to design some good schemes for Content Addressable Memory (CAM). CAM is a special type of memory array which provides hardware search system where the information or data to be searched enters into the two-dimensional memory array and provides the search result (the address of memory where the data is found). our objective was to design an appropiate scheme of charging controllers and sense amplifier which consume less power and operate in high speed. only probable matched matchlines are charged to almost VDD. the charging controller and sense amplifiers. As most of the power is consumed in matchlines and matchlines are charged by the charging controller. For that reason. Chapter 4 describes one of the proposed schemes. 4    . Most of the matchline is not charged so much. Chapter 2 describes different type of logic circuits-study of which is needed to understand the significance of dynamic circuits. To design very high speed CAM we have investigated the CAM cells. This thesis proposes methods and techniques to achieve the goal of power-efficient design of CAM circuits used commonly in high-performance cache memory while improving or maintaining their area. 1.3 OBJECTIVES    The objective of this investigation and research was to find out a way or scheme to design high speed and low power dynamic circuits.

5    .Chapter 5 describes another scheme which contains the simplified version of charging controller of the scheme described in chapter 4. India. Hyderabad. a high amount of power is saved. It also mentions suggestions for extending the current research for possible future work. The principle of this technique is “carry coal to Newcastle”. Chapter 6 narrates a scheme which have high noise margin. This scheme charges only a negligible number of matchline to VDD. Chapter 7 presents a summary of proposed methods and techniques mentioned in the thesis for low-power CAM circuits in high-performance memory arrays. It is also accepted in TENCON 2008. For that reason. Finally.

CHAPTER 2  DIFFERENT TYPES OF LOGIC  6    .

then there is some Static Power dissipation. As CAM is based on dynamic logic investigation of dynamic logic is very important. Logic circuits such as ratioed logic. This study is needed to realize the significance of dynamic circuits. different types of logic circuits are described. If Pull down network is off. Static Power = 0.2. 2. 1: Resistor Pull-up 7    . If Pull down network is on. dynamic logic and domino logic are studied.1 INTRODUCTION    In this chapter. VDD  Resistive  Load RL  F Input PDN  VSS  Fig. CMOS logic.2 RATIOED LOGIC    Ratioed logic is an attempt to reduce the number of transistors required to implement a logic function. This arrangement is not often used because of the large space requirements of resistors produced in a silicon substrate.CHAPTER 2 DIFFERENT TYPES OF LOGIC 2.    2. 2.1 Load Resistance RL   The main goal is to reduce the number of transistors at the cost of reduced robustness and extra power dissipation. often at the cost of reduced robustness and extra power dissipation.

Power Dissipation is high since current flows when input voltage = logical 1. 2: nMOS depletion mode transistor pull up When switching the output from 1 to 0. VDD  Depletion  Load  F Input  PDN  VSS  Fig.2.2 nMOS depletion mode transistor pull up   Power dissipation is high since rail to rail current flows when input = logical 1.2. 2. Output voltage can never reach VDD (logical 1). 2. 8    . the pull up device is non-saturated initially and this presents lower resistance through which to charge capacitive loads. Switching of output from 1 to 0 begins when input voltage exceeds the Vt of the pull down device.2.3 nMOS enhancement mode pull up    If the gate of the pull-up transistor is connected to VDD then it is called nMOS enhancement mode pull up.                             VDD  F Input PDN  VSS  Fig. 3: nMOS enhancement mode pull up . 2.

2.4               VSS  Input PMOS  Load VSS  PDN F VDD  Fig. 5: Complementary transistor pull-up (CMOS) 9    . because no current flow either for logical 0 or for logical 1 inputs. VDD            Inputs          VSS  PDN  Output  PUN  Fig. we have a structure similar to the NMOS equivalent.2. 4: Pseudo-nMOS Logic The circuit arrangements look and behave much like nMOS circuits and appropriate ratio rules must be applied.2. 2. So. This approach of the logic design is illustrated in the Fig. there is no static power dissipation. 2. 2.4 Pseudo‐nMOS logic  If we replace the depletion mode pull-up transistor of the standard nMOS circuits with a p-transistor with gate connected to VSS. Full logical 1 and 0 levels are presented at the output. For devices of similar dimensions the p-channel is slower than the n-channel device.3 COMPLEMENTARY TRANSISTOR PULL‐UP (CMOS)    In CMOS we use both the pull-up network and also the pull down network.

6: CMOS inverter current versus Vin 10    . In long channel transistors the dynamic power is the dominant component of the total power.1] Dynamic power is a result of the power consumed in charging and discharging various device and wire capacitances in the circuit. the capacitances C being charged or discharged and square of supply voltage.1 Components of Total Power Dissipation in CMOS Circuits  One of the major design challenges in high-performance digital integrated circuits is the minimization of the total power dissipation. this is not the case in advanced technologies. as leakage power is becoming a significant component of total power. However.1] PowerTOTAL = PowerDYNAMIC + PowerSHORT −CIRCUIT + PowerLEAKAGE PowerDYNAMIC = AF × F × C × Vdd 2 PowerSHORTCIRCUIT = ( PowerLEAKAGE Trise + T fall 2 = I LEAKAGE × Vdd ) × Vdd × I PEAK [1. 2. b) Short-circuit power and c) Static or leakage power.       Current  (between rails)  Vin  Fig. this component of power depends on the switching activity factor (probability that a power consuming transition occurs) AF.3. Equation 1.1. As seen from Equation 1. clock frequency F.2. Vdd.1 defines total power and its three components in a simplified form [1. Total power consumption in digital CMOS circuits can be divided into three major components: a) Switching power or dynamic power.

Since the input signals to the logic gates have a nonzero/finite slope or edge rate. b) subthreshold leakage current between source and drain when gate-source voltage.4 DYNAMIC CIRCUITS    Ratioed circuits reduce the input capacitance by replacing the pMOS transistors connected to the inputs with a single resistive pull-up. there is a direct path current between Vdd and Vss for a period of time during which both the PMOS and NMOS devices conduct simultaneously. Precharge  CLK  Evaluate Precharge  Y  Fig. The magnitude of this current is given by the actual transistor widths and the on-state saturation current (IDSAT). Vt of the transistors and c) gate leakage current via the gate tunneling mechanism. Because of the quadratic dependence of dynamic power on Vdd. static power dissipation and a non-zero VOL. contention on the falling transitions.1. 7: Precharge and evaluation of dynamic gates. In a simplified form it can be calculated as shown in Equation 1. reducing threshold voltage causes the sub-threshold leakage current to increase exponentially. The drawbacks of ratioed circuits includes slow resistive transitions. Static or leakage power dissipation is due to the leakage current.                   2. reducing this voltage is the most effective approach to minimize dynamic power dissipation. The duration for which the current flows depends on the signal rise and fall times and increases as the signal slopes degrade. However. Vgs. where Trise and Tfall are the rise and fall times respectively and IPEAK is the peak short circuit current. Three major sources of leakage current are: a) current flowing through reverse biased P-N diode junctions of the transistors located between the source or drain and substrate. ILEAKAGE that flows between power rails in the absence of any switching activity. The overall short-circuit power can be obtained by integrating the total current over the duration of short circuit and then multiplying with Vdd. is smaller than the threshold voltage. 2. 11    . Unfortunately. Dynamic circuits circumvent these drawbacks by using a clocked pull-up transistor rather than a pMOS that is always ON. reducing the supply voltage necessitates the reduction of threshold voltage to avoid serious degradation of performance.Short-circuit power is dissipated when there is a direct conducting path between power supply (Vdd) and ground (Vss).

so the clocked pMOS is ON and initializes the output Y high. CLK Y Inputs PDN  Fig. 2. 8: Footed dynamic inverter   Dynamic circuits are the fastest commonly used circuit family because they have lower input capacitance and no contention during switching. the clock (CLK) is ‘0’. and are sensitive to noise during evaluation. CLK  Precharge  Transistor    Y A  FOOT Fig.Dynamic circuit operation is divided into two modes. the clock is ‘1’ and the clocked pMOS turns OFF.7. contention will take place because both the pMOS and nMOS transistors will be ON. During precharge. 2. However.9 if the input is ‘1’ during precharge. 9: Unfooted dynamic gates. shown in Fig. The output may remain high or may be discharged low through the pull-down network. During evaluation. They also have static power dissipation. In Fig.   12    . they require careful clocking. 2. 2. consume significant dynamic power.

10. Precharge occurs while the gate is idle and often may take place more slowly. 10: Generalized footed gates.When the input cannot be guaranteed to be ‘0’ during precharge. Fig. 2.an extra clocked evaluation transistor can be added to the bottom of the nMOS stack to avoid contention as shown in Fig. The extra transistor is sometimes called a foot. As usual. 2. CLK  Y Inputs  PDN  Fig. 2. Inverter CLK  Y    A  CLK    Y A gd=1/3 Pd=2/3 gd=2/3 Pd=3/3 Fig. 2. Therefore. 11: Logical effort of footed and unfooted dynamic gates 13    . the precharge transistor width is chosen for twice unit resistance. This reduces the capacitive load on the clock and the parasitic capacitance at the expense of greater rising delays. Fig. 2.11 estimates the falling logical effort of both footed and unfooted dynamic gates. the pull-down transistors widths are chosen to give unit resistance.10 shows generic footed gates.

the precharge transistor is also OFF. 2. dynamic gates are particularly well suited to wide NOR functions or multiplexers because the logical effort is independent of the number of inputs. 12: Monotonicity problem The input later falls LOW. When the clock rises. as happen in an inverter. Violates monotonicity  during evaluation  A  Precharge  CLK  Evaluate  Precharge  Y  Output should rise but does not  Fig. While a dynamic gate is in evaluation.Footed gates have higher logical effort than their unfooted counterparts but are still an improvement over static logic. staying LOW rather than rising as it would in a normal inverter. During precharge.12 shows waveforms for a footed dynamic inverter in which the input violates monotonically. the logical effort of footed gates is better than predicted because velocity saturation means series nMOS transistors have less resistance than we estimate. but not start HIGH and fall LOW. the inputs must be monotonically rising. Like pseudo-nMOS gates. the output is pulled HIGH. 14    . the inputs must be monotonically rising for the dynamic gate to compute the correct function. In practice. That is. turning off the pull-down network. However. A fundamental difficulty with the dynamic circuits is the monotonicity requirement. Fig. The output will remain low until the next precharge step. the input can start LOW and remain LOW. In summary. start HIGH and remain HIGH. 2. so the output floats. start LOW and rise HIGH. The size of the foot can be increased relative to the other nMOS transistors to reduce logical effort of the other inputs at the expense of greater clock loading. the input is HIGH so the output is discharged LOW through the pull-down network.

Unfortunately, the output of a dynamic gate begins HIGH and monotonically falls LOW during evaluation. This monotonically falling output X is not a suitable input to a secong dynamic gate expecting monotonically rising signals as shown in Fig. 2.13. Dynamic gates sharing the same clock cannot be directly connected. This problem is often overcome with domino logic.

CLK  X A 

Y

A=1  Precharge  CLK  Precharge 

Evaluate 

X  X monotonically falls during evaluation 

Y  Y should rise but cannot 

Fig. 2. 13: Incorrect connection of dynamic gates.

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2.5 DOMINO LOGIC 
Domino logic circuits find wider applications in high performance microprocessors due to their superior speed and area characteristics as compared to static CMOS circuits. But their noise margins are low making them more prone to noise. Various leakage reduction techniques are applied to domino logic circuits also to reduce the leakage. As the technology is scaled below 130nm, noise margin becomes a critical issue and hence techniques that provide high noise immunity become necessary in order to have reliable circuits. The monotonicity problem can be solved by placing a static CMOS inverter between dynamic gates as shown in the figure. This converts the monotonically falling output into a monotonically rising signal suitable for the next gate. The dynamic- static pair together is called a domino gate. A single clock can be used to precharge and evaluate all the logic gates within the chain. Therefore, the static inverter is usually a HI-skew gate to favor this rising output. We may observe that precharge occurs in parallel, but evaluation occurs sequentially. A standard domino logic circuit with a keeper is as shown in Fig. 2.14. A standard domino logic circuit consists of an n-type dynamic logic block followed by a static inverter. During precharge, the output of the dynamic gate is charged to Vdd and the output of the inverter is set to 0.

Fig. 2. 14: Standard Domino Logic circuit

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During evaluation, the inverter makes conditional transition from 0 to 1. If the output of the domino gate is fed to other domino gates, then it must be ensured that all inputs are set to 0 at the end of the precharge phase and the transitions during evaluation are only 0 to 1. Hence the dynamic node discharges only when the previous stage evaluates to 1 and a high fan-out is achieved due to the static inverter present at the output. To counteract the leakage issues and to establish a low impedance path, a bleeder transistor (keeper) is connected in the feedback path.
    Width: min Length:L 
CLK 

X A 

Y

Fig. 2. 15: Weak keeper implementation

The function of the keeper is to compensate the charge lost due to the pull-down leakage paths. But the keeper is fully turned on at the beginning of the evaluation phase. When the pull down network is ON, then there exists a contention between this and keeper transistor, which degrades the speed of domino circuits. Traditionally, a minimum sized keeper is used to minimize delay and power degradation caused by the contention current. A small keeper, however, cannot provide necessary noise immunity for reliable operation in an increasingly noisy and noise-sensitive on-chip environment. Therefore, there is a tradeoff between the high speed/energy efficient operation and reliability in domino logic. Hence, keeper sizing is important in deep sub micron circuits.

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  CHAPTER 3  CONTENT ADDRESSABLE MEMORY  (CAM) REVIEW    18    .

Energy per search and search speed are two important metrics used to evaluate CAM performance[12]Content addressable memory (CAM). all of them are discussed in this research. sending each data packet individually through 19    . input transition power and clocking power. These applications include parametric curve extraction [18]. artificial intelligence. a new low-power CAM design is proposed here. Its implementation under 0. Hough transformation [19]. CAMs have a single clock cycle throughput making them faster than other hardware and software-based search systems. We have proved that under most conditions cell layout is smaller by this modification. Two modified circuit structures for binary static CAM cells are also proposed. CAMs are now much needed where quick searches of a database. CAMs can be used in a wide variety of applications requiring high search speeds. After that. makes CAMs a more attractive solution to the less expensive RAM software solution. Lempel–Ziv compression [22]–[25]. file storage management. CAM has three major power-sinking sources: evaluation power. then. database management and pattern recognition. a high-performance lookup engine in many systems. and image coding [26].1 INTRODUCTION    Content addressable memories (CAMs) are memories that can search the entire memory in parallel and output the location of entries that hold a match to the key value. a list. In fact. or a pattem is in order. The primary commercial application of CAMs today is to classify and forward Internet protocol (IP) packets in network routers [27]–[32]. a message such an as e-mail or a Web page is transferred by first breaking up the message into small data packets of a few hundred bytes.5fJ/bit/search or equivalently 372 mJ/bit/search/m for random inputs. larger table sizes and wider data widths. In networks like the Internet. A Content Addressable Memory (CAM) compares input search data against a table of stored data.35-p m process operates at 83. [21]. This feature is used extensively in applications such as internet routers to channel incoming packets towards their destination addresses contained in the packet header. CAMs can be a determining factor for a wide range of applications such as local-area networks. A Content-Addressable Memory (CAM) searches for data by its content and returns the address of the matching data.Chapter 3 CONTENT ADDRESSABLE MEMORY (CAM) REVIEW     3.3 MHz with power performance metric as 45. and returns the address of the matching data [13]–[17]. Today the increased need for faster searches. Huffman coding/decoding [20]. and. is so power-consuming that any saving becomes very significant in the whole system.

Each stored word has a matchline that indicates whether the search word and stored word are identical (the match case) or are different (a mismatch case. A typical CAM employs a table size ranging between a few hundred entries to 32K entries. in order to choose the appropriate one. through the intermediate nodes of the network (called routers). corresponding to an address space ranging from 7 bits to 15 bits.the network. As CAM applications grow.1 shows a simplified block diagram of a CAM. is the main thread of recent research in large capacity CAMs. A priority encoder selects the highest priority matching location to map to the match result. The matchlines are fed to an encoder that generates a binary match location corresponding to the matchline that is in the match state. The overall function of a CAM is to take a search word and 20    . However. In addition. the power problem is further exacerbated. These packets are routed from the source. with existing implementations ranging from 36 to 144 bits. SL0 SL0 SL1 SL1 SL2 SL2 ML0 C C C ML1 Encoder Hit C C C ML2 C C C ML3 C C C Input Search Data Drivers/Registers Fig. The function of a router is to compare the destination address of a packet to all possible routes. we survey developments in the CAM area at two levels: circuits and architectures. 3. In this research. differential search lines. without sacrificing speed or area. Before providing an outline of this research at the end of this section. 1: Simple schematic model of a 4x3 CAM array showing the core memory cells. The input to the system is the search word that is broadcast onto the searchlines to the table of stored data. and reassembled at the destination to reproduce the original message. there is often a hit signal (not shown in the figure) that flags the case in which there is no matching location in the CAM. the speed of a CAM comes at the cost of increased silicon area and power consumption. two design parameters that designers strive to reduce. Reducing power consumption. or miss). 3. with words in lower address locations receiving higher priority. demanding larger CAM sizes. An encoder is used in systems where only a single match is expected. we first briefly introduce the operation of CAM and also describe the CAM application of packet forwarding. In CAM applications where more than one word may match. A CAM is a good choice for implementing this lookup operation due to its fast search capability. a priority encoder is used instead of a simple encoder. match lines and encoder Fig. The number of bits in a CAM word is usually large.

capacity CAMs rather than on fully associative caches. which is an address. which target smaller capacity and higher speed. This rule of thumb comes from the fact that a typical CAM cell consists of two SRAM cells. 2: Profile of CAM capacity (log scale) versus year of publication [33]–[40] The operation of a CAM is like that of the tag portion of a fully associative cache. 3. a single matchline goes high. [40]. to all addresses stored in the tag memory. the largest available CAM chip is usually about half the size of the largest available SRAM chip. although the largest CAMs reported in the literature are 9 Mbit in size [33]. Unlike CAMs. Today’s largest commercially available single-chip CAMs are 18 Mbit implementations.2 plots (on a logarithmic scale) the capacity of published CAM [33]–[40] chips versus time from 1985 to 2004. 2005 21    . revealing an exponential growth rate typical of semiconductor memory circuits and the factor-of-two relationship between SRAM and CAM. One can think of this operation as a fully programmable arbitrary mapping of the large space of the input search word to the smaller space of the output match location. the matchline directly activates a read of the data portion of the cache associated with the matching tag. indicating the location of a match. 8M Memory Size (bit) 10k 1986 Year Fig. Many circuits are common to both CAMs and caches. Fig. 3. we focus on large. In the case of match.return the matching memory location. however. caches do not use priority encoders since only a single match occurs. as we will see shortly. instead. The tag portion of a cache compares its input. As a rule of thumb.

3. 2 CORE CELLS AND MATCHLINE STRUCTURE 
 

A CAM cell serves two basic functions: bit storage (as in RAM) and bit comparison (unique to CAM). Fig. 3.4 shows a NOR-type CAM cell [Fig. 3.3(a)] and the NAND-type CAM cell [Fig. 3.3(b)]. The bit storage in both cases is an SRAM cell where cross-coupled inverters implement the bit-storage nodes D and DB . To simplify the schematic, we omit the nMOS access transistors and bitlines which are used to read and write the SRAM storage bit. Although some CAM cell implementations use lower area DRAM cells [3.27], [3.31], typically, CAM cells use SRAM storage. The bit comparison, which is logically equivalent to an XOR of the stored bit and the search bit is implemented in a somewhat different fashion in the NOR and the NAND cells.

3.2.1 Structure of NOR Cell 
 

A NOR Cell implements the comparison between the complementary stored bit, D (and DB), and the complementary search data on the complementary searchline, SL (and SLB), using four comparison transistors, M1 through M4, which are all typically minimumsize to maintain high cell density. These transistors implement the pull down path of a dynamic XNOR logic gate with inputs SL and D. Each pair of transistors, M1/M3 and M2/M4, forms a pull down path from the matchline, ML, such that a mismatch of SL and D

Fig. 3. 3: CAM core cells for (a) 10-T NOR-type CAM and (b) 9-T NAND-type CAM. The cells are shown using SRAM-based data-storage cells. activates least one of the pull down paths,connecting ML to ground. A match of SL and D disables both pull down paths, disconnecting ML from ground. The NOR nature of this cell becomes clear when multiple cells are connected in parallel to form a CAM word by shorting the ML of each cell to the ML of adjacent cells. The pull down paths connect in parallel resembling the pull down path of a CMOS NOR logic gate. There is a match condition on a given ML only if every individual cell in the word has a match.

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3.2.2 Structure of NAND Cell 
 

The NAND cell implements the comparison between the stored bit, D, and corresponding search data on the corresponding searchlines, (SL, SLB), using the three comparison transistors M1, MD and MDB, which are all typically minimum-size to maintain high cell density. We illustrate the bit-comparison operation of a NAND cell through an example. Consider the case of a match when SL=1 and D=1. Pass transistor MD is ON and passes the logic “1” on the SL to node B. Node B is the bit-match node which is logic “1” if there is a match in the cell. The logic “1” on node B turns ON transistor M1. Note that is also turned ON in the other match case when SL=0 and D=0 . In this case, the transistor MDB passes a logic high to raise node B. The remaining cases, where SL≠D result in a miss condition, and accordingly node B is logic “0” and the transistor M1 is OFF. Node B is a pass-transistor implementation of the XNOR SLΘD function. The NAND nature of this cell becomes clear when multiple NAND cells are serially connected. In this case, the MLn and MLn+1 nodes are joined to form a word. A serial nMOS chain of all the Mi transistors resembles the pull down path of a CMOS NAND logic gate. A match condition for the entire word occurs only if every cell in a word is in the match condition. An important property of the NOR cell is that it provides a full rail voltage at the gates of all comparison transistors. On the other hand, a deficiency of the NAND cell is that it provides only a reduced logic “1” voltage at node B, which can reach only VDD - Vtn sswhen the searchlines are driven to VDD (where VDD is the supply voltage and Vtn is the nMOS threshold voltage).

3.2.3 Ternary Cells 
 

Usually two types of ternary cell are used. The NOR and NAND cells that have been presented are binary CAM cells. Such cells store either a logic “0” or a logic “1”.Ternary cells, in addition, store an “X” value. The “X” value is a don’t care, that represents both “0” and “1”, allowing a wildcard operation. Wildcard operation means that an “X” value stored in a cell causes a match regardless of the input bit. As discussed earlier, this is a feature used in packet forwarding in Internet routers. A ternary symbol can be encoded into two bits according to Table 2.2. We represent these two bits as D and DB. Note that although the D and DB are not necessarily complementary, we maintain the complementary notation for consistency with the binary CAM cell. Since two bits can represent 4 possible states, but ternary storage requires only three states, we disallow the state where D and DB are both zero. To store a ternary value in a NOR cell, we add a second SRAM cell, as shown in Fig. 3.5. One bit, D, connects to the left pulldown path and the other bit, DB, connects to the right pull down path, making the pull down paths independently controlled.We store an “X” by setting both D and DB equal to logic “1”, which disables both pull down paths and forces the cell to match regardless in the inputs. We store a logic “1” by setting D=1 and DB=0 and store a logic “0” by setting D=0 and DB=1. In addition to storing an “X”, the cell allows searching for an “X” by setting both SL and SLB to logic “0”. This is an external don’t care that forces a match of a bit regardless of the stored bit.

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Table 3. 1: Truth Table for NOR Cell Stored Value Stored D 0 1 X 0 1 1 D 1 0 1 Search D 0 1 0 D 1 0 0

Table 3. 2: Truth Table for NAND Cell Stored Value Stored Bit D 0 1 x x 0 1 0 1 M 0 0 1 1 Search Bit SL 0 1 1 1 SL 1 0 1 1

Fig. 3. 4: Structure of Ternary core cells for (a) NOR-type (b) NAND-type CAM [41], [42].

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the NOR cell and the NAND cell are the prevalent core cells for providing storage and comparison circuitry in CMOS CAMs. In cases where ternary operation is needed but only binary CAMs are available. the cell allows searching for an “X” by setting both SL and SLB to logic “1”.3 MATCHLINE SENSING SCHEMES  This section reviews matchline sensing schemes that generate the match result. timing control and power consumption. When storing an “X”. slowing down the search operation. Further minor modifications to CAM cells include mixing parts of the NAND and NOR cells. [42]. regardless of the value of D.4(b) [41]. ensuring that the cell always matches.4(a). it is possible to emulate ternary operation using two binary cells per ternary symbol. rather than minimum-size nMOS transistors. propose implementing the pull down transistors M1-M4 using pMOS devices and complementing the logic levels of the searchlines and matchlines accordingly. charge sharing. then introduce several variations that save power. due to reducing the number of spacings of p-diffusions to n-diffusions in the cell. as depicted in Fig. 25    . This forces transistor Mmask ON. and alternating the logic level of the pull down path to ground in the NOR cell [44]–[46]. In addition to storing an “X”.2 lists the stored encoding and search-bit encoding for the ternary NAND cell.1 Conventional (Precharge‐High) Matchline Sensing  We review the basic operation of the conventional precharge-high scheme and look at sensing speed. 3. In addition to increased density. For a comprehensive survey of the precursors of CMOS CAM cells refer to [47]. The tradeoff that results from using minimum-size pMOS transistors.   3.  3. Currently.3. Using pMOS transistors (instead of nMOS transistors) for the comparison circuitry allows for a more compact layout. Table 2.Although storing an “X” is possible only in ternary CAMs. using dynamic-threshold techniques in silicon-on-insulator (SOI) processes. As a modification to the ternary NOR cell of Fig. an external “X” symbol possible in both binary and ternary CAMs. we review the conventional precharge high scheme. the smaller area of the cell reduces wiring capacitance and therefore reduces power consumption. we set this mask bit to “1”.3. is that the pulldown path will have a higher equivalent resistance. A NAND cell can be modified for ternary storage by adding storage for a mask bit at node M. First.

and (b) the corresponding timing diagram showing relative signal transitions. the operation continues by asserting mlpreb to precharge the matchline high. which is output on the MLSA sense-output node. ML precharge. Fig.1. called Fig. 5: (a) the schematic with precharge circuitry for matchline sensing using the precharge-high scheme.3. The operation begins by asserting slpre to precharge the searchlines low. ML. [34] 26    . 3.5(b) shows the signal timing which is divided into three phases: SL precharge. 3. in schematic form. a path (or multiple paths) to ground will discharge the matchline. The ML evaluate phase begins by placing the search word on the searchlines. or leave the matchline high in the case of a match. If there is at least one single-bit miss on the matchline. indicating amiss for the entire word.With the pull down paths disconnected. Fig.5(a) shows. Once the matchline is high. an implementation of this matchline-sensing scheme. 3.1 Basic Operation   The basic scheme for sensing the stateof the NOR matchline is first to precharge high the matchline and then evaluate by allowing the NOR cells to pull down the match-lines in the case of amiss. and ML evaluation. disconnecting all the pull down paths in the NOR cells. both slpre and mlpreb are de-asserted.3.

Fig.3 Charge Sharing   There is a potential charge-sharing problem depending on whether the CAM storage bits D and DB are connected to the top transistor or the bottom transistor in the pulldown path. 27    . the number of misses is expected to be much greater than the number of matches. we will investigate the performance of matchline in terms of speed. using a dynamic NAND structure results in a significant reduction in power. and power consumption. thus. 6: Matchline power for NAND and NOR architecture [33] 3.2 Matchline  power    In a typical system. If all bits on the matchline match. robustness. The matchline power dissipation is one of the major sources of power consumption in CAM. Using this sketch of the precharge high scheme. 3. thematchline will remain high indicating a match for the entire word.1. especially for wide words.MLso. Fig.1.6 demonstrates the power advantages of a NAND architecture versus a NOR.3. 3. 3. 1A NAND match-line architecture is considerably slower than it has NOR counterpart.3.

and nodes X1 and X2. and (b) the stored bit is connected to the top transistors of the pulldown pair. where the stored bit is connected to the top transistors. designers use the configuration shown in Fig. 3. VML. causing the ML voltage.1. Once the precharge completes. This shares the charge at node X1 or node X2 with that of ML. since typically there are only a small number of matches we can neglect this power consumption. there is a charge-sharing problem between the matchline.     Fig.Fig.7(a). Accordingly. which occurs immediately after the matchline precharge-high phase. SL and SLB are both at ground. charge sharing is eliminated. Charge sharing occurs during matchline evaluation. Since the stored bit is constant during a search operation. however. In the case of a match. ML. 7: Two possible configurations for the NOR cell: (a) the stored bit is connected to the bottom transistors of the pulldown pair. In the configuration of Fig.3. the power consumption associated with a single matchline depends on the previous state of the matchline.4 Power Consumption   The dynamic power consumed by a single matchline that misses is due to the rising edge during precharge and the falling edge during evaluation. to drop. which may lead to a sensing error. even in the case of match. 3. and is given by the equation Pmiss = fCMLVDD2 Where f is the frequency of search operations. 3.7 (b). To avoid this problem. one of the searchlines is activated. causing either M1 or M2 to turn ON. the overall matchline power consumption of a CAM block with w matchlines is PML=wPmiss       28    .3. depending on the search data.7 shows these two possible configurations of the NOR cell. 3. During matchline precharge.

whereas in the case of match. One method of reducing the ML power consumption. In the case of a miss. with every matchline. the matchline discharges through the CAM cell(s) to ground.3. The precharge operation (assertion of pre signal) charges the tank capacitor to VDD and then uses charge sharing (enabled by eval signal) to dump the charge onto the matchline. The reduction of power consumption is linearly proportional to the reduction of the voltage swing.3. The main challenge addressed by various low-swing implementations is using a low-swing voltage without resorting to an externally generated reference voltage. the matchline remains at the precharge level. A similar charge-sharing matchline scheme was also described in [50]. Fig.   29    . which saves power by reducing swing.4 LOW‐SWING SCHEMES    The ML power consumption is an important issue and challenge to the researchers. resulting in the modified power equation PML=wfCMLVDDVMLswing Where VMLswing is the voltage swing of the ML. 8: Low-swing matchline sensing scheme of [33]. [50]. 3. The matchline swing is reduced from the full supply swing to mV. Ctank. and is set to be equal to 300 mV in the design [33]. Researchers proposed many techniques of reducing ML power consumption. This sense amplifier is shown in generic form in the figure. Precharge to VLow =300 mV is accomplished by associating a tank capacitor. Fig.Matchline evaluation uses a sense amplifier that employs transistor ratios to generate a reference level of about VLow /2 =150mV. is to reduce the ML voltage swing [33].8 is a simplified schematic of the matchline sensing scheme of [33]. and potentially increasing its speed.

9. The signal timing is shown in Fig. 3. eliminating the need for a separate SL precharge phase required by the precharge-high scheme of Fig. 3. while a matchline in the miss state charges to a voltage of only IML*RML /m.9(b). 3. After some delay. A matchline in the match state charges linearly to a high voltage.9(a) shows a simplified schematic of the current-race scheme [51]. the enable signal. enb. leaving their latch in the initial state. there is a single SL/ML precharge phase. the amplifier is the nMOS transistor. the power consumed to charge a matchline to slightly above Vtn is Pmatch=fCMLVDDVtn Since the power consumption of a match and a miss are identical. whereas matchlines in the miss state will remain at a much smaller voltage. The benefits of this scheme over the precharge-high schemes are the simplicity of the threshold circuitry and the extra savings in searchline power due to the elimination of the SL precharge phase which is discussed 30    . The precharge signal. whose output is stored by a half-latch. connects the current source to the matchline. Fig. Looking at the match case for convenience. regardless of the state of the matchline.5 CURRENT‐RACE SCHEME  Current-Race saving is an important scheme for the CAM architecture. Instead. a simple matchline sense amplifier easily differentiates between a match state and a miss state and generates the signal MLso. as indicated in Fig. 3. matchlines in the match state will charge to slightly above tripping their latch. Since the matchline is precharged low. the overall power consumption for all w matchlines is PML=wPmatch This equation is identical to the low-swing scheme (previous equation) with VMLswing=Vtn. A simple replica matchline (not shown) controls the shutoff of the current source and the latching of the match signal. 3. the scheme concurrently charges the searchlines to their search data values.5(b).3. The nMOS sense transistor trips the latch with a threshold of Vtn. By setting the maximum voltage of a miss to be small. starts the search cycle by precharging thematchline low. As shown in Fig. Msense. mlpre. We derive the power consumption of this scheme by first noting that the same amount of current is discharged into every matchline.9(b). This scheme precharges the matchline low and evaluates the matchline state by charging the matchline with a current IML supplied by a current source. where m denotes the number of misses in cells connected to the matchline. After the SL/ML precharge phase completes.

3. However.3. the variation of parasitic capacitance on the matchline depends only on the states of SL and SLB which are the same for all cells in the same column.7(a). 3.6. performs a match operation on the first few bits of a word before activating the search of the remaining bits 31    . 3. 9: (a) Circuit implementation including precharge circuitry and (b) a timing diagram for a single search cycle. Changing CAM cell configuration is an important feature of current racing scheme. The first technique. The matchline-sensing techniques we have seen so far. For current-race matchline sensing [51]. the configuration of Fig. there is no charge-sharing problem for either CAM cell configuration of Fig. In the configuration of Fig. Rather than to avoid charge sharing. there will be variations in the capacitance CML among the MLs. We now examine three schemes that allocate power to matchlines nonuniformly. the criterion that determines which cell to use in this case is matching parasitic capacitances between MLs. expend approximately the same amount of energy on every matchline. Since different cells will have different stored data. the parasitic load on a matchline depends on the ON/OFF state of M1 and of M2. regardless of the specific data pattern.Fig.7(b). and whether there is a match or a miss.7(a) maintains good matching between MLs and prevents possible sensing errors due to parasitic capacitance variations. The current-race scheme also allows changing the CAM cell configuration due to the fact that the matchline is precharged low. 3. Thus.6 SELECTIVE‐PRECHARGE SCHEME    Selective precharge scheme came considering the non uniform ML power consumption.    3. called selective precharge. With precharge low. in the configuration of Fig. since the ML precharge level is the same as the level of the intermediate nodes X1 and X2.

11(a) shows a simplified schematic of a conventional NOR matchline structure where all cells are connected in parallel. one implementation of selective precharge is to use this mixed NAND/NOR matchline structure. 3. there are two sources of overhead that limit the power saving. an implementation may divide the matchline into any number of segments.11(a). but with the matchline broken into four matchline segments that are serially evaluated. Selective precharge is perhaps themost commonmethod used to save power on matchlines [34]. Second. in the worst-case scenario. which is controlled by the NAND CAM cell and turned on only if there is a match in the first CAM bit. the initial 3-bit search should allow only ½ 3 words to survive to the second stage saving about 88% of the matchline power. 10: Sample implementation of the selective-precharge matchline technique [52]. selective precharge initially searches only the first 3 bits and then searches the remaining 141 bits only for words that matched in the first 3 bits. The remaining cells are NOR cells. [53]–[57] since it is both simple to implement and can reduce power by a large amount in many CAM applications. in a 144-bit word. 3. the initial match implementation may draw a higher power per bit than the search operation on the remaining bits. The example uses the first bit for the initial search and the remaining n-1 bits for the remaining search. resulting in power saving. Fig. 32    .7 PIPELINING SCHEME    More generally. Thus. Assuming a uniform random data distribution.7(a) and (b)]. 3. 3.10 is a simplified schematic of an example of selective precharge similar to that presented in the original paper [52]. The ML is precharged through the transistor M1.[52]. 3.  3. A design that uses multiple matchline segments in a pipelined fashion is the pipelined matchlines scheme [58]. the subsequent stages are shut off. an application may have a data distribution that is not uniform. eliminating any power saving. the initial match bits are identical among all words in the CAM. 3. Note that the ML of the NOR cells must be pre-discharged (circuitry not shown) to ground to maintain correct operation in the case that the previous search left thematchline high due to a match. The drawbacks of this scheme are the increased latency and the area overhead due to the pipeline stages. where a match in a given segment results in a search operation in the next segment but a miss terminates the match operation for that word. For example. To maintain speed. In practice. [59]. to maintain speed.11(b) shows the same set of cells as in Fig. Fig. the implementation modifies the precharge part of the precharge-high scheme [of Fig. Fig. If any stage misses. First. Fig. and.

Fig. In this design.   Fig. and (b) a miss case where the third stage results in a miss and turns off the subsequent stages. the subsequent cells do not activate.[58] 33    . If at any cell there is a miss. 11: Pipelined matchlines reduce power by shutting down after a miss in a stage By itself. as there is no need for a comparison operation. a pipelined matchline scheme is not as compelling as basic selective precharge. 3. thus saving power. pipelining enables the use of hierarchical searchlines. 3. 12: Simulated wave forms in the pipelined match-line architecture for (a) the fullmatch case consisting of a match in every stage. Thus. Another approach is to segment the matchline so that each individual bit forms a segment. the CAM cell is modified so that thematch evaluation ripples through each CAM cell. selective precharge operates on a bit-by-bit basis. The drawback of this scheme is the extra circuitry required at each cell to gate the comparison with the result from the previous cell. however.

This block is the mechanism by which a different amount of current is allocated. [61] is another data-dependent matchline-sensing scheme which is a modified form of the current-race sensing scheme. overall the scheme saves power.3. the ML sensing circuitry of the fourth and fifth segments is not activated. In this example. and the output is a control voltage that determines the current. The input to this current-control block is the matchline voltage. which charges the matchline. Fig 3.12 shows a full match as indicated by the rising ML in every segment along with the corresponding full-rail output of the MLSA. VML. which. The key improvement of the current-saving scheme is to allocate a different amount of current for a match than for a miss. hence saving power. 34    . 13: Current-saving matchline-sensing scheme Fig. 3.12(b) shows an example of a word that misses in the third stage as indicated by the lack of an MLSA output pulse. The main difference from the current-race scheme as depicted in Fig.9 is the addition of the currentcontrol block.8 CURRENT‐SAVING SCHEME  The current-saving scheme [60]. 3. Fig.Fig 3. based on a match or a miss. In the current-saving scheme matches are allocated a larger current and misses are allocated a lower current. in turn.13 shows a simplified schematic of the current-saving scheme.12 shows the simulated waveforms of the ML segments in the pipelined ML scheme. 3. Fig 3. The current-control block provides positive feedback since higher VML results in higher IML. regardless of whether it has a match or a miss. Recall that the currentrace scheme uses the same current on each matchline. Since almost every matchline has a miss. IML. results in higher VML.

The researchers gave a good importance to these two factors and improved the power and speed significantly.3 3.7 3.5 5. The previous result from the simulation that the researchers performed is shown below in table format.8 4.8 3.3. Researchers gave importance to these two factors too.1 3. Table 3.5 3. Scheme simplicity and noise immunity are other two factors.9 3. 3: Comparison between the schemes[62] Scheme ML energy fj/bit/search Conventional Low swing Current race Selective precharge Pipelining Current saving 9.5 4.9 CONCLUSION  From the above discussion of previous Content addressable Memory (CAM) it is clearly shown that the main concern was power and speed.7 + + + Cycle time(ns) Noise Scheme simplicity ++ + + --     35    .6 5.2 5.

  CHAPTER 4  PROPOSED CHARGING CONTROL  SCHEME & SENSE AMPLIFIER     36    .

2 shows the proposed charging controller. Due to the rising demand of CAM for high speed search capability in various applications. the ML has no discharging path to ground and the path remains in the high-impedance state. So. During the evaluation stage. MLC is switched to high so that charging of ML through M3 begins. at the beginning of search cycle. If SL resembles stored bit D or the stored bit is X (don’t care). charging of ML through M3 remains prohibited during the pre-discharging of ML. etc. The transistor M2 is turned ON by a low MLP and M5 is OFF by a low MLC. in a ML. the search data register broadcasts the search data to the search-lines (SLs). 37    . In this work. Fig. this causes M3 to be turned OFF. During the evaluation stage. 4. current-saving scheme [65]. Therefore. Comparison with the current-race and current-saving schemes shows match-line energy reduction of over 50% and speed improvement of over 3 times. A lot of researches have been done to reduce the power consumption and to increase the speed. the size as well as power consumption of CAM arrays continue to rise. the array of CAM cells stores the data entries.1(a) shows the basic architecture of the proposed charge controlling scheme. Here. 4. ML is pre-discharged to ground by a high MLP. Here. and the sense amplifier (SA) senses the ML voltage and gives the final match/miss decision.CHAPTER 4 PROPOSED CHARGING CONTROL SCHEME & SENSE AMPLIFIER     4. It is reported in a survey [67] that the current-saving scheme consumes less power than other schemes [63]. If SL does not resemble D. [68]. At the beginning of each search cycle. At the same time. the ML has a discharging path (through either transistors T1-T2 path or T3-T4 path) to ground. current-race scheme [64]. MLP is switched to low so that both M1 and M2 turn OFF. [66]. search data register stores the search word.2 PROPOSED CHARGE CONTROLLING SCHEME  Fig. we proposed a simplified match-line charging control scheme. Fig.1(b) shows the internal circuit of conventional NORtype Ternary CAM (TCAM) cell which is less susceptible to failure due to the process variation as compared to NAND-type cell [69]. Previous works present some schemes such as selective-precharge scheme [63]. the number of discharging paths is equal to the number of mismatches.1 INTRODUCTION    Content-addressable memory (CAM) is a storage device that searches for the matching data by content and returns the address of the matching data. 4. each charge controller block controls the charging and discharging process of the respective match-line (ML). all MLs are pre-discharged to ground by the charging controller. 4. [64].

As charging to ML1 is slower than ML0. ML0 reaches about VDD/3 and MLC is low. The achieved voltage (~VDD/3) of ML0 is high enough to be sensed as a high level for the proposed sense amplifier (SA). this causes the gate of the transistor M3 to be low and charging to ML0 continues via M3. The end result is no more charging of ML through M3. 4. M6 becomes fully ON and M7 becomes partially ON. MLC is kept high until the voltage of ML0 is enough to turn M4 ON. As the voltage of match-line. 1: Structure of the CAM of the proposed scheme: (a) basic architecture and (b) NORtype TCAM cell used in the scheme. 38    . the matchline which has one miss is denoted by ML1 and this ML is hardest to detect as a miss. there is no discharging path through the CAM cell. charging to the fully matched match-line (denoted by ML0) is faster than the partially matched match-line. then. Fig. the voltage of ML1 is not enough to be sensed as a high level by the SA. Now. So.If the CAM cell data of this ML is fully matched with the search-line data.

During the evaluation stage. As the voltage of ML0 rises up to 0.18µm CMOS process with the supply voltage of 1.65V and MLC is low.1 shows the comparative search energy and performance among the schemes. 4. Fig. the node SN begins to discharge and MLS begins to rise.8V.3 shows the proposed sense amplifier (SA). degrades through the discharging path. MLP is switched to low and MLC is switched to high for 0. Then. The SA senses this voltage as a miss and results a low MLS1. As MLS reaches high level.3 SIMULATION RESULTS AND ANALYSIS  The proposed scheme along with current-race and current-saving schemes are simulated using HSpice in the same 64 × 72 TCAM for TSMC 0. the node SN is precharged to high through MS1. On the other hand. the transistor MS3 turns ON resulting in faster discharge of node SN. even for a large process variation. the transistor MS2 turns ON. At the beginning of a search cycle. our scheme will produce the correct search results. Table 4. During precharge stage.46V and then. So. Transistor MS4 is used to initialize the output MLS to ground at the beginning of each search cycle.39 ns so that previously charged MLs can discharge to ground.Fig. As the difference between the maximum ML0 and ML1 (worst-case match-line) is 190 mV. 39    . when the voltage of ML is slightly above VDD/3. The proposed sense amplifier senses this voltage as a match and output MLS0 turns to a full high level.4 shows the simulation result for our design. the voltage of the ML1 rises up to 0. 4. It shows that ML energy reduction is 57% and 54% compared to the current-race and currentsaving schemes respectively and the speed is 3. 4. 2: Internal circuit of the charging controller. Fig. the charging is stopped and the voltage of ML0 remains unchanged.33ns.13 times that of the both schemes. MLP is high for 0. 4.

So. this scheme reduces a large amount of dynamic and leakage power. whereas the previous SAs use ~1V as a switching voltage. As a result. the equivalent resistance is half of the previous schemes. So.6 V as a high level. speed of the circuit increases.The major difference between previous schemes [64]-[66] and our scheme is that we have used only one PMOS for charging the ML while previous schemes use two PMOS in series. So. the proposed scheme need not further charging after 0. 3: Proposed sense amplifier (SA) 40    .6V (equals to VDD/3) at ML0 is achieved. Equivalent capacitance is also reduced. The proposed SA can sense a stable 0. The basic difference between previous SA design [64]-[66] and the proposed SA is the switching threshold of SA. 4. while a larger voltage swing of about VDD/2 in [64]-[66] causes a higher power consumption. MLP   MS1 MLS SN ML MS2 MS3 MS4 MLP Fig.

+5% VDD and at a temperature of 273 K as well as in the slow process (SLH) corner with +10% threshold votlage.65 0. 1: Comparison of Different Schemes Schemes Current-race [64] Current-saving [65]. 4: Simulation results of the proposed CAM showing voltages ML0 (fully matched). MLC and MLP.4 CORNER SIMULATION OF THE SCHEME    To test the reliability of the proposed scheme. The simulation results are shown in Fig. high VDD and low temperature (FHL) and the slow process corner with high threshold voltage. 1/T time.Fig.32 1. Table 4. we have simulated the proposed scheme in two extreme corners which we defined as follows: the fast corner with low threshold voltage.62 Minimum Cycle Speed. ML1 (one-bit miss). 4.65 0. ML2 (two-bit miss). -5% VDD and at a temperature of 343 K.60 1.15 278 278 870 4.6. 4.[66] This work ML Energy (fJ/bit/ search) 3. T (MHz) (ns) 3. Simulation results reveal that the proposed scheme works satisfactorily in the fast process (FHL) corner with -10% threshold votlage.5 and Fig.53 SL Energy (fJ/bit/ search) 0. 4.60 3.56 3. low VDD and high temperature (SLH). 41    .

6: Corner Simulation results for SLH (when threshold voltage= +10%. 4. 4.VDD=+5%. 5: Corner Simulation results for FHL (when threshold voltage= -10%.5 CONCLUSION  This work present a novel CAM scheme in which ML energy reduces by over 50% compared to previous current-race and current-saving schemes while the speed increases by over 3 times.Fig. 42    . and temparature=273K)   Fig. and temparature=343K)   4.VDD=-5%.

  CHAPTER 5  PROPOSED SIMPLIFIED DESIGN OF  CHARGING CONTROLLER       43    .

especially in the field of network routing applications. current-race scheme [81]. A number of techniques at the circuit level has been proposed in the past for reducing the power consumption in high-perfromance CAM arrays. The current-race scheme limits the ML voltage swing by VDD/2 and pre-discharge the MLs to ground instead of precharging to VDD. consisting of an array of storage CAM cells. As the applications and usges of CAM continue to expand. The search data is sent to the search-lines (SLs) and compared bitwise with the stored word in the storage CAM cells. the match-lines (MLs) are precharged to high and the search-lines are precharged to ground [76]. Hough Transformation [73]. The current-saving scheme is the improved version of current-race scheme which allocates less power to match decision involving a large number 44    . CAM is used extensively in applications such as network address translation. etc. [71]. the CAM array size as well as the total power consumption is becoming larger. When the search data do not resemble the stored data. these include low-swing schemes [78]-[79]. as SL is not precharged. parametric curve extraction [72]. the main focus in the design of CAM arrays has been given to the reduction of the power consumption while at the same time increasing the speed of search without sacrificing the robustness [75]. pattern recognition.CHAPTER 5 PROPOSED SIMPLIFIED DESIGN OF CHARGING CONTROLLER     5. and a column of sense amplifiers. selective precharge scheme [80].1 shows the simplified block diagram of a conventional CAM architecture. compared to the precharge-high scheme [76]. [77].1 INTRODUCTION    Content-addressable memory (CAM) is a storage device that searches for the matching data by content and returns the address at which the matching data was found [70]. The selective precharge scheme reduces ML power consumption by breaking the search into two segments and observing that the second segment is rarely activated. there is a 50% reduction in SL power consumption [75]. [77]. a search data register. In the current-race scheme. only the matched MLs remain high and only one or a few rows of stored words match with the search data. Fig. The low-swing scheme reduces the ML power by reducing the ML swing voltage. a significant amount of power is consumed in discharging and charging the large number of MLs in CAM arrays. Conventionally. image coding [74]. the precharged MLs are discharged. Hence. Since. and current-saving schemes [82]. [83]. 5.

So. we have selected the current-race and current-saving schemes as the baselines. This sensing unit can sense a stable voltage of about VDD/3 as a high and provide the match decision. This sensing unit is proposed by the same authors in [84]. to compare our proposed scheme with existing ones. [80]. During the evaluation stage. the MLs are charged towards VDD until the voltage of the fully matched ML approaches the sense threshold voltage of the sensing unit. we propose a new ML charging technique where the MLs are predischarged to ground at the beginning of each search cycle. 1: Simplified conventional CAM architecture In this work. 51. To speed up the charging and discharging process of MLs. we use only one PMOS and one NMOS device while previous schemes [81]-[83] use two PMOS devices for charging each match-line.8% reduction compared to the current-saving scheme.of mismatched bits. 5. a large amount of dynamic as well as leakage power is saved. [81]. It is reported in a survey [75] that the current-saving scheme consumes less power than other schemes [76]. and 68% reduction in minimum cycle time. Section III presents the simulation results and analysis along with comparison among different schemes. The overall effect of the proposed scheme is a 55% ML power reduction compared to the current-race scheme. Fig. The remainder of this work is organized as follows: section II describes the operation of our proposed scheme in details. 45    . Section IV provides the conclusion. As the voltage swing of ML is limited to about VDD/3.

has no path to ground.2 PROPOSED ML CHARGING TECHNIQUE     Fig. Fig. MLC is switched to low to begin the charging of the MLs. For the partially matched MLs. MLC is kept high. As the fully matched ML. The outputs MLS0. Hence. We have used NOR-type Ternary CAM (TCAM) cell in our study. If there is a match in one or more MLs. NOR-type cell provides a full rail voltage at the gates of all comparison transistors [75].5. Number of discharging path is equal to the number of mismatches. before the MLC control signal is switched to high. MLS1 etc. the voltage of the MLs will degrade due to the discharge through one or more discharging paths. 46    . since enabling pull-down path in the NOR cell does not interfere with ML precharge [71]. the ML has no discharging path to ground. all the MLs are reset to ground by the charging unit of “charging and sensing block”. The array of CAM cells stores the data words and the search data register stores the word to be searched.2(a) shows the architecture of a CAM array using the proposed ML charging technique. Another disadvantage of NAND-type cell is that it needs unacceptably long search time that increases quadratically with the number of TCAM cells in series [83]. the ML has a conducting path to ground. This reset technique of ML eliminates the need for SL reset. as there is no path to discharge for the fully matched MLs other than small leakage current. only for the fully matched MLs. the search data register broadcasts the search data to the SLs. the voltage of those MLs will remain almost at the same voltage when MLC was switched to high. At the beginning of each search cycle.2(b) shows the internal circuit of a NOR-type Ternary CAM (TCAM) cell. If SL resembles stored bit D or the stored bit is X (don’t care). then the voltage of those matched MLs will be high enough to turn ON the transistor M3 in the sensing unit. Each ML has its own “charging and sensing block” which has a charging and sensing unit. The charging unit controls the charging and discharging of MLs. 5. At the beginning of search cycle. the transistor M3 will be ON. each ML is reset to ground by a high MLP through transistor M1. at this stage. 5. NOR-type is preferred over NAND-type because of the its less susceptibility to failure due to the variation of process. where all the CAM cells connected to it have a match. During the evaluation stage. After the precharge stage is complete. other MLs which have at least one mismatch will not rise to the extent to turn the transistor M3 ON. also. [81]. 5. The charging unit allows all the MLs to charge for a period determined by the time it takes the ML voltage of a matched ML to reach sensing threshold of the sensing unit. the sensing unit senses the ML voltage and generates the final full-swing output in case of a match. Fig. it is charged at a higher rate than the MLs that have at least one miss. If SL does not match D.3 shows the ML charging unit proposed in this work and the sensing unit proposed by the same authors in [84]. temperature and supply voltage [85]. of sensing unit turn to high for matched MLs and remain low for missed MLs. there will be a discharging path to ground through that CAM cell. As the charging of the miss-matched MLs is slower than the fully matched ML. If there is at least one miss among all the CAM cells connected to each ML.

3: The ML charging unit proposed in this work and the sensing unit proposed in [84].Fig. 5.   Fig. 47    . 2: Structure of the CAM array with the proposed scheme: (a) the basic architecture and (b) internal circuit of the NOR-type TCAM cell used in this scheme. 5. Here the usual SRAM access transistor and associated bitlines are omitted for simplicity.

67 V to enable the turning ON of the transistor M3. the feedback circuit consisting of the inverter and transistor M5 is used to speed up the sensing faster. 5. Transistor M6 is used for predischarging the output node MLS of the sensing unit to ground before the start of the evaluation stage.18µm technology with a 1.3 SIMULATION RESULTS AND ANALYSIS    The operation of the proposed CAM is verified by performing HSpice simulations based on TSMC 0. ML1 (one-bit miss).4 shows the simulation result of the proposed design.   48    . both MLP and MLC are set to high so that previously charged MLs can reset to ground. 5. which is hardest to detect as a miss) is not high enough to turn the transistor M3 ON resulting in same low voltage at the output node MLS1. the sensing unit senses this voltage as a match and generates a full swing output voltage at MLS0. Fig. Fig. The voltage of the matchline ML1 (only one bit mismatched ML.In the sensing unit shown in Fig. The size of the CAM array is 64 × 72 bit. 4: Simulation results of the proposed CAM showing voltages ML0 (fully matched). 5. MLC is kept low for a period enough to charge the fully matched ML (ML0) to 0. ML2 (two-bit miss). At this point. The evaluation stage starts with the switching of both MLP and MLC to low. MLC is switched to high and the voltage of the fully matched ML (ML0) continues to maintain its value.8V supply voltage. 5.3. At the beginning of a search cycle. MLC and MLP.

as the number of the transistors in charging unit of the proposed scheme is less than that in the existing schemes. this scheme results in reduced power consumption.[83] This work ML Energy (fJ/bit/search) 3. 49    .60 1. The cross-talk noise on MLs from neighboring signals needs to be minimized or eliminated using proper shielding and adequate spacing. Table 5. sense amplifiers of the existing scheme requires a higher sense voltage of at about 1V. The major difference between existing schemes [81]-[83] and our scheme is that we have used only one PMOS device for charging the MLs while existing schemes use two PMOS devices in series. Due to the reduced sensing sense threshold voltage and lower voltage swing of MLs. The sensing unit [16] used in the simulation also contributed to the reduced power consumption.8% compared to the current-saving scheme and 55% compared to the current-race scheme. the circuit will work properly even in presence of supply noise. While the SL energy remains almost same.15 For the comparison of the proposed scheme with two other existing schemes (currentrace and current-saving).65 0.07V.67V as a high input whereas using the similar setup. With respect to variation in supply voltage (VDD). 1: Comparison of Different Schemes Scheme Current-race [81] Current-saving [82].13 times the speed of the other two schemes (278MHz).60 SL Energy (fJ/bit/search) 0. The difference between the maximum voltage to which ML0 and ML1 (hardest to detect as a miss) reach during evaluation.56 3. less silicon area will be required to implement the unit CAM arrays. The match-line energy reduction is 51. This sensing unit can sense about 0.67V to 2.32 1.65 0. So. Also. the MLs need to be protected against other sources of noise. the speed of operation is 870 MHz which is 3. resulting in half the equivalent resistance and increased speed of operation.1 shows the comparative performance and energy per bit per search for these schemes. However. For the proposed technique. this voltage is large enough to guard against any failure due to process variations. an up-noise of over 180 mV on ML1 or a down-noise of over 180 mV will cause wrong values to be sensed by the sense amplifier. the proposed scheme is found to be functional while VDD is varied from 1.60 3. we simulated all three schemes with the same CMOS process using the same basic NOR type TCAM cell in the same 64 × 72 CAM block.Table 5.62 Minimum Cycle time (ns) 3. is about 180mV. the reduction in the minimum cycle time of operation of the proposed scheme is 68% compared to the both schemes.

5. To speed up the charging process. The results are compared with the existing current-race and current-saving schemes using the same technology.performance technique for charging match-lines for content-addressable memory arrays.4 CONCLUSION  In this work. The results show that the match-line energy reduces by 51.18µm CMOS process. The proposed scheme was simulated using HSpice in a 64 × 72 TCAM for TSMC 0.   50    . we have proposed a low-power and high. we have used only one PMOS device to charge up the match-lines and one NMOS device to reset them.8% and the minimum cycle time reduces by 68% compared to those schemes.

  CHAPTER 6  PROPOSED CAM WITH IMPROVED  NOISE MARGIN      51    .

1 INTRODUCTION    As Content Addressable Memory (CAM) is based on dynamic logic. speed and power consumption remains low as previous. the match-line which has faster charging rate. The match-line which has lower probability to be matched match-line is no longer charged. the circuit will automatic charge those match-lines at the third state. As the matched matchline is charged to VDD.2 OPERATION OF THE SCHEME    The main structure of the CAM array is like the charging controller scheme. In spite of the increase of noise immunity. Maintaining good immunity to noise.) i. so ML is the worst node regarding noise. The principle of the new proposed charging controller is that “Carry coal to Newcastle”. 52    . This saves a large amount of power. The conventional sense amplifier is used to sense the match line voltage. The match-lines which has probability of being matched match-line (may be fully matched match-line in most of case or one miss-match-line if sufficient noise is added. an improved circuit of charging controller is used.e. design of high speed and low-power CAM is the main purpose of this research. there is large difference of the voltages between fully matched matchline and 1-bit-missed matchline. Here.CHAPTER 6 PROPOSED CAM WITH IMPROVED NOISE MARGIN     6. 6. it is more prone to be noise affected. so noise margin is high. The dynamic node Match-line (ML) of CAM is so long and may remain floating.

6.1 Charging controller     Fig.2 shows the internal circuitry of the proposed charging controller. 6.     6. Fig. The total operation can be segmented into three phases or stages of time. 6.Fig. 2: Internal circuitry of improved Charging   53    . 1: Structure of the CAM array.2.

after the second stage. the transistor M1 and M7 is ON.3). So the charging to the respective matchline will continue. ML is precharged by high MLP. 6. For partially matched matchline.Fig. 6. So the gate of M2 will gradually get a low. To gain the high threshold switch. all the match-line is charged. At 2nd stage.. rd 6. 6. This high will go through M5 transistor.2. At 3rd stage. This voltage is enough to make ON the transistor M3. the voltage of the matchline is higher than any other matchline. charging is stopped. A high MLC is applied to gate of M6. 54    . At this time. The strength of the transistor M3 is make higher than M3 so that switching threshold of the inverter like part remain lower. so it becomes ON and the gate of M2 is low.4. the strength of the keeper transistor is made higher than NMOS transistor.8V).2 The sense amplifier    This scheme uses the conventional sense amplifier as shown in Fig. For fully-matched matchline (as ML00 in Fig. So the gate of M2 is high and it is OFF so that the match-lines cannot be charged in this time. One or two match-lines are charged up to VDD (1. the charging will be stopped just after the starting of 3 stage due to a high given by the output of transistor M4. 3: Waveforms for CAM   At 1st stage. in most of match-line (miss-match line).

6.5 shows the input signals such as MLC and MLP and output MLS00 (output of the matchline which is fully matched) and MLS01 (output of the matchline which is partially matched. 4: Conventional sense amplifier.Fig. 6. 6.3 SIMULATION RESULT    Fig. 55    .4 shows the simulation result which shows the two cycles of charging of different matchlines. Fig.. 5: Charging in different match-lines. 6. 6.) MLS00  ML00  ML01  ML02  MLS01  Fig.

if the charging continues. we simulated all three schemes with the same CMOS process using 56    .65 0.[83] This work ML Energy (fJ/bit/search) 3. a large noise is should added in the matchline. 6. For process variation.60 1.32 1. we can assume that the match-line which has only one mismatch may be able to make ON the transistor M3.56 3. Table 6.60 3. the voltage of the match-line will not be so large that can be sensed by the sense amplifier whose sensing threshold is higher. 1: Comparison of Different Schemes with improved noise margin scheme Scheme Current-race [81] Current-saving [82]. To result in error in the circuit. 6: Controlled signals and output of each match-line.15 For the comparison of the proposed scheme with two other existing schemes (currentrace and current-saving).87 SL Energy (fJ/bit/search) 0. As we can see that the difference between the voltage of ML0 and ML1 is high.MLP  MLC  MLS00  MLS01  Fig.95 Minimum Cycle time (ns) 3.65 0. So the noise immunity is quite better in this circuit. For that reason.

1 shows the comparative performance and energy per bit per search for these schemes. Table 6.4 CONCLUSION    The scheme shown in this Chapteris quite noise insensitive.5% compared to the current-race scheme. For the proposed technique. We think that this scheme would be practically implementable and usable.the same basic NOR type TCAM cell in the same 64 × 72 CAM block. This scheme reduces the power consumption by a large extent. the speed of operation is 870 MHz which is 3.2 shows the comparison of noise immunity and noise immunity which shows the scheme of this chapter provides good noise immunity.13 times the speed of the other two schemes (278MHz).6% compared to the current-saving scheme and 47. The match-line energy reduction is 43. the reduction in the minimum cycle time of operation of the proposed scheme is 68% compared to the both schemes. 57    . While the SL energy remains almost same. Table 6. The speed of the operation is also high as the previously proposed schemes. Table 6. 2: Comparison of Noise Immunity of different schemes Scheme Noise Immunity Conventional Current race Current saving Charging control scheme Low noise scheme charging controller Good(+) + ++ + -Scheme simplicity 6.

  CHAPTER 7  CONCLUSION      58    .

With the advancement of process technology. and 54% compared to the current-saving scheme 7. Noise is an important factor in CAM circuitry analysis. There are several types 59    . Previous schemes follow different techniques to reduce the match line (ML) and search line (SL) power consumption. [89] use two PMOSs to charge match-line. we use only one PMOS and one NMOS with full low and full high (when they are active) at the gate respectively where previous schemes [87]. the immunity of a system of gates usually differs from that of any individual gate. supply voltage. fan-in and fan-out.2 Future Work    We didn’t analyze the noise immunity of our scheme. this parameter being governed by the word length used in today’s computer systems. and temperature. [88]. The match operation of high-performance CAM array is also performed with domino gates. 1 Conclusion    CAMS are most often encountered as cache memories in computer systems but they are also starting to be used in applications such as database retrieval. shape of the noise signal. the leakage current in transistors continues to rise. thus a generalized analysis of the noise immunity of a logic circuit becomes a very complex process when one takes all the above parameters into consideration. The performance and area advantages of dynamic gates come at a cost of higher power and lower noise robustness. Moreover. To speed up the charging and discharging process.Chapter 7 Conclusion 7. The width of the patterns stored in these CAMs usually varies between 32 and 64 bits. The immunity of a CMOS logic gate to noise signals is a function of many variables. such as individual chip differences. stray inductance and capacitance. parallel arithmetic algorithms and string processing. In this dissertation several methods and techniques are presented to design low-power and High Speed CAM circuits used in cache memory. worsening the total power and noise immunity in CAM circuits. The overall effect of this scheme is a 57% ML power reduction compared to the current-race scheme. location of the noise.

propagated noise at the inputs. charge leakage. and Bobba’s technique.                                           60    . We will design the layout of our scheme in next future and fabricate it. Twin-transistor technique. So.of noise that can destroy the stored value. D’Souza’s method: PMOS transistor pullup. The major noises sources in electronic circuit are Crosstalk noise. For chip fabrication purpose layout design is necessary. Mirror technique. There are so many techniques to reduce the effect of noise such as Covino’s or inverter technique. Chip fabrication is our next concern. Charge-sharing noise. power supply noise. and process variations.

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3rd Edition. 3rd Edition. Nikolic. A. ©2005. 69    . D. Inc. 2002. NJ. Eshraghian. K. Upper Saddle River. D.  N.  Rabaey. Digital  Integrated  Circuits:  A  Design  Perspective. ©1994. Prentice Hall.  Chandrakasan and B.  A. Weste. Pearson Education. Banerjee. CMOS VLSI DESIGN: A Circuits and Systems Perspective. Pucknell. Harris.. Basic VLSI Design. A.Bibliography    [1] [2] [3]                                           J.

Md. N. Rashid. Tsukuba science city. and Ataur R. Md. Mehedi Hasan.RESEARCH PAPERS FROM THIS THESIS     1. Mehedi Hasan. Tauhidur Rahman. Ibaraki. Hasan.B. Japan. T. H. H. “A Novel Match-line Charging Control Scheme with a New Sense Amplifier for High-Speed and Low-Power Content-Addressable Memory”. A.                           70    . Md. Rahman. A. 2. accepted in TENCON 2008. Patwary. Patwary. “A High-Speed and Low-Power Design of ContentAddressable Memory Using a Novel Match-line Charging Technique”. Rashid.M. Md. 2008 International Conference on Solid State Devices and Materials (SSDM 2008). Md.M. Naimul Hasan. Hyderabad. and Ataur R.B. Md.

INCLUDE 'MEAS_MCAM32.INCLUDE 'vmlv64.3N 0V VMLPB MLPB 0 PWL 0 0V.80V.INCLUDE 'ML_GOF4_4...56N 1..8V.txt' $2ND 4 X 72 CAM CELL BLOCK . ML_GOF4_2=MATCH LINE_ GROUP OF 4_2 .8V.54N 0V.txt' .INCLUDE 'ML_GOF4_10.txt' .65V *MEASURE THE SL AND ML POWER .15N 0V.TXT' * VCC AND PRECHARGE VOLTAGES VDD 1 0 DC 1.1.8V.1.15N 1.g.87N 1.INCLUDE 'ML_GOF4_8. E.08N 1.1 HSpice code for Charging control scheme File: mcam64_72ssdm.56N 0V.1.INCLUDE 'mcamxmlcs64.txt' ...08N 0V.41N 1.1.1.. ML_GOF4_1=MATCH LINE_ GROUP OF 4_1 .txt' $FIRST 4 X 72 CAM CELL BLOCK .80V.54N 0V..41N 1.1.sp TCAM Circuit .49N 0V.INCLUDE 'MYMLSA.txt' .1.72N 1.INCLUDE 'ML_GOF4_2.INCLUDE 'mcamxsa64.39N 1.1.17N 0V.54N 1.39N 0V.2.2.89N 0V.txt' *SENSE AMPLIFIER BLOCK ..1.39N 0V.INCLUDE 'ML_GOF4_1.8V.30N 0V VMLP MLP 0 PWL 0 1. 1.2.56N 1.txt' .80V.02N 0V. MLV00 is to charge matchline ML00 .0.INCLUDE 'MYMLCS.1.8V.8V *Voltage sources to charge matchlines .80V VSLDE SLDE 0 PWL 0 1.8V.8V.txt' ..8V.8V.8V.3N 1.IC V(MLV00)=0.TXT' ..INCLUDE 'ML_GOF4_9.15N 0V.3N 1.30N UIC .INCLUDE 'ML_GOF4_5.txt' .34N 0V.INCLUDE 'ML_GOF4_3.8V.41N 0V.8V.INCLUDE 'ML_GOF4_11.1.8V VMLC MLC 0 PWL 0 0V. 1.1.INCLUDE 'ML_GOF4_7.74N 0V.txt' *MATCHLINE PRECHARGE & CHARGE CONTROLLER BLOCKS .36N 1.TXT' $ML CHARGE CONTROLLER BLOCK .APPENDIX A SIMULATION CODE A.txt' 71    .15N 1..2.txt' .1.1.txt' *** MATCH LINE CAM CELL TOGETHER 4 LINE .1.51N 1.TRAN 20P 2.INCLUDE 'ML_GOF4_6.

INCLUDE 'WORD10M2.TXT' .INCLUDE 'WORD10M12.INCLUDE 'WORD10M16.TXT' .TXT' .TXT' .TXT' .INCLUDE 'WORD10M3.TXT' .TXT' $ 8 CAM CELL IN ROW WHERE 10101010 IS STORED *****WORD WITH MISS .INCLUDE 'TCAMX.END File: vmlv64.txt' .txt' .INCLUDE 'WORD10M6.8V VMLV02 MLV02 0 DC 1.txt' .INCLUDE 'WORD10M1.TXT' $16 CAM CELL IN A ROW WHERE 2 MISS TO DATA 1010101010101010 .txt' $SEARCH LINE DATA .INCLUDE 'BYTEX.INCLUDE 'ML_GOF4_15.INCLUDE 'BYTE10.TXT' .INCLUDE 'WORD10.TXT' $16 CAM CELL IN A ROW WHERE 1 MISS TO DATA 1010101010101010 .txt' .INCLUDE 'ML_GOF4_13.TXT' $DATA ENTER ENABLE NMOS *TCAMS .txt VMLV00 MLV00 0 DC 1.TXT' .INCLUDE 'WORD10M10.INCLUDE 'TCAM1..TXT' .TXT' .INCLUDE 'SLDET.INCLUDE 'SLD10.TXT' .TXT' .TXT' .TXT' .INCLUDE 'WORD10M13.lib' .INCLUDE 'WORD10M7.8V VMLV03 MLV03 0 DC 1.TXT' .INCLUDE 'TCAM0.8 72    .INCLUDE 'WORD10M14.INCLUDE 'WORD10M11.INCLUDE 'ML_GOF4_16.INCLUDE 'WORD10M5.INCLUDE 'WORD10M4.INCLUDE 'WORD10M8.TXT' .INCLUDE 'WORD10M15.TXT' *WORD =X .txt' *MODEL .TXT' $ TERNARY CAM WHERE 0 IS STORED $ TERNARY CAM WHERE 1 IS STORED $ TERNARY CAM WHERE X IS STORED $ 16 CAM CELL IN A ROW WHERE X IS STORED $ 8 CAM CELL IN ROW WHERE X IS STORED *WORD= 1010101010101010 & BYTE=10101010 .INCLUDE 'tsmc018.8V VMLV01 MLV01 0 DC 1.INCLUDE 'ML_GOF4_14.TXT' $ 16 CAM CELL IN A ROW WHERE 1010101010101010 IS STORED .TXT' .8V VMLV04 MLV04 0 DC 1.INCLUDE 'WORD10M9.INCLUDE 'ML_GOF4_12.INCLUDE 'WORDX.8 VMLV06 MLV06 0 DC 1.INCLUDE 'BYTE10M8.txt' .8 VMLV07 MLV07 0 DC 1.8 VMLV05 MLV05 0 DC 1.

8 VMLV52 MLV52 0 DC 1.8 VMLV34 MLV34 0 DC 1.8V VMLV42 MLV42 0 DC 1.8 VMLV46 MLV46 0 DC 1.8V VMLV43 MLV43 0 DC 1.8 VMLV45 MLV45 0 DC 1.8 VMLV39 MLV39 0 DC 1.8 VMLV58 MLV58 0 DC 1.8 VMLV33 MLV33 0 DC 1.8 VMLV15 MLV15 0 DC 1.8 VMLV29 MLV29 0 DC 1.8V VMLV61 MLV61 0 DC 1.8 VMLV27 MLV27 0 DC 1.8V VMLV44 MLV44 0 DC 1.8 VMLV17 MLV17 0 DC 1.8 VMLV53 MLV53 0 DC 1.8 VMLV35 MLV35 0 DC 1.8 VMLV48 MLV48 0 DC 1.8 VMLV38 MLV38 0 DC 1.8 VMLV47 MLV47 0 DC 1.8 VMLV13 MLV13 0 DC 1.8 VMLV18 MLV18 0 DC 1.8 VMLV36 MLV36 0 DC 1.8 VMLV57 MLV57 0 DC 1.8 VMLV26 MLV26 0 DC 1.8V VMLV24 MLV24 0 DC 1.8 VMLV25 MLV25 0 DC 1.8 VMLV54 MLV54 0 DC 1.8 VMLV51 MLV51 0 DC 1.8 VMLV31 MLV31 0 DC 1.8 VMLV59 MLV59 0 DC 1.8 VMLV56 MLV56 0 DC 1.8 VMLV14 MLV14 0 DC 1.8V VMLV41 MLV41 0 DC 1.8 VMLV28 MLV28 0 DC 1.8V VMLV23 MLV23 0 DC 1.8 VMLV20 MLV20 0 DC 1.8 VMLV11 MLV11 0 DC 1.8 VMLV32 MLV32 0 DC 1.8 VMLV40 MLV40 0 DC 1.8 VMLV60 MLV60 0 DC 1.8 VMLV10 MLV10 0 DC 1.8 VMLV49 MLV49 0 DC 1.8V VMLV21 MLV21 0 DC 1.8 VMLV12 MLV12 0 DC 1.8 VMLV16 MLV16 0 DC 1.8 VMLV37 MLV37 0 DC 1.VMLV08 MLV08 0 DC 1.8V VMLV22 MLV22 0 DC 1.8 VMLV50 MLV50 0 DC 1.8 VMLV09 MLV09 0 DC 1.8 VMLV30 MLV30 0 DC 1.8V 73    .8 VMLV19 MLV19 0 DC 1.8 VMLV55 MLV55 0 DC 1.

18U W = 0.18U W = 0.txt XMLCS00 1 MLC MLPB MLP MLV00 ML00 MYMLCS $FOR ML00 XMLCS01 1 MLC MLPB MLP MLV01 ML01 MYMLCS $FOR ML01 XMLCS02 1 MLC MLPB MLP MLV02 ML02 MYMLCS XMLCS03 1 MLC MLPB MLP MLV03 ML03 MYMLCS XMLCS04 1 MLC MLPB MLP MLV04 ML04 MYMLCS XMLCS05 1 MLC MLPB MLP MLV05 ML05 MYMLCS XMLCS06 1 MLC MLPB MLP MLV06 ML06 MYMLCS XMLCS07 1 MLC MLPB MLP MLV07 ML07 MYMLCS XMLCS08 1 MLC MLPB MLP MLV08 ML08 MYMLCS XMLCS09 1 MLC MLPB MLP MLV09 ML09 MYMLCS XMLCS10 1 MLC MLPB MLP MLV10 ML10 MYMLCS XMLCS11 1 MLC MLPB MLP MLV11 ML11 MYMLCS XMLCS12 1 MLC MLPB MLP MLV12 ML12 MYMLCS XMLCS13 1 MLC MLPB MLP MLV13 ML13 MYMLCS XMLCS14 1 MLC MLPB MLP MLV14 ML14 MYMLCS XMLCS15 1 MLC MLPB MLP MLV15 ML15 MYMLCS XMLCS16 1 MLC MLPB MLP MLV16 ML16 MYMLCS XMLCS17 1 MLC MLPB MLP MLV17 ML17 MYMLCS XMLCS18 1 MLC MLPB MLP MLV18 ML18 MYMLCS XMLCS19 1 MLC MLPB MLP MLV19 ML19 MYMLCS XMLCS20 1 MLC MLPB MLP MLV20 ML20 MYMLCS XMLCS21 1 MLC MLPB MLP MLV21 ML21 MYMLCS XMLCS22 1 MLC MLPB MLP MLV22 ML22 MYMLCS XMLCS23 1 MLC MLPB MLP MLV23 ML23 MYMLCS XMLCS24 1 MLC MLPB MLP MLV24 ML24 MYMLCS XMLCS25 1 MLC MLPB MLP MLV25 ML25 MYMLCS XMLCS26 1 MLC MLPB MLP MLV26 ML26 MYMLCS XMLCS27 1 MLC MLPB MLP MLV27 ML27 MYMLCS XMLCS28 1 MLC MLPB MLP MLV28 ML28 MYMLCS XMLCS29 1 MLC MLPB MLP MLV29 ML29 MYMLCS XMLCS30 1 MLC MLPB MLP MLV30 ML30 MYMLCS XMLCS31 1 MLC MLPB MLP MLV31 ML31 MYMLCS XMLCS32 1 MLC MLPB MLP MLV32 ML32 MYMLCS 74    .54U *MATCHLINE CURRENT SAVING MML1 ML MLCD MLV MLV cmosp L =0.8V VMLV63 MLV63 0 DC 1.18U W = 0.63U .18U W = 0.txt .18U W = 0.27U MML4 MLCD MLC 0 0 cmosn L =0.VMLV62 MLV62 0 DC 1.SUBCKT MYMLCS 1 MLC MLPB MLP MLV ML *MATCHLINE PRECHARGE TRANSISTOR MMLP ML MLP 0 0 cmosn L =0.8V File: MYMLCS.18U W = 0.63U MML2 MLCD MLPB MLP 1 cmosp L =0.18U W = 0.63U MML3 MLCD ML 0 0 cmosn L =0.27U MML5 MLCD MLC ML5S 1 cmosp L =0.ENDS MYMLCS File: mcamxmlcs64.63U MML6 ML5S ML 1 1 cmosp L =0.

18U W = .18U W = 0.27U .TXT XSA00 1 ML00 MLP MLPB MLSO00 MLSA XSA01 1 ML01 MLP MLPB MLSO01 MLSA 75    .ENDS INVTR .27U .TXT .XMLCS33 1 MLC MLPB MLP MLV33 ML33 MYMLCS XMLCS34 1 MLC MLPB MLP MLV34 ML34 MYMLCS XMLCS35 1 MLC MLPB MLP MLV35 ML35 MYMLCS XMLCS36 1 MLC MLPB MLP MLV36 ML36 MYMLCS XMLCS37 1 MLC MLPB MLP MLV37 ML37 MYMLCS XMLCS38 1 MLC MLPB MLP MLV38 ML38 MYMLCS XMLCS39 1 MLC MLPB MLP MLV49 ML39 MYMLCS XMLCS40 1 MLC MLPB MLP MLV40 ML40 MYMLCS XMLCS41 1 MLC MLPB MLP MLV41 ML41 MYMLCS XMLCS42 1 MLC MLPB MLP MLV42 ML42 MYMLCS XMLCS43 1 MLC MLPB MLP MLV43 ML43 MYMLCS XMLCS44 1 MLC MLPB MLP MLV44 ML44 MYMLCS XMLCS45 1 MLC MLPB MLP MLV45 ML45 MYMLCS XMLCS46 1 MLC MLPB MLP MLV46 ML46 MYMLCS XMLCS47 1 MLC MLPB MLP MLV47 ML47 MYMLCS XMLCS48 1 MLC MLPB MLP MLV48 ML48 MYMLCS XMLCS49 1 MLC MLPB MLP MLV49 ML49 MYMLCS XMLCS50 1 MLC MLPB MLP MLV50 ML50 MYMLCS XMLCS51 1 MLC MLPB MLP MLV51 ML51 MYMLCS XMLCS52 1 MLC MLPB MLP MLV52 ML52 MYMLCS XMLCS53 1 MLC MLPB MLP MLV53 ML53 MYMLCS XMLCS54 1 MLC MLPB MLP MLV54 ML54 MYMLCS XMLCS55 1 MLC MLPB MLP MLV55 ML55 MYMLCS XMLCS56 1 MLC MLPB MLP MLV56 ML56 MYMLCS XMLCS57 1 MLC MLPB MLP MLV57 ML57 MYMLCS XMLCS58 1 MLC MLPB MLP MLV58 ML58 MYMLCS XMLCS59 1 MLC MLPB MLP MLV59 ML59 MYMLCS XMLCS60 1 MLC MLPB MLP MLV60 ML60 MYMLCS XMLCS61 1 MLC MLPB MLP MLV61 ML61 MYMLCS XMLCS62 1 MLC MLPB MLP MLV62 ML62 MYMLCS XMLCS63 1 MLC MLPB MLP MLV63 ML63 MYMLCS MYMLSA.18U W = 0.36U MSA2 MSA1D MLPB 1 1 CMOSP L =0.63U MI2 OUT IN 0 0 CMOSN L =0.ENDS MLSA MCAMXSA64.SUBCKT INVTR VCC IN OUT MI1 OUT IN VCC VCC CMOSP L = 0.27U MSA4 MLSO MLP 0 0 CMOSN L =0.18U W = 0.18U W = 0.SUBCKT MLSA 1 ML MLP MLPB MLSO MSA1 MSA1D ML 0 0 CMOSN L =0.18U W = 0.63U XSA 1 MSA1D MLSO INVTR MSA3 MSA1D MLSO 0 0 CMOSN L =0.

XSA02 1 ML02 MLP MLPB MLSO02 MLSA XSA03 1 ML03 MLP MLPB MLSO03 MLSA XSA04 1 ML04 MLP MLPB MLSO04 MLSA XSA05 1 ML05 MLP MLPB MLSO05 MLSA XSA06 1 ML06 MLP MLPB MLSO06 MLSA XSA07 1 ML07 MLP MLPB MLSO07 MLSA XSA08 1 ML08 MLP MLPB MLSO08 MLSA XSA09 1 ML09 MLP MLPB MLSO09 MLSA XSA10 1 ML10 MLP MLPB MLSO10 MLSA XSA11 1 ML11 MLP MLPB MLSO11 MLSA XSA12 1 ML12 MLP MLPB MLSO12 MLSA XSA13 1 ML13 MLP MLPB MLSO13 MLSA XSA14 1 ML14 MLP MLPB MLSO14 MLSA XSA15 1 ML15 MLP MLPB MLSO15 MLSA XSA16 1 ML16 MLP MLPB MLSO16 MLSA XSA17 1 ML17 MLP MLPB MLSO17 MLSA XSA18 1 ML18 MLP MLPB MLSO18 MLSA XSA19 1 ML19 MLP MLPB MLSO19 MLSA XSA20 1 ML20 MLP MLPB MLSO20 MLSA XSA21 1 ML21 MLP MLPB MLSO21 MLSA XSA22 1 ML22 MLP MLPB MLSO22 MLSA XSA23 1 ML23 MLP MLPB MLSO23 MLSA XSA24 1 ML24 MLP MLPB MLSO24 MLSA XSA25 1 ML25 MLP MLPB MLSO25 MLSA XSA26 1 ML26 MLP MLPB MLSO26 MLSA XSA27 1 ML27 MLP MLPB MLSO27 MLSA XSA28 1 ML28 MLP MLPB MLSO28 MLSA XSA29 1 ML29 MLP MLPB MLSO29 MLSA XSA30 1 ML30 MLP MLPB MLSO30 MLSA XSA31 1 ML31 MLP MLPB MLSO31 MLSA XSA32 1 ML32 MLP MLPB MLSO32 MLSA XSA33 1 ML33 MLP MLPB MLSO33 MLSA XSA34 1 ML34 MLP MLPB MLSO34 MLSA XSA35 1 ML35 MLP MLPB MLSO35 MLSA XSA36 1 ML36 MLP MLPB MLSO36 MLSA XSA37 1 ML37 MLP MLPB MLSO37 MLSA XSA38 1 ML38 MLP MLPB MLSO38 MLSA XSA39 1 ML39 MLP MLPB MLSO39 MLSA XSA40 1 ML40 MLP MLPB MLSO40 MLSA XSA41 1 ML41 MLP MLPB MLSO41 MLSA XSA42 1 ML42 MLP MLPB MLSO42 MLSA XSA43 1 ML43 MLP MLPB MLSO43 MLSA XSA44 1 ML44 MLP MLPB MLSO44 MLSA XSA45 1 ML45 MLP MLPB MLSO45 MLSA XSA46 1 ML46 MLP MLPB MLSO46 MLSA XSA47 1 ML47 MLP MLPB MLSO47 MLSA XSA48 1 ML48 MLP MLPB MLSO48 MLSA XSA49 1 ML49 MLP MLPB MLSO49 MLSA XSA50 1 ML50 MLP MLPB MLSO50 MLSA XSA51 1 ML51 MLP MLPB MLSO51 MLSA XSA52 1 ML52 MLP MLPB MLSO52 MLSA XSA53 1 ML53 MLP MLPB MLSO53 MLSA XSA54 1 ML54 MLP MLPB MLSO54 MLSA XSA55 1 ML55 MLP MLPB MLSO55 MLSA 76    .

TXT XW001 1 ML00 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10 XW002 1 ML00 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW003 1 ML00 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW004 1 ML00 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW005 1 ML00 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW011 1 ML01 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10 XW012 1 ML01 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW013 1 ML01 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW014 1 ML01 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW015 1 ML01 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW021 1 ML02 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M1 77    .XSA56 1 ML56 MLP MLPB MLSO56 MLSA XSA57 1 ML57 MLP MLPB MLSO57 MLSA XSA58 1 ML58 MLP MLPB MLSO58 MLSA XSA59 1 ML59 MLP MLPB MLSO59 MLSA XSA60 1 ML60 MLP MLPB MLSO60 MLSA XSA61 1 ML61 MLP MLPB MLSO61 MLSA XSA62 1 ML62 MLP MLPB MLSO62 MLSA XSA63 1 ML63 MLP MLPB MLSO63 MLSA ML_GOF4_1.

TXT XW041 1 ML04 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M3 XW042 1 ML04 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW043 1 ML04 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW044 1 ML04 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW045 1 ML04 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 78    .XW022 1 ML02 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW023 1 ML02 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW024 1 ML02 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW025 1 ML02 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW031 1 ML03 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M2 XW032 1 ML03 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW033 1 ML03 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW034 1 ML03 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW035 1 ML03 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_2.

XW051 1 ML05 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M4 XW052 1 ML05 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW053 1 ML05 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW054 1 ML05 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW055 1 ML05 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW061 1 ML06 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M5 XW062 1 ML06 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW063 1 ML06 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW064 1 ML06 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW065 1 ML06 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW071 1 ML07 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M6 XW072 1 ML07 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW073 1 ML07 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW074 1 ML07 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 79    .

TXT XW081 1 ML08 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M7 XW082 1 ML08 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW083 1 ML08 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW084 1 ML08 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW085 1 ML08 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW091 1 ML09 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M8 XW092 1 ML09 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW093 1 ML09 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW094 1 ML09 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW095 1 ML09 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW101 1 ML10 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M9 XW102 1 ML10 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW103 1 ML10 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW104 1 ML10 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B 80    .XW075 1 ML07 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_3.

TXT XW121 1 ML12 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M11 XW122 1 ML12 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW123 1 ML12 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW124 1 ML12 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW125 1 ML12 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW131 1 ML13 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M12 XW132 1 ML13 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW133 1 ML13 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B 81    .+SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW105 1 ML10 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW111 1 ML11 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M10 XW112 1 ML11 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW113 1 ML11 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW114 1 ML11 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW115 1 ML11 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_4.

txt XW161 1 ML16 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M15 XW162 1 ML16 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 82    .+SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW134 1 ML13 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW135 1 ML13 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW141 1 ML14 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M13 XW142 1 ML14 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW143 1 ML14 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW144 1 ML14 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW145 1 ML14 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW151 1 ML15 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M14 XW152 1 ML15 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW153 1 ML15 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW154 1 ML15 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW155 1 ML15 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_5.

XW163 1 ML16 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW164 1 ML16 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW165 1 ML16 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW171 1 ML17 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW172 1 ML17 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW173 1 ML17 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW174 1 ML17 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW175 1 ML17 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW181 1 ML18 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW182 1 ML18 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M1 XW183 1 ML18 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW184 1 ML18 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW185 1 ML18 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW191 1 ML19 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW192 1 ML19 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M2 83    .

txt XW201 1 ML20 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW202 1 ML20 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M3 XW203 1 ML20 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW204 1 ML20 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW205 1 ML20 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW211 1 ML21 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW212 1 ML21 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M4 XW213 1 ML21 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW214 1 ML21 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW215 1 ML21 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW221 1 ML22 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 84    .XW193 1 ML19 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW194 1 ML19 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW195 1 ML19 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_6.

txt XW241 1 ML24 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW242 1 ML24 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M7 XW243 1 ML24 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW244 1 ML24 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW245 1 ML24 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW251 1 ML25 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B 85    .XW222 1 ML22 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M5 XW223 1 ML22 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW224 1 ML22 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW225 1 ML22 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW231 1 ML23 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW232 1 ML23 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M6 XW233 1 ML23 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW234 1 ML23 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW235 1 ML23 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_7.

+SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW252 1 ML25 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M8 XW253 1 ML25 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW254 1 ML25 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW255 1 ML25 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW261 1 ML26 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW262 1 ML26 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M9 XW263 1 ML26 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW264 1 ML26 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW265 1 ML26 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW271 1 ML27 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW272 1 ML27 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M10 XW273 1 ML27 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW274 1 ML27 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW275 1 ML27 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 86    .

ML_GOF4_8.txt XW281 1 ML28 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW282 1 ML28 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M11 XW283 1 ML28 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW284 1 ML28 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW285 1 ML28 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW291 1 ML29 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW292 1 ML29 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M11 XW293 1 ML29 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW294 1 ML29 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW295 1 ML29 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW301 1 ML30 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW302 1 ML30 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M12 XW303 1 ML30 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW304 1 ML30 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 87    .

XW305 1 ML30 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW311 1 ML31 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW312 1 ML31 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10M13 XW313 1 ML31 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW314 1 ML31 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW315 1 ML31 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_9.txt XW321 1 ML32 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW322 1 ML32 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW323 1 ML32 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW324 1 ML32 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW325 1 ML32 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW331 1 ML33 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW332 1 ML33 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW333 1 ML33 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW334 1 ML33 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B 88    .

+SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW335 1 ML33 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW341 1 ML34 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW342 1 ML34 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW343 1 ML34 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW344 1 ML34 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW345 1 ML34 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW351 1 ML35 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW352 1 ML35 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW353 1 ML35 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW354 1 ML35 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW355 1 ML35 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_10.txt XW361 1 ML36 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW362 1 ML36 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW363 1 ML36 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 89    .

XW364 1 ML36 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW365 1 ML36 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW371 1 ML37 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW372 1 ML37 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW373 1 ML37 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW374 1 ML37 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW375 1 ML37 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW381 1 ML38 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW382 1 ML38 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW383 1 ML38 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW384 1 ML38 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW385 1 ML38 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW391 1 ML39 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW392 1 ML39 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 90    .

XW393 1 ML39 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW394 1 ML39 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW395 1 ML39 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_11.txt XW401 1 ML40 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW402 1 ML40 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW403 1 ML40 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW404 1 ML40 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW405 1 ML40 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW411 1 ML41 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW412 1 ML41 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW413 1 ML41 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW414 1 ML41 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW415 1 ML41 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW421 1 ML42 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 91    .

XW422 1 ML42 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW423 1 ML42 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW424 1 ML42 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW425 1 ML42 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW431 1 ML43 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW432 1 ML43 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW433 1 ML43 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW434 1 ML43 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW435 1 ML43 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_12.txt XW441 1 ML44 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW442 1 ML44 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW443 1 ML44 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW444 1 ML44 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW445 1 ML44 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW451 1 ML45 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B 92    .

+SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW452 1 ML45 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW453 1 ML45 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW454 1 ML45 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW455 1 ML45 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW461 1 ML47 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW462 1 ML47 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW463 1 ML47 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW464 1 ML47 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW465 1 ML47 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW471 1 ML47 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW472 1 ML47 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW473 1 ML47 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW474 1 ML47 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW475 1 ML47 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_13.txt 93    .

XW481 1 ML48 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW482 1 ML48 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW483 1 ML48 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW484 1 ML48 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW485 1 ML48 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW491 1 ML49 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW492 1 ML49 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW493 1 ML49 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW494 1 ML49 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW495 1 ML49 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW501 1 ML50 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW502 1 ML50 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW503 1 ML50 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW504 1 ML50 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW505 1 ML50 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 94    .

XW511 1 ML51 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW512 1 ML51 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW513 1 ML51 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW514 1 ML51 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW515 1 ML51 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_14.txt XW521 1 ML52 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW522 1 ML52 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW523 1 ML52 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW524 1 ML52 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW525 1 ML52 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW531 1 ML53 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW532 1 ML53 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW533 1 ML53 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW534 1 ML53 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW535 1 ML53 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B 95    .

txt XW561 1 ML56 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW562 1 ML56 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW563 1 ML56 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW564 1 ML56 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B 96    .+SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW541 1 ML54 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW542 1 ML54 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW543 1 ML54 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW544 1 ML54 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW545 1 ML54 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW551 1 ML55 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW552 1 ML55 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW553 1 ML55 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW554 1 ML55 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW555 1 ML55 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_15.

+SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW565 1 ML56 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW571 1 ML57 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW572 1 ML57 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW573 1 ML57 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW574 1 ML57 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW575 1 ML57 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW581 1 ML58 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW582 1 ML58 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW583 1 ML58 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW584 1 ML58 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW585 1 ML58 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW591 1 ML59 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW592 1 ML59 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW593 1 ML59 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 97    .

XW594 1 ML59 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW595 1 ML59 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 ML_GOF4_16.txt XW601 1 ML60 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW602 1 ML60 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW603 1 ML60 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW604 1 ML60 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW605 1 ML60 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW611 1 ML61 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW612 1 ML61 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW613 1 ML61 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW614 1 ML61 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW615 1 ML61 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW621 1 ML62 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW622 1 ML62 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 98    .

XW623 1 ML62 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW624 1 ML62 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW625 1 ML62 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 XW631 1 ML63 SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B WORD10M16 XW632 1 ML63 SL16 SL16B SL17 SL17B SL18 SL18B SL19 SL19B SL20 SL20B +SL21 SL21B SL22 SL22B SL23 SL23B SL24 SL24B SL25 SL25B SL26 SL26B SL27 SL27B +SL28 SL28B SL29 SL29B SL30 SL30B SL31 SL31B WORD10 XW633 1 ML63 SL32 SL32B SL33 SL33B SL34 SL34B SL35 SL35B SL36 SL36B +SL37 SL37B SL38 SL38B SL39 SL39B SL40 SL40B SL41 SL41B SL42 SL42B SL43 SL43B +SL44 SL44B SL45 SL45B SL46 SL46B SL47 SL47B WORD10 XW634 1 ML63 SL48 SL48B SL49 SL49B SL50 SL50B SL51 SL51B SL52 SL52B +SL53 SL53B SL54 SL54B SL55 SL55B SL56 SL56B SL57 SL57B SL58 SL58B SL59 SL59B +SL60 SL60B SL61 SL61B SL62 SL62B SL63 SL63B WORD10 XW635 1 ML63 SL64 SL64B SL65 SL65B SL66 SL66B SL67 SL67B SL68 SL68B +SL69 SL69B SL70 SL70B SL71 SL71B BYTE10 SLD10.80V VSLD08 SLD08 0 1.80V VSLD04 SLD04 0 1.80V VSLD08B SLD08B 0 0V 99    .80V VSLD00B SLD00B 0 0V VSLD01 SLD01 0 0V VSLD01B SLD01B 0 1.80V VSLD04B SLD04B 0 0V VSLD05 SLD05 0 0V VSLD05B SLD05B 0 1.80V VSLD02 SLD02 0 1.txt VSLD00 SLD00 0 1.80V VSLD06B SLD06B 0 0V VSLD07 SLD07 0 0V VSLD07B SLD07B 0 1.80V VSLD06 SLD06 0 1.80V VSLD02B SLD02B 0 0V VSLD03 SLD03 0 0V VSLD03B SLD03B 0 1.

80V VSLD22B SLD22B 0 0V VSLD23 SLD23 0 0V VSLD23B SLD23B 0 1.80V VSLD24B SLD24B 0 0V VSLD25 SLD25 0 0V VSLD25B SLD25B 0 1.80V VSLD14B SLD14B 0 0V VSLD15 SLD15 0 0V VSLD15B SLD15B 0 1.80V VSLD10B SLD10B 0 0V VSLD11 SLD11 0 0V VSLD11B SLD11B 0 1.80V VSLD16B SLD16B 0 0V VSLD17 SLD17 0 0V VSLD17B SLD17B 0 1.80V VSLD22 SLD22 0 1.80V VSLD28 SLD28 0 1.VSLD09 SLD09 0 0V VSLD09B SLD09B 0 1.80V VSLD26B SLD26B 0 0V VSLD27 SLD27 0 0V VSLD27B SLD27B 0 1.80V VSLD26 SLD26 0 1.80V VSLD10 SLD10 0 1.80V VSLD24 SLD24 0 1.80V VSLD12 SLD12 0 1.80V VSLD28B SLD28B 0 0V 100    .80V VSLD20B SLD20B 0 0V VSLD21 SLD21 0 0V VSLD21B SLD21B 0 1.80V VSLD14 SLD14 0 1.80V VSLD16 SLD16 0 1.80V VSLD12B SLD12B 0 0V VSLD13 SLD13 0 0V VSLD13B SLD13B 0 1.80V VSLD18 SLD18 0 1.80V VSLD18B SLD18B 0 0V VSLD19 SLD19 0 0V VSLD19B SLD19B 0 1.80V VSLD20 SLD20 0 1.

80V VSLD42B SLD42B 0 0V VSLD43 SLD43 0 0V VSLD43B SLD43B 0 1.80V VSLD38B SLD38B 0 0V VSLD39 SLD39 0 0V VSLD39B SLD39B 0 1.80V VSLD30B SLD30B 0 0V VSLD31 SLD31 0 0V VSLD31B SLD31B 0 1.80V VSLD32B SLD32B 0 0V VSLD33 SLD33 0 0V VSLD33B SLD33B 0 1.80V VSLD44B SLD44B 0 0V VSLD45 SLD45 0 0V VSLD45B SLD45B 0 1.80V VSLD46B SLD46B 0 0V VSLD47 SLD47 0 0V 101    .80V VSLD34 SLD34 0 1.80V VSLD30 SLD30 0 1.80V VSLD36B SLD36B 0 0V VSLD37 SLD37 0 0V VSLD37B SLD37B 0 1.80V VSLD46 SLD46 0 1.80V VSLD36 SLD36 0 1.VSLD29 SLD29 0 0V VSLD29B SLD29B 0 1.80V VSLD38 SLD38 0 1.80V VSLD32 SLD32 0 1.80V VSLD40 SLD40 0 1.80V VSLD42 SLD42 0 1.80V VSLD44 SLD44 0 1.80V VSLD40B SLD40B 0 0V VSLD41 SLD41 0 0V VSLD41B SLD41B 0 1.80V VSLD34B SLD34B 0 0V VSLD35 SLD35 0 0V VSLD35B SLD35B 0 1.

80V VSLD54 SLD54 0 1.80V VSLD58B SLD58B 0 0V VSLD59 SLD59 0 0V VSLD59B SLD59B 0 1.80V VSLD66 SLD66 0 1.80V VSLD60 SLD60 0 1.80V VSLD62 SLD62 0 1.80V VSLD52B SLD52B 0 0V VSLD53 SLD53 0 0V VSLD53B SLD53B 0 1.80V VSLD48 SLD48 0 1.80V VSLD56B SLD56B 0 0V VSLD57 SLD57 0 0V VSLD57B SLD57B 0 1.80V VSLD60B SLD60B 0 0V VSLD61 SLD61 0 0V VSLD61B SLD61B 0 1.80V VSLD58 SLD58 0 1.80V VSLD48B SLD48B 0 0V VSLD49 SLD49 0 0V VSLD49B SLD49B 0 1.80V VSLD54B SLD54B 0 0V VSLD55 SLD55 0 0V VSLD55B SLD55B 0 1.80V VSLD52 SLD52 0 1.80V VSLD50B SLD50B 0 0V VSLD51 SLD51 0 0V VSLD51B SLD51B 0 1.80V VSLD56 SLD56 0 1.80V VSLD66B SLD66B 0 0V 102    .80V VSLD62B SLD62B 0 0V VSLD63 SLD63 0 0V VSLD63B SLD63B 0 1.VSLD47B SLD47B 0 1.80V VSLD64 SLD64 0 1.80V VSLD64B SLD64B 0 0V VSLD65 SLD65 0 0V VSLD65B SLD65B 0 1.80V VSLD50 SLD50 0 1.

18U W = 0.27U MSLD11B SL11B SLDE SLD11B 0 cmosn L =0.18U W = 0.27U MSLD04B SL04B SLDE SLD04B 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.18U W = 0.TXT MSLD00 SL00 SLDE SLD00 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD06B SL06B SLDE SLD06B 0 cmosn L =0.18U W = 0.27U MSLD00B SL00B SLDE SLD00B 0 cmosn L =0.27U MSLD11 SL11 SLDE SLD11 0 cmosn L =0.27U MSLD05B SL05B SLDE SLD05B 0 cmosn L =0.27U MSLD02B SL02B SLDE SLD02B 0 cmosn L =0.27U MSLD07B SL07B SLDE SLD07B 0 cmosn L =0.18U W = 0.27U MSLD10B SL10B SLDE SLD10B 0 cmosn L =0.27U MSLD01B SL01B SLDE SLD01B 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD05 SL05 SLDE SLD05 0 cmosn L =0.18U W = 0.27U MSLD06 SL06 SLDE SLD06 0 cmosn L =0.27U MSLD09 SL09 SLDE SLD09 0 cmosn L =0.18U W = 0.27U 103    .18U W = 0.27U MSLD04 SL04 SLDE SLD04 0 cmosn L =0.80V SLDET.18U W = 0.27U MSLD13 SL13 SLDE SLD13 0 cmosn L =0.27U MSLD07 SL07 SLDE SLD07 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD08 SL08 SLDE SLD08 0 cmosn L =0.27U MSLD08B SL08B SLDE SLD08B 0 cmosn L =0.18U W = 0.80V VSLD70B SLD70B 0 0V VSLD71 SLD71 0 0V VSLD71B SLD71B 0 1.80V VSLD68 SLD68 0 1.18U W = 0.27U MSLD09B SL09B SLDE SLD09B 0 cmosn L =0.27U MSLD01 SL01 SLDE SLD01 0 cmosn L =0.27U MSLD03B SL03B SLDE SLD03B 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD12 SL12 SLDE SLD12 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.80V VSLD68B SLD68B 0 0V VSLD69 SLD69 0 0V VSLD69B SLD69B 0 1.27U MSLD10 SL10 SLDE SLD10 0 cmosn L =0.27U MSLD02 SL02 SLDE SLD02 0 cmosn L =0.18U W = 0.27U MSLD13B SL13B SLDE SLD13B 0 cmosn L =0.VSLD67 SLD67 0 0V VSLD67B SLD67B 0 1.18U W = 0.80V VSLD70 SLD70 0 1.27U MSLD12B SL12B SLDE SLD12B 0 cmosn L =0.27U MSLD03 SL03 SLDE SLD03 0 cmosn L =0.18U W = 0.

18U W = 0.27U MSLD23B SL23B SLDE SLD23B 0 cmosn L =0.18U W = 0.27U MSLD23 SL23 SLDE SLD23 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.27U MSLD14B SL14B SLDE SLD14B 0 cmosn L =0.27U MSLD21 SL21 SLDE SLD21 0 cmosn L =0.27U MSLD18B SL18B SLDE SLD18B 0 cmosn L =0.27U MSLD29B SL29B SLDE SLD29B 0 cmosn L =0.18U W = 0.27U MSLD29 SL29 SLDE SLD29 0 cmosn L =0.27U MSLD26 SL26 SLDE SLD26 0 cmosn L =0.27U MSLD15 SL15 SLDE SLD15 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD26B SL26B SLDE SLD26B 0 cmosn L =0.18U W = 0.27U MSLD19 SL19 SLDE SLD19 0 cmosn L =0.18U W = 0.27U MSLD22 SL22 SLDE SLD22 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.27U MSLD16 SL16 SLDE SLD16 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD16B SL16B SLDE SLD16B 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD28 SL28 SLDE SLD28 0 cmosn L =0.27U 104    .27U MSLD31B SL31B SLDE SLD31B 0 cmosn L =0.18U W = 0.27U MSLD31 SL31 SLDE SLD31 0 cmosn L =0.27U MSLD32 SL32 SLDE SLD32 0 cmosn L =0.18U W = 0.27U MSLD30 SL30 SLDE SLD30 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD27B SL27B SLDE SLD27B 0 cmosn L =0.18U W = 0.27U MSLD20B SL20B SLDE SLD20B 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.18U W = 0.27U MSLD30B SL30B SLDE SLD30B 0 cmosn L =0.27U MSLD28B SL28B SLDE SLD28B 0 cmosn L =0.27U MSLD25 SL25 SLDE SLD25 0 cmosn L =0.18U W = 0.27U MSLD27 SL27 SLDE SLD27 0 cmosn L =0.27U MSLD24 SL24 SLDE SLD24 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.18U W = 0.27U MSLD33B SL33B SLDE SLD33B 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.27U MSLD33 SL33 SLDE SLD33 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.27U MSLD19B SL19B SLDE SLD19B 0 cmosn L =0.18U W = 0.27U MSLD25B SL25B SLDE SLD25B 0 cmosn L =0.27U MSLD20 SL20 SLDE SLD20 0 cmosn L =0.18U W = 0.27U MSLD17B SL17B SLDE SLD17B 0 cmosn L =0.27U MSLD15B SL15B SLDE SLD15B 0 cmosn L =0.27U MSLD32B SL32B SLDE SLD32B 0 cmosn L =0.18U W = 0.27U MSLD22B SL22B SLDE SLD22B 0 cmosn L =0.MSLD14 SL14 SLDE SLD14 0 cmosn L =0.27U MSLD21B SL21B SLDE SLD21B 0 cmosn L =0.27U MSLD17 SL17 SLDE SLD17 0 cmosn L =0.27U MSLD24B SL24B SLDE SLD24B 0 cmosn L =0.27U MSLD18 SL18 SLDE SLD18 0 cmosn L =0.

18U W = 0.18U W = 0.27U MSLD39B SL39B SLDE SLD39B 0 cmosn L =0.27U MSLD47 SL47 SLDE SLD47 0 cmosn L =0.18U W = 0.27U MSLD49 SL49 SLDE SLD49 0 cmosn L =0.27U MSLD41B SL41B SLDE SLD41B 0 cmosn L =0.27U MSLD51 SL51 SLDE SLD51 0 cmosn L =0.27U MSLD46B SL46B SLDE SLD46B 0 cmosn L =0.18U W = 0.27U MSLD41 SL41 SLDE SLD41 0 cmosn L =0.27U MSLD36 SL36 SLDE SLD36 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD45B SL45B SLDE SLD45B 0 cmosn L =0.27U MSLD37B SL37B SLDE SLD37B 0 cmosn L =0.18U W = 0.18U W = 0.MSLD34 SL34 SLDE SLD34 0 cmosn L =0.18U W = 0.27U MSLD42 SL42 SLDE SLD42 0 cmosn L =0.27U MSLD42B SL42B SLDE SLD42B 0 cmosn L =0.27U MSLD49B SL49B SLDE SLD49B 0 cmosn L =0.27U MSLD44 SL44 SLDE SLD44 0 cmosn L =0.18U W = 0.27U MSLD38B SL38B SLDE SLD38B 0 cmosn L =0.27U MSLD45 SL45 SLDE SLD45 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD36B SL36B SLDE SLD36B 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD48 SL48 SLDE SLD48 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD37 SL37 SLDE SLD37 0 cmosn L =0.18U W = 0.27U MSLD48B SL48B SLDE SLD48B 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.27U 105    .18U W = 0.27U MSLD43B SL43B SLDE SLD43B 0 cmosn L =0.27U MSLD44B SL44B SLDE SLD44B 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD52B SL52B SLDE SLD52B 0 cmosn L =0.18U W = 0.27U MSLD50B SL50B SLDE SLD50B 0 cmosn L =0.27U MSLD46 SL46 SLDE SLD46 0 cmosn L =0.18U W = 0.27U MSLD35B SL35B SLDE SLD35B 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD40B SL40B SLDE SLD40B 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.18U W = 0.18U W = 0.27U MSLD51B SL51B SLDE SLD51B 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.18U W = 0.27U MSLD38 SL38 SLDE SLD38 0 cmosn L =0.27U MSLD39 SL39 SLDE SLD39 0 cmosn L =0.27U MSLD52 SL52 SLDE SLD52 0 cmosn L =0.27U MSLD34B SL34B SLDE SLD34B 0 cmosn L =0.27U MSLD53 SL53 SLDE SLD53 0 cmosn L =0.18U W = 0.27U MSLD43 SL43 SLDE SLD43 0 cmosn L =0.27U MSLD35 SL35 SLDE SLD35 0 cmosn L =0.27U MSLD50 SL50 SLDE SLD50 0 cmosn L =0.27U MSLD47B SL47B SLDE SLD47B 0 cmosn L =0.27U MSLD40 SL40 SLDE SLD40 0 cmosn L =0.18U W = 0.18U W = 0.

18U W = 0.27U MSLD62 SL62 SLDE SLD62 0 cmosn L =0.27U MSLD59B SL59B SLDE SLD59B 0 cmosn L =0.27U MSLD69B SL69B SLDE SLD69B 0 cmosn L =0.27U MSLD65 SL65 SLDE SLD65 0 cmosn L =0.27U MSLD61B SL61B SLDE SLD61B 0 cmosn L =0.27U MSLD71 SL71 SLDE SLD71 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.18U W = 0.18U W = 0.18U W = 0.18U W = 0.27U MSLD59 SL59 SLDE SLD59 0 cmosn L =0.18U W = 0.18U W = 0.18U W = 0.27U MSLD66 SL66 SLDE SLD66 0 cmosn L =0.27U MSLD70 SL70 SLDE SLD70 0 cmosn L =0.18U W = 0.27U MSLD67B SL67B SLDE SLD67B 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD67 SL67 SLDE SLD67 0 cmosn L =0.27U MSLD58 SL58 SLDE SLD58 0 cmosn L =0.18U W = 0.27U MSLD54B SL54B SLDE SLD54B 0 cmosn L =0.18U W = 0.27U MSLD68 SL68 SLDE SLD68 0 cmosn L =0.27U MSLD60B SL60B SLDE SLD60B 0 cmosn L =0.18U W = 0.27U MSLD64 SL64 SLDE SLD64 0 cmosn L =0.27U MSLD71B SL71B SLDE SLD71B 0 cmosn L =0.18U W = 0.18U W = 0.SUBCKT TCAM0 1 2 7 8 106    .18U W = 0.18U W = 0.18U W = 0.27U MSLD54 SL54 SLDE SLD54 0 cmosn L =0.18U W = 0.27U MSLD60 SL60 SLDE SLD60 0 cmosn L =0.27U MSLD55 SL55 SLDE SLD55 0 cmosn L =0.27U MSLD62B SL62B SLDE SLD62B 0 cmosn L =0.27U MSLD58B SL58B SLDE SLD58B 0 cmosn L =0.18U W = 0.27U MSLD63B SL63B SLDE SLD63B 0 cmosn L =0.27U MSLD70B SL70B SLDE SLD70B 0 cmosn L =0.18U W = 0.18U W = 0.TXT .18U W = 0.18U W = 0.27U MSLD56 SL56 SLDE SLD56 0 cmosn L =0.18U W = 0.27U MSLD63 SL63 SLDE SLD63 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD68B SL68B SLDE SLD68B 0 cmosn L =0.18U W = 0.27U MSLD56B SL56B SLDE SLD56B 0 cmosn L =0.27U MSLD66B SL66B SLDE SLD66B 0 cmosn L =0.18U W = 0.27U MSLD55B SL55B SLDE SLD55B 0 cmosn L =0.27U MSLD57B SL57B SLDE SLD57B 0 cmosn L =0.27U TCAM0.18U W = 0.27U MSLD65B SL65B SLDE SLD65B 0 cmosn L =0.18U W = 0.27U MSLD57 SL57 SLDE SLD57 0 cmosn L =0.27U MSLD69 SL69 SLDE SLD69 0 cmosn L =0.MSLD53B SL53B SLDE SLD53B 0 cmosn L =0.18U W = 0.18U W = 0.27U MSLD64B SL64B SLDE SLD64B 0 cmosn L =0.27U MSLD61 SL61 SLDE SLD61 0 cmosn L =0.

SUBCKT INVTR VCC IN OUT M1 OUT IN VCC VCC cmosp L = 0.27U MN4 6 8 0 0 cmosn L =0.18U W = 0.18U W = .18U W = 0.18U W = 0.18U W = 0.ENDS TCAM0 TCAM1.27U *FOR WRITE VWL WL 0 DC 0V VBLL BLL 0 DC 0V VBLLB BLLB 0 DC 0V VBLR BLR 0 DC 0V VBLRB BLRB 0 DC 0V MR1 3 WL BLLB 0 cmosn L =0.27U MN2 2 4 6 0 cmosn L =0.SUBCKT TCAM1 1 2 7 8 VMD1 9 0 DC 1.18U W = 0.27U MN4 6 8 0 0 cmosn L =0.27U MN3 5 7 0 0 cmosn L =0.ENDS INVTR .27U MR2 9 WL BLL 0 cmosn L =0.27U MN2 2 4 6 0 cmosn L =0.27U .27U *INVERTER SUBCKT .8v X1 1 9 3 INVTR X2 1 3 9 INVTR X3 1 10 4 INVTR X4 1 4 10 INVTR MN1 2 3 5 0 cmosn L =0.27U MN3 5 7 0 0 cmosn L =0.27U MR4 4 WL BLR 0 cmosn L =0.TXT .8V VMD1B 10 0 DC 0V X1 1 9 3 INVTR X2 1 3 9 INVTR X3 1 10 4 INVTR X4 1 4 10 INVTR MN1 2 3 5 0 cmosn L =0.18U W = 0.27U MR3 10 WL BLRB 0 cmosn L =0.63U M2 OUT IN 0 0 cmosn L =0.18U W = 0.27U *FOR WRITE VWL WL 0 DC 0V VBLL BLL 0 DC 0V 107    .18U W = 0.18U W = 0.18U W = 0.18U W = 0.18U W = 0.18U W = 0.VMD0 9 0 DC 0V VMD0B 10 0 DC 1.

27U MR2 9 WL BLL 0 cmosn L =0.ENDS TCAM1 TCAMX.27U .18U W = .18U W = 0.27U MR3 10 WL BLRB 0 cmosn L =0.27U *FOR WRITE VWL WL 0 DC 0V VBLL BLL 0 DC 0V VBLLB BLLB 0 DC 0V VBLR BLR 0 DC 0V VBLRB BLRB 0 DC 0V MR1 3 WL BLLB 0 cmosn L =0.18U W = 0.18U W = 0.TXT 108    .27U MR4 4 WL BLR 0 cmosn L =0.ENDS INVTR .27U .8V VMDXB 10 0 DC 1.27U .27U MR3 10 WL BLRB 0 cmosn L =0.27U MR4 4 WL BLR 0 cmosn L =0.27U MN2 2 4 6 0 cmosn L =0.18U W = 0.18U W = 0.VBLLB BLLB 0 DC 0V VBLR BLR 0 DC 0V VBLRB BLRB 0 DC 0V MR1 3 WL BLLB 0 cmosn L =0.27U MR2 9 WL BLL 0 cmosn L =0.18U W = .ENDS TCAMX WORDX.8V X1 1 9 3 INVTR X2 1 3 9 INVTR X3 1 10 4 INVTR X4 1 4 10 INVTR MN1 2 3 5 0 cmosn L =0.18U W = 0.18U W = 0.SUBCKT INVTR VCC IN OUT M1 OUT IN VCC VCC cmosp L = 0.18U W = 0.18U W = 0.63U M2 OUT IN 0 0 cmosn L =0.18U W = 0.18U W = 0.27U MN3 5 7 0 0 cmosn L =0.18U W = 0.63U M2 OUT IN 0 0 cmosn L =0.27U MN4 6 8 0 0 cmosn L =0.ENDS INVTR .SUBCKT TCAMX 1 2 7 8 VMDX 9 0 DC 1.18U W = 0.27U .18U W = 0.SUBCKT INVTR VCC IN OUT M1 OUT IN VCC VCC cmosp L = 0.TXT .

ENDS WORDX BYTEX.SUBCKT WORD10M1 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM1 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM1 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM1 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM1 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM1 X11 1 ML SL11 SL11B TCAM0 109    .SUBCKT BYTEX 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B X00 1 ML SL00 SL00B TCAMX X01 1 ML SL01 SL01B TCAMX X02 1 ML SL02 SL02B TCAMX X03 1 ML SL03 SL03B TCAMX X04 1 ML SL04 SL04B TCAMX X05 1 ML SL05 SL05B TCAMX X06 1 ML SL06 SL06B TCAMX X07 1 ML SL07 SL07B TCAMX .ENDS BYTEX WORD10M1..TXT .TXT .SUBCKT WORDX 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAMX X01 1 ML SL01 SL01B TCAMX X02 1 ML SL02 SL02B TCAMX X03 1 ML SL03 SL03B TCAMX X04 1 ML SL04 SL04B TCAMX X05 1 ML SL05 SL05B TCAMX X06 1 ML SL06 SL06B TCAMX X07 1 ML SL07 SL07B TCAMX X08 1 ML SL08 SL08B TCAMX X09 1 ML SL09 SL09B TCAMX X10 1 ML SL10 SL10B TCAMX X11 1 ML SL11 SL11B TCAMX X12 1 ML SL12 SL12B TCAMX X13 1 ML SL13 SL13B TCAMX X14 1 ML SL14 SL14B TCAMX X15 1 ML SL15 SL15B TCAMX .

SUBCKT WORD10M2 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM1 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM1 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM1 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM1 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM1 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M1 WORD10M2.TXT .ENDS WORD10M2 WORD10M4.X12 1 ML SL12 SL12B TCAM1 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M2 WORD10M3.SUBCKT WORD10M2 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM1 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM1 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM1 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM1 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM1 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .TXT 110    .TXT .

TXT .ENDS WORD10M5 WORD10M6.SUBCKT WORD10M5 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM1 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM1 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .TXT ..SUBCKT WORD10M6 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM0 111    .SUBCKT WORD10M4 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM1 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM1 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM1 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M4 WORD10M5.

ENDS WORD10M7 WORD10M8.SUBCKT WORD10M7 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .SUBCKT WORD10M8 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM0 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 112    .ENDS WORD10M6 WORD10M7.X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM1 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM1 X15 1 ML SL15 SL15B TCAM0 .TXT .TXT .

ENDS WORD10M8 WORD10M9.SUBCKT WORD10M11 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B 113    .TXT .TXT .ENDS WORD10M10 WORD10M11.SUBCKT WORD10M10 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .TXT .X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .SUBCKT WORD10M9 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM0 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM0 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M9 WORD10M10.

SUBCKT WORD10M13 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 114    .TXT .ENDS WORD10M12 WORD10M13.+SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM0 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .SUBCKT WORD10M12 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM1 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM0 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .TXT .ENDS WORD10M11 WORD10M12.

X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM1 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM1 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM0 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .TXT .SUBCKT WORD10M14 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM1 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM1 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM1 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM0 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM0 .ENDS WORD10M14 WORD10M15.ENDS WORD10M13 WORD10M14.TXT .SUBCKT WORD10M15 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM1 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM1 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM1 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM1 X14 1 ML SL14 SL14B TCAM0 115    .

3NS .MEAS TRAN AVGML1POW AVG P(VMLV01) FROM = 1.TXT .3NS .3NS .MEAS TRAN AVGML5POW AVG P(VMLV05) FROM = 1.15NS TO = 2.X15 1 ML SL15 SL15B TCAM0 .3NS .15NS TO = 2.3NS .MEAS TRAN AVGML2POW AVG P(VMLV02) FROM = 1.3NS .MEAS TRAN AVGML4POW AVG P(VMLV04) FROM = 1.ENDS WORD10M15 WORD10M16.ENDS BYTE10M8 MEAS_MCAM32.15NS TO = 2.15NS TO = 2.SUBCKT BYTE10M8 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM1 .3NS .ENDS WORD10M16 BYTE10M8.MEAS TRAN AVGML9POW AVG P(VMLV09) FROM = 1.SUBCKT WORD10M16 1 ML SL00 SL00B SL01 SL01B SL02 SL02B SL03 SL03B SL04 SL04B +SL05 SL05B SL06 SL06B SL07 SL07B SL08 SL08B SL09 SL09B SL10 SL10B SL11 SL11B +SL12 SL12B SL13 SL13B SL14 SL14B SL15 SL15B X00 1 ML SL00 SL00B TCAM0 X01 1 ML SL01 SL01B TCAM1 X02 1 ML SL02 SL02B TCAM0 X03 1 ML SL03 SL03B TCAM1 X04 1 ML SL04 SL04B TCAM0 X05 1 ML SL05 SL05B TCAM1 X06 1 ML SL06 SL06B TCAM0 X07 1 ML SL07 SL07B TCAM1 X08 1 ML SL08 SL08B TCAM0 X09 1 ML SL09 SL09B TCAM1 X10 1 ML SL10 SL10B TCAM0 X11 1 ML SL11 SL11B TCAM1 X12 1 ML SL12 SL12B TCAM0 X13 1 ML SL13 SL13B TCAM1 X14 1 ML SL14 SL14B TCAM0 X15 1 ML SL15 SL15B TCAM1 .3NS .txt .MEAS TRAN AVGML3POW AVG P(VMLV03) FROM = 1.MEAS TRAN AVGML0POW AVG P(VMLV00) FROM = 1.15NS TO = 2.15NS TO = 2.3NS .15NS TO = 2.3NS 116    .MEAS TRAN AVGML10POW AVG P(VMLV10) FROM = 1.MEAS TRAN AVGML6POW AVG P(VMLV06) FROM = 1.3NS .15NS TO = 2.TXT .15NS TO = 2.MEAS TRAN AVGML8POW AVG P(VMLV08) FROM = 1.MEAS TRAN AVGML7POW AVG P(VMLV07) FROM = 1.15NS TO = 2.15NS TO = 2.

15NS .MEAS TRAN AVGML31POW AVG P(VMLV31) FROM = 1.15NS .MEAS TRAN AVGSL2POW AVG P(VSLD02) FROM = 0NS TO = 1.MEAS TRAN AVGML23POW AVG P(VMLV23) FROM = 1.15NS .MEAS TRAN AVGML13POW AVG P(VMLV13) FROM = 1..15NS .MEAS TRAN AVGML21POW AVG P(VMLV21) FROM = 1.MEAS TRAN AVGSLB2POW AVG P(VSLD02B) FROM = 0NS TO = 1.15NS TO = 2.3NS .MEAS TRAN AVGSL0POW AVG P(VSLD00) FROM = 0NS TO = 1.MEAS TRAN AVGML12POW AVG P(VMLV12) FROM = 1.15NS .15NS TO = 2.3NS 117    .15NS TO = 2.MEAS TRAN AVGML14POW AVG P(VMLV14) FROM = 1.MEAS TRAN AVGML22POW AVG P(VMLV22) FROM = 1.MEAS TRAN AVGML18POW AVG P(VMLV18) FROM = 1.MEAS TRAN AVGSLC2B2POW AVG P(VSLD02B) FROM = 1.MEAS TRAN AVGSLC2B0POW AVG P(VSLD00B) FROM = 1.MEAS TRAN AVGSLB7POW AVG P(VSLD07B) FROM = 0NS TO = 1.MEAS TRAN AVGML24POW AVG P(VMLV24) FROM = 1.15NS TO = 2.3NS .15NS .MEAS TRAN AVGSLC2B1POW AVG P(VSLD01B) FROM = 1.3NS .15NS TO = 2.MEAS TRAN AVGSL7POW AVG P(VSLD07) FROM = 0NS TO = 1.15NS .15NS TO = 2.MEAS TRAN AVGSL4POW AVG P(VSLD04) FROM = 0NS TO = 1.15NS TO = 2.15NS .MEAS TRAN AVGML11POW AVG P(VMLV11) FROM = 1.3NS .MEAS TRAN AVGSL1POW AVG P(VSLD01) FROM = 0NS TO = 1.3NS .3NS .3NS .15NS .15NS .15NS .15NS .MEAS TRAN AVGML17POW AVG P(VMLV17) FROM = 1.MEAS TRAN AVGSL6POW AVG P(VSLD06) FROM = 0NS TO = 1.15NS TO = 2.MEAS TRAN AVGSLB9POW AVG P(VSLD09B) FROM = 0NS TO = 1.15NS .MEAS TRAN AVGSLB3POW AVG P(VSLD03B) FROM = 0NS TO = 1.MEAS TRAN AVGSL9POW AVG P(VSLD09) FROM = 0NS TO = 1.3NS .3NS .MEAS TRAN AVGML20POW AVG P(VMLV20) FROM = 1.MEAS TRAN AVGSLB5POW AVG P(VSLD05B) FROM = 0NS TO = 1.MEAS TRAN AVGSLC20POW AVG P(VSLD00) FROM = 1.3NS .3NS .15NS TO = 2.15NS TO = 2.3NS .3NS .15NS .3NS .15NS TO = 2.15NS .15NS .3NS .15NS TO = 2.15NS TO = 2.MEAS TRAN AVGML26POW AVG P(VMLV26) FROM = 1.3NS .3NS .MEAS TRAN AVGSL5POW AVG P(VSLD05) FROM = 0NS TO = 1.MEAS TRAN AVGSLB8POW AVG P(VSLD08B) FROM = 0NS TO = 1.MEAS TRAN AVGSLB0POW AVG P(VSLD00B) FROM = 0NS TO = 1.15NS TO = 2.3NS .3NS .15NS .3NS .3NS .MEAS TRAN AVGSLC23POW AVG P(VSLD03) FROM = 1.3NS .MEAS TRAN AVGML29POW AVG P(VMLV29) FROM = 1.3NS .15NS TO = 2.3NS .MEAS TRAN AVGSLB4POW AVG P(VSLD04B) FROM = 0NS TO = 1.MEAS TRAN AVGSLC2B3POW AVG P(VSLD03B) FROM = 1.15NS TO = 2.MEAS TRAN AVGML25POW AVG P(VMLV25) FROM = 1.15NS TO = 2.MEAS TRAN AVGSLC24POW AVG P(VSLD04) FROM = 1.MEAS TRAN AVGSLB6POW AVG P(VSLD06B) FROM = 0NS TO = 1.15NS TO = 2.MEAS TRAN AVGML27POW AVG P(VMLV27) FROM = 1.15NS TO = 2.15NS TO = 2.15NS .15NS TO = 2.MEAS TRAN AVGSL3POW AVG P(VSLD03) FROM = 0NS TO = 1.MEAS TRAN AVGML30POW AVG P(VMLV30) FROM = 1.3NS .3NS .15NS TO = 2.15NS TO = 2.MEAS TRAN AVGSLC21POW AVG P(VSLD01) FROM = 1.MEAS TRAN AVGML28POW AVG P(VMLV28) FROM = 1.3NS .15NS TO = 2.MEAS TRAN AVGML19POW AVG P(VMLV19) FROM = 1.15NS TO = 2.3NS .MEAS TRAN AVGML15POW AVG P(VMLV15) FROM = 1.15NS TO = 2.15NS TO = 2.15NS TO = 2.MEAS TRAN AVGML16POW AVG P(VMLV16) FROM = 1.MEAS TRAN AVGSLB1POW AVG P(VSLD01B) FROM = 0NS TO = 1.15NS TO = 2.MEAS TRAN AVGSLC22POW AVG P(VSLD02) FROM = 1.15NS .15NS .MEAS TRAN AVGSL8POW AVG P(VSLD08) FROM = 0NS TO = 1.15NS TO = 2.3NS .

3NS .197728 = 0.3NS .1E-9 = 0.5 LINT DWG PRWG =0 = -1E-8 = 1.504826E-11 VSAT = 0. Star-HSPICE Level 49.40499E-9 = 1.0948017 = 2.MEAS TRAN AVGSLC2B9POW AVG P(VSLD09B) FROM = 1.MEAS TRAN AVGSLC28POW AVG P(VSLD08) FROM = 1.3376355 =1 =0 WINT XW B0 A1 = 1.8094484 DVT1W = 0 DVT1 UA DVT2W = 0 DVT2 = 0.4640272 = -0.1 PARAMETERS * * SPICE 3f5 Level 8.4449958 = -0..630684E-7 = 2.355009E5 = 6.901075E-7 = 3.0197749 UB A0 B1 A2 PRWB = 2.4E-4 CDSCD = 0 = 6.MEAS TRAN AVGSLC2B7POW AVG P(VSLD07B) FROM = 1.868769E-4 = 0.MEAS TRAN AVGSLC2B5POW AVG P(VSLD05B) FROM = 1.15NS TO = 2.MEAS TRAN AVGSLC2B6POW AVG P(VSLD06B) FROM = 1.3NS .15NS TO = 2.15NS TO = 2. UTMOST Level 8 * * DATE: Oct 31/05 * LOT: T58F WAF: 9005 * Temperature_parameters=Default .15NS TO = 2.127266E-3 = 1E-7 +DVT0W = 0 +DVT0 = 1.MEAS TRAN AVGSLC26POW AVG P(VSLD06) FROM = 1.15NS TO = 2.MEAS TRAN AVGSLC2B4POW AVG P(VSLD04B) FROM = 1.0164863 = 123.MODEL CMOSN NMOS ( +VERSION = 3.452411E-9 VOFF =0 CDSC ETA0 = -0.1 +XJ +K1 +K3B = 1E-7 = 0.4215486 = -1.99995E-6 = 0.728719E-9 NFACTOR = 2.15NS TO = 2.3662473 = 1E-3 = 1.MEAS TRAN AVGSLC2B8POW AVG P(VSLD08B) FROM = 1.15NS TO = 2.0294061 TNOM NCH K2 W0 = 27 LEVEL = 49 TOX VTH0 K3 NLX = 4.15NS TO = 2.MEAS TRAN AVGSLC29POW AVG P(VSLD09) FROM = 1.1860065 = -2.lib * T58F SPICE BSIM3 VERSION 3.5864999 = 0.3NS tsmc018.15NS TO = 2.408323E-18 =2 = 4.3NS .690044E-8 = -4.3NS .3549E17 = 1.230928E-3 ETAB 118    .15NS TO = 2.3NS .3NS .MEAS TRAN AVGSLC25POW AVG P(VSLD05) FROM = 1.3NS .2064649 +U0 +UC +AGS +KETA +RDSW +WR +XL +DWB +CIT = 273.MEAS TRAN AVGSLC27POW AVG P(VSLD07) FROM = 1.15NS TO = 2.3NS .3NS .028975E-5 +CDSCB = 0 = 2.

84133E-25 = 1.92 EM=41000000 ) * * * flicker noise parameters above added manually from some other process * .466429E-4 = 8.777519 +PVSAT = 2.349607E-9 PVAG = 1.91287E9 +DELTA = 0.9368961 WKETA = -2.0145467 +PDIBLC2 = 1.194072E-7 = 4.165078E-3 PUA = 5.3820266 MJSW = 0.01 +PRT +KT1L +UB1 +WL +WWN +LLN +LWL =0 =0 = -7.66653E-3 +PSCBE1 = 8.102322 = 2.3E-10 +CF +PK2 +PU0 =0 PBSWG = 0.3906012 =0 = 1.3822069 PDIBLC1 = 0.MODEL CMOSP PMOS ( +VERSION = 3.11 = 4.31E-9 = 3.102322 PVTH0 = -2.0E+00 PETA0 = 1.3E4 UTE KT2 = -1.3182567385564E+19 +NOIB=144543.4916211 TNOM NCH K2 W0 = 27 LEVEL = 49 TOX VTH0 K3 NLX = 4.880976E-3 LKETA = 7.685917E-3 RSH = 6.1E-9 = -0.505418E-12 PUB = 8.003159E-4 PKETA = -6.1 +XJ +K1 +K3B = 1E-7 = 0.1762787 DROUT = 0.+DSUB = 0.7 MOBMOD = 1 KT1 UA1 AT =0 =0 =1 = -0.0395326 = 1E-6 119    .6E-11 =1 =0 WW LL LWN WLN WWL LW =0 CAPMOD = 2 CGSO PB XPART = 0.006286E3 +NOIMOD=2.23E-10 MJ = 0.608154E-10 PBSW +CJSWG = 3.8 = 0.593254E-3 = 6.1589E17 = 0.23E-10 +CJ +CJSW = 9.977074592 NOIC=-1.199373E-3 PRDSW = -0.7694691 PDIBLCB = -0.5341312 = 7.8 = 0.61E-18 =0 =1 =1 =0 PCLM = 1.022 UC1 = -5.759277E-3 NOIA=1.1 PSCBE2 = 7.5 = 0.24515784572817E-12 EF=0.8 MJSWG = 0.5 CGBO = 1E-12 +CGDO = 8.

0222457 PUA = -6.4186945 DVT1W = 0 DVT1 UA DVT2W = 0 DVT2 = 0.095236 +KETA = 0.11 = 4.5580645 WKETA = 0.766563E-3 DROUT = 1.300003 = -0.22E-10 +CF +PK2 +PU0 =0 PBSWG = 0.022 UC1 = -5.949178E-7 = 0.9976555 = 6.7 MOBMOD = 1 KT1 UA1 AT =0 =0 =1 = -0.321294 =1 =0 PRWG =0 = -1E-8 PRWB WINT XW = 2.0209921 +PDIBLC2 = 7.422908E-7 = 0.011891E-3 PVAG = 0.8468686 = 0.4E-4 CDSCD = 0 ETAB = -4.31E-9 = 3.61E-18 =0 =1 =1 =0 RSH UTE KT2 = 7.94454E-8 = -2.5060555 +U0 +UC +AGS = 115.4099522 MJSW = 0.8769118 PVTH0 = 2.573746E-9 VSAT B0 A1 = 1.5 LINT DWG = -0.6894042 = -1E-10 = 0.36889E-11 PUB 120    .+DVT0W = 0 +DVT0 = 0.728395E-7 PDIBLCB = -1E-3 +PSCBE1 = 4.5 CGBO MJ = 1E-12 +CGDO = 6.495872E-3 = 1E-21 = 1.1 UB A0 B1 A2 = 1.144521E-3 = 6.8769118 +CJSWG = 4.872184E10 PSCBE2 = 5E-10 +DELTA = 0.3E4 = -1.358398E-4 +CDSCB = 0 +DSUB = 1.01 +PRT +KT1L +UB1 +WL +WWN +LLN +LWL =0 =0 = -7.302018E-3 PRDSW = 9.3478565 MJSWG = 0.490749E-10 PBSW = 0.3299898 PDIBLC1 = 1.0166345 +RDSW +WR +XL +DWB +CIT = 198.816555E-3 PCLM = 1.2423835 = 1.83797E-10 VOFF =0 CDSC ETA0 = 2.6E-11 =1 =0 WW LL LWN WLN WWL LW =0 CAPMOD = 2 CGSO PB XPART = 0.3478565 = 2.4749146 = 0.4986647 = 0.874308E-21 = 1.35E-10 +CJ +CJSW = 1.821914E-3 = -1.35E-10 = 0.5 = 0.035504E-3 = 1.0575312 LKETA = -1.798724E-8 NFACTOR = 2 = -4.130982E5 = 1.

827793E-5 PKETA = -2.8420442 + NOIMOD=2.0E+00 PETA0 = 2.61260020285845E-11 EF=1.57456993317604E+18 + NOIC=2.536564E-3 NOIB=2500 EM=41000000 ) NOIA=3.1388 * * * flicker noise parameters above added manually from some other process *   121    .+PVSAT = 49.

2.8V.10V *MEASURE THE SL AND ML POWER .56N 0V. 1.INCLUDE 'MYMLCSNEW.30N 1.39N 0V.1..56N 0V.3N 1.1.0.8V.txt' $2ND 4 X 72 CAM CELL BLOCK .INCLUDE 'ML_GOF4_9.2.8V.INCLUDE 'mcamxmlcs64..1.15N 0V.77N 1.1.1.39N 1.A.3N 1.2.75N 0V.txt' .15N uic .02N 0V.8V.1.INCLUDE 'ML_GOF4_3. 1.17N 0V. E.PARAM x=1.8V.54N 0V.1.INCLUDE 'ML_GOF4_8.15N 1.8V.0.39N 1.8V *Voltage sources to charge matchlines ..3N 0V VMLPB MLPB 0 PWL 0 0V.90N 0V.15N 1.INCLUDE 'MYMLSA.15N 1.txt' *SENSE AMPLIFIER BLOCK .1.txt' .49N 0V.08N 0V.txt' *** MATCH LINE CAM CELL TOGETHER 4 LINE .INCLUDE 'ML_GOF4_1.INCLUDE 'vmlv64.8V..8V..g.41N 0V.1.txt' .80V.txt' 122    .80V.80 VDD 1 0 DC x VMLC MLC 0 PWL 0 1.txt' .INCLUDE 'mcamxsa64.2 HSpice code for simplified design of charging controller  mcam64_72_tencon.41N 0V.INCLUDE 'ML_GOF4_7.INCLUDE 'MEAS_MCAM32.TXT' . ML_GOF4_1=MATCH LINE_ GROUP OF 4_1 .. ML_GOF4_2=MATCH LINE_ GROUP OF 4_2 .IC V(MLV00)=.8V.56N 1.txt' *MATCHLINE PRECHARGE & CHARGE CONTROLLER BLOCKS ..8V.08N 1.txt' .54N 1.54N 1.INCLUDE 'ML_GOF4_2.txt' . 1.INCLUDE 'ML_GOF4_11.TRAN 20P 2.80V VSLDE SLDE 0 PWL 0 1.INCLUDE 'ML_GOF4_4.80V.1.1. MLV00 is to charge matchline ML00 .1.8V VMLP MLP 0 PWL 0 1.sp TCAM Circuit .92N 1.0.1.TXT' * VCC AND PRECHARGE VOLTAGES .8V.INCLUDE 'ML_GOF4_10.8V.TXT' $ML CHARGE CONTROLLER BLOCK ..txt' .36N 1.8V.INCLUDE 'ML_GOF4_6.51N 1.34N 0V.30N 1.txt' $FIRST 4 X 72 CAM CELL BLOCK .INCLUDE 'ML_GOF4_5.8V.2.41N 1.txt' .1.

TXT' .TXT' .INCLUDE 'WORD10M14.INCLUDE 'SLD10.TXT' $16 CAM CELL IN A ROW WHERE 2 MISS TO DATA 1010101010101010 .TXT' .INCLUDE 'WORD10M13.INCLUDE 'WORD10M6.txt' *MODEL .TXT' .TXT' .txt' .TXT' .INCLUDE 'WORDX.TXT' .INCLUDE 'WORD10M9.INCLUDE 'WORD10M11.txt' .INCLUDE 'BYTEX.txt' .INCLUDE 'WORD10M5.TXT' .INCLUDE 'WORD10M7.INCLUDE 'ML_GOF4_14.INCLUDE 'WORD10M12.INCLUDE 'WORD10M10.INCLUDE 'BYTE10M8.INCLUDE 'WORD10M4.INCLUDE 'ML_GOF4_12.txt' .INCLUDE 'WORD10M8.INCLUDE 'WORD10M15..TXT' .TXT' .INCLUDE 'SLDET.INCLUDE 'ML_GOF4_15.TXT' $ 8 CAM CELL IN ROW WHERE 10101010 IS STORED *****WORD WITH MISS .INCLUDE 'TCAMX.INCLUDE 'WORD10M2.TXT' .TXT * MY MLCS WITH TWO TRANSISTORS .TXT' *WORD =X .TXT' .txt' $SEARCH LINE DATA .INCLUDE 'WORD10M16.TXT' $ 16 CAM CELL IN A ROW WHERE 1010101010101010 IS STORED .INCLUDE 'ML_GOF4_13.TXT' $DATA ENTER ENABLE NMOS *TCAMS .INCLUDE 'WORD10M1.TXT' .SUBCKT MYMLCS 1 MLC MLPB MLP MLV ML 123    .TXT' .TXT' $16 CAM CELL IN A ROW WHERE 1 MISS TO DATA 1010101010101010 .TXT' $ TERNARY CAM WHERE 0 IS STORED $ TERNARY CAM WHERE 1 IS STORED $ TERNARY CAM WHERE X IS STORED $ 16 CAM CELL IN A ROW WHERE X IS STORED $ 8 CAM CELL IN ROW WHERE X IS STORED *WORD= 1010101010101010 & BYTE=10101010 .INCLUDE 'TCAM0.INCLUDE 'TCAM1.END MYMLCSNEW.TXT' .INCLUDE 'tsmc018.INCLUDE 'WORD10.TXT' .INCLUDE 'BYTE10.INCLUDE 'ML_GOF4_16.txt' .TXT' .lib' .INCLUDE 'WORD10M3.

1.1.30N UIC .15N x.sp TCAM Circuit .18U W = 0.ENDS MYMLCS     A.TXT' .txt' *MATCHLINE PRECHARGE & CHARGE CONTROLLER BLOCKS .75N x..75N 0.0.0.77N 0. E.7V *MEASURE THE SL AND ML POWER .63N 0.48N x.65N x.29N 0.14N 0.0.90N x.65N x.TRAN 20P 2.48N x.txt' *SENSE AMPLIFIER BLOCK .0.54U *MATCHLINE CURRENT SAVING M2 ML MLC MLV MLV cmosp L =0.77N x.1.1.65N 0.8 VDD 1 0 DC x VMLC MLC 0 PWL 0 0.*MATCHLINE PRECHARGE TRANSISTOR MMLP ML MLP 0 0 cmosn L =0.63N 0.15N 0.30N 0V VMLP MLP 0 PWL 0 x.90N 0V.1.0.1.2.1.INCLUDE 'mcamxmlcs64_lna2.50N 0.50N x.50N 0.30N 0 *Voltage sources to charge matchlines .1.PARAM x=1.g.48N 0..1.1.INCLUDE 'mcamxsa64.92N x...1.15N 0.50N x.65N x.30N 0 VSLDE SLDE 0 PWL 0 0.29N 0.48N 0.INCLUDE 'vmlv64.65N 0V.TXT' $ML CHARGE CONTROLLER BLOCK .1.30N x VMLCB MLCB 0 PWL 0 x.1.29N x.2.48N 0..1.2.1.2.15N x.0.2.1.63N 0.txt' 124    .63N x.14N x.63U .1.2. MLV00 is to charge matchline ML00 .IC V(MLV01)=1.29N x.30N x VMLPB MLPB 0 PWL 0 0..1.1.18U W = 0.63N x.INCLUDE 'MYMLCS_lna2.2.0.INCLUDE 'MEAS_MCAM32.2.1.15N 0.2.TXT' * VCC AND PRECHARGE VOLTAGES .50N x.1.INCLUDE 'MLSA_lna2.1.2..29N x.3 HSpice code for improved noise scheme [chapter 6]  mcam64_72_lna2.92N 0.14N x.

txt' .INCLUDE 'ML_GOF4_15.INCLUDE 'ML_GOF4_1.INCLUDE 'BYTEX.TXT' .txt' .TXT' .INCLUDE 'SLD10.txt' $SEARCH LINE DATA .TXT' $ 8 CAM CELL IN ROW WHERE 10101010 IS STORED *****WORD WITH MISS .TXT' .txt' .txt' .INCLUDE 'WORD10.INCLUDE 'WORD10M3.txt' .TXT' .TXT' $ TERNARY CAM WHERE 0 IS STORED $ TERNARY CAM WHERE 1 IS STORED $ TERNARY CAM WHERE X IS STORED $ 16 CAM CELL IN A ROW WHERE X IS STORED $ 8 CAM CELL IN ROW WHERE X IS STORED *WORD= 1010101010101010 & BYTE=10101010 .TXT' $16 CAM CELL IN A ROW WHERE 1 MISS TO DATA 1010101010101010 .TXT' .TXT' $16 CAM CELL IN A ROW WHERE 2 MISS TO DATA 1010101010101010 .TXT' $DATA ENTER ENABLE NMOS *TCAMS .TXT' .txt' .TXT' *WORD =X .INCLUDE 'ML_GOF4_8.*** MATCH LINE CAM CELL TOGETHER 4 LINE .INCLUDE 'ML_GOF4_13.txt' .INCLUDE 'WORD10M13.INCLUDE 'TCAMX.INCLUDE 'WORD10M11.txt' .INCLUDE 'BYTE10.TXT' .TXT' .TXT' .INCLUDE 'TCAM1. ML_GOF4_2=MATCH LINE_ GROUP OF 4_2 .txt' .TXT' $ 16 CAM CELL IN A ROW WHERE 1010101010101010 IS STORED .txt' .INCLUDE 'WORD10M15.INCLUDE 'WORD10M5.TXT' .INCLUDE 'ML_GOF4_12.txt' .INCLUDE 'ML_GOF4_14.txt' .TXT' .INCLUDE 'WORD10M10.INCLUDE 'WORD10M6.INCLUDE 'WORD10M12.INCLUDE 'WORDX.txt' .INCLUDE 'WORD10M9.INCLUDE 'ML_GOF4_11.INCLUDE 'SLDET.TXT' .INCLUDE 'ML_GOF4_5.TXT' 125    .INCLUDE 'WORD10M2.INCLUDE 'ML_GOF4_9.INCLUDE 'ML_GOF4_4.INCLUDE 'ML_GOF4_3. ML_GOF4_1=MATCH LINE_ GROUP OF 4_1 .INCLUDE 'WORD10M8.txt' $2ND 4 X 72 CAM CELL BLOCK .INCLUDE 'ML_GOF4_16.INCLUDE 'WORD10M4.INCLUDE 'ML_GOF4_6.INCLUDE 'TCAM0.TXT' .INCLUDE 'ML_GOF4_2.INCLUDE 'ML_GOF4_10.INCLUDE 'WORD10M14.txt' $FIRST 4 X 72 CAM CELL BLOCK .TXT' .INCLUDE 'ML_GOF4_7.TXT' .txt' .INCLUDE 'WORD10M1.INCLUDE 'WORD10M7.

18u W = 0.SUBCKT MYMLCS 1 MLV MLC MLCB MLP MLPB ML *MATCHLINE PRECHARGE TRANSISTOR M1 ML MLP 0 0 CMOSN L =0.END MYMLCS_lna2.18u W = 0.TXT' .27u M7 MID2 MLPB 1 1 CMOSP L =0.18u W = 0.18u W = 0.27u M6 MID2 MLC 0 0 CMOSN L =0.ENDS MYMLCS mcamxmlcs64_lna2.TXT .63u M5 MID1 MLCB MID2 0 CMOSN L =0.26u M3 MID1 ML 0 0 CMOSN L =0.txt XMLCS00 1 MLC MLPB MLP MLV00 ML00 MYMLCS $FOR ML00 XMLCS01 1 MLC MLPB MLP MLV01 ML01 MYMLCS $FOR ML01 XMLCS02 1 MLC MLPB MLP MLV02 ML02 MYMLCS XMLCS03 1 MLC MLPB MLP MLV03 ML03 MYMLCS XMLCS04 1 MLC MLPB MLP MLV04 ML04 MYMLCS XMLCS05 1 MLC MLPB MLP MLV05 ML05 MYMLCS XMLCS06 1 MLC MLPB MLP MLV06 ML06 MYMLCS XMLCS07 1 MLC MLPB MLP MLV07 ML07 MYMLCS XMLCS08 1 MLC MLPB MLP MLV08 ML08 MYMLCS XMLCS09 1 MLC MLPB MLP MLV09 ML09 MYMLCS XMLCS10 1 MLC MLPB MLP MLV10 ML10 MYMLCS XMLCS11 1 MLC MLPB MLP MLV11 ML11 MYMLCS XMLCS12 1 MLC MLPB MLP MLV12 ML12 MYMLCS XMLCS13 1 MLC MLPB MLP MLV13 ML13 MYMLCS XMLCS14 1 MLC MLPB MLP MLV14 ML14 MYMLCS XMLCS15 1 MLC MLPB MLP MLV15 ML15 MYMLCS XMLCS16 1 MLC MLPB MLP MLV16 ML16 MYMLCS XMLCS17 1 MLC MLPB MLP MLV17 ML17 MYMLCS XMLCS18 1 MLC MLPB MLP MLV18 ML18 MYMLCS XMLCS19 1 MLC MLPB MLP MLV19 ML19 MYMLCS XMLCS20 1 MLC MLPB MLP MLV20 ML20 MYMLCS XMLCS21 1 MLC MLPB MLP MLV21 ML21 MYMLCS XMLCS22 1 MLC MLPB MLP MLV22 ML22 MYMLCS XMLCS23 1 MLC MLPB MLP MLV23 ML23 MYMLCS XMLCS24 1 MLC MLPB MLP MLV24 ML24 MYMLCS XMLCS25 1 MLC MLPB MLP MLV25 ML25 MYMLCS 126    .54u M4 MID1 ML 1 1 CMOSP L =0.INCLUDE 'BYTE10M8.18u W = 1.63u .INCLUDE 'WORD10M16.txt' *MODEL .63u *MATCHLINE CURRENT SAVING M2 ML MID2 MLV MLV CMOSP L =0..INCLUDE 'tsmc018.18u W = 0.18u W = 0.lib' .

ENDS MLSA 127    .27U .SUBCKT INVTR VCC IN OUT MI1 OUT IN VCC VCC cmosp L = 0.ENDS INVTR .18U W = 0.18U W = 0.18U W = .18U W = 0.63U MI2 OUT IN 0 0 cmosn L =0.XMLCS26 1 MLC MLPB MLP MLV26 ML26 MYMLCS XMLCS27 1 MLC MLPB MLP MLV27 ML27 MYMLCS XMLCS28 1 MLC MLPB MLP MLV28 ML28 MYMLCS XMLCS29 1 MLC MLPB MLP MLV29 ML29 MYMLCS XMLCS30 1 MLC MLPB MLP MLV30 ML30 MYMLCS XMLCS31 1 MLC MLPB MLP MLV31 ML31 MYMLCS XMLCS32 1 MLC MLPB MLP MLV32 ML32 MYMLCS XMLCS33 1 MLC MLPB MLP MLV33 ML33 MYMLCS XMLCS34 1 MLC MLPB MLP MLV34 ML34 MYMLCS XMLCS35 1 MLC MLPB MLP MLV35 ML35 MYMLCS XMLCS36 1 MLC MLPB MLP MLV36 ML36 MYMLCS XMLCS37 1 MLC MLPB MLP MLV37 ML37 MYMLCS XMLCS38 1 MLC MLPB MLP MLV38 ML38 MYMLCS XMLCS39 1 MLC MLPB MLP MLV49 ML39 MYMLCS XMLCS40 1 MLC MLPB MLP MLV40 ML40 MYMLCS XMLCS41 1 MLC MLPB MLP MLV41 ML41 MYMLCS XMLCS42 1 MLC MLPB MLP MLV42 ML42 MYMLCS XMLCS43 1 MLC MLPB MLP MLV43 ML43 MYMLCS XMLCS44 1 MLC MLPB MLP MLV44 ML44 MYMLCS XMLCS45 1 MLC MLPB MLP MLV45 ML45 MYMLCS XMLCS46 1 MLC MLPB MLP MLV46 ML46 MYMLCS XMLCS47 1 MLC MLPB MLP MLV47 ML47 MYMLCS XMLCS48 1 MLC MLPB MLP MLV48 ML48 MYMLCS XMLCS49 1 MLC MLPB MLP MLV49 ML49 MYMLCS XMLCS50 1 MLC MLPB MLP MLV50 ML50 MYMLCS XMLCS51 1 MLC MLPB MLP MLV51 ML51 MYMLCS XMLCS52 1 MLC MLPB MLP MLV52 ML52 MYMLCS XMLCS53 1 MLC MLPB MLP MLV53 ML53 MYMLCS XMLCS54 1 MLC MLPB MLP MLV54 ML54 MYMLCS XMLCS55 1 MLC MLPB MLP MLV55 ML55 MYMLCS XMLCS56 1 MLC MLPB MLP MLV56 ML56 MYMLCS XMLCS57 1 MLC MLPB MLP MLV57 ML57 MYMLCS XMLCS58 1 MLC MLPB MLP MLV58 ML58 MYMLCS XMLCS59 1 MLC MLPB MLP MLV59 ML59 MYMLCS XMLCS60 1 MLC MLPB MLP MLV60 ML60 MYMLCS XMLCS61 1 MLC MLPB MLP MLV61 ML61 MYMLCS XMLCS62 1 MLC MLPB MLP MLV62 ML62 MYMLCS XMLCS63 1 MLC MLPB MLP MLV63 ML63 MYMLCS MLSA_lna2.27U MSA2 MSA1D MLPB 1 1 cmosp L =0.18U W = 0.54U .SUBCKT MLSA 1 ML MLP MLPB MLSO MSA1 MSA1D ML 0 0 cmosn L =0.TXT .63U XSA 1 MSA1D MLSO INVTR MSA3 MSA1D MLSO 1 1 cmosp L =0.

It is a powerful program that is used in IC and board-level design to check the integrity of circuit designs and to predict circuit behavior. Click on Next. 3. Double click the file “Setup. B. [1] HSpice is one of the most prominent commercial versions of SPICE which is now owned by Synopsys. click again on Next or simply click on Next for default destination folder. B.1 INTRODUCTION SPICE (Simulation Program with Integrated Circuit Emphasis) is a general-purpose analog electronic circuit simulator. By browsing the destination folder.1 Fig. 128    .1 2.exe”.APPENDIX B HSPICE BASICS B.2 INSTALLATION AND USAGE OF HSPICE 2007 1. A window will appear like Fig. B.

B. Now installation will be started. click on Ok. click on the Next button. B. click on Ok. 129    . When the window like Fig. When the window like Fig. As in Fig. B. selecting “Typical Setup”. 6.4. Fig.2.3 6. Click on Next-> again on Next -> and again on Next. B. B.3 appear.4 appears.2 5. Fig.

dat” and click on Ok. 8.Fig. 130    . 11. 12. B.4 7.5 will appear. B. Click on Simulate. B. Click on Finish and computer will be restarted. 10. By clicking “Avanwaves”.B. A window like Fig.6. Fig.sp file.03_Win_setup_w_license\Disk1\crack\license. Now simulation will be completed.5 9.sp file in a directory. 14. If it wants any license file. 13. browse “your directory\hspice_vZ2007.03. Click on Open and browse for the directory of the . Click Start -> All programs -> HSPICE Z-2007. you will get a window like Fig. Write a simple Hspice code and save as .03 -> HSPUI z-2007.

1. Control lines   Command lines that you use to control the behavior of HSPICE. Title line   Title  line  is  always  the  first  line  of  the  input  file.3.3. Then a list will appear on Box of “Types” and “Curves”.2.  Since  this  line  is  echoed  back  in  the  outputfile  for  the  page  header.3.Fig.3. Element description   Will be discussed in more detail later.   B. There may be “DC:*****” according to analysis type.1.1.  it  is  a  very  good  place  to  describe  what  this  simulation  is  for.1.   B.4.1. The resultant graph will appear on Black window.3. Input File  •  HSPICE input is composed of (mainly) four part.3 BASIC RULES OR QUICK MANUAL [2] B.   B. 17. Click on the curve you want to watch.END   131    . .6 15. Click on the line like “Transient: Tcam circuit”. B.  HSPICE  simply  neglects  it. 16. B.1.3.   B.

 source and bulk  to node 3.END line is ignored. gate to 1. AS.2.7 .Anything after the . add its threshold voltage.     B.1. Area for the source and drain are 30*10E‐12. The simplest for of MOS  model definition would be :     .   * Comment   Any line starting with * is considered as a comment. length 1 micron.MODEL NCH NMOS     The above line tells you that the mos type NCH is a NMOS device. L : Width and Length of MOS   AS.1. PD : the peripheral length of source. Element Description  B. drain region     You will need to specify AD.     (Example)     M100 4 1 3 3 NCH W=10u L=1u AD=30p AS=30P PD=16u PS=16U     defines a MOS transistor named M100 with its drain connected to node 4. drain region(optional)   PS. MOS   Any line that starts with M is considered as the description line for a MOS transistor. and PS if you are concerned about the parasitic capacitances of  the drain and source area.3.1. PD..     132    . and their  peripherals. at least.. so you may want to. you need to define its model. It doesn't say anything more than  that. AD : the area of the source.     MODEL NCH NMOS   + VT0 = 0.     MXX Node_D Node_G Node_S Node_B MODEL_NAME   + W=W_VALUE L=L_VALUE [AD=AD_VALUE] [AS=AS_VALUE]   + [PD=PD_VALUE] [PS=PS_VALUE]     W.3.2.3.2. Active device   B. Now since the model is NCH.   * Line continuation   Any line that starts with + sign is considered as the continuation of the previous line. Its width is 10.

2.3.1.4. a line like the following:   V1 10 11 pulse 0 5 10n 1n 2n 4n 10n   says that there's a voltage source connected between node 10 and node 11. however. with leading time (delay) of 10n.3.. v1 at t=t1.2.3 Diode   DXX N_anode N_cathode MODEL   B.3.3.   B. 1ns rising time. if you write   V1 10 11 pulse 5 0 10n 1n 2n 4n 10n   now the 1ns is falling time. Dependent source   133    . v_amp is the amplitude.3.2. not rising time since V1 is originally 5v instead of 0V. Pulse   Most frequently used time‐varying waveform is a pulse.3.2. Sine   Sin is for sinusoidal waveform. PWL   PWL is used for piecewise linear waveform.   VNAME n1 n2 pwl t0 v0 t1 v1 t2 v2 t3 v3 . which toggles between  0V and 5V. Passive Device   RXX N1 N2 Rvalue ‐‐‐‐ Resistor   CXX N1 N2 Cvalue ‐‐‐‐ Capacitor   LXX N1 N2 Lvalue ‐‐‐‐ Inductor   B.3.  voltage  source  and  current  source. Most flexible. and so on.1.3.2.B. 2ns falling time and 4ns high time.2. For example.3. freq is the frequency   B..   The value of VNAME is v0 at t=t0. but need many parameters to use.2.3.     B.3.2.3. Bipolar transistor   QXX N_Collector N_Base N_Emitter MODEL   B.2.2.1.     Be careful. Independent source   There  are  two  types  of  independent  source. and  period 10ns.   B.2.   V1 10 0 sin v_off v_amp freq [phase]   v_off is offset value.3.

  The  four  kinds  of  inear  dependent  sources  are :   VCCS : voltage‐controlled current source (G element)   VCVS : voltage‐controlled voltage source (E element)   CCCS : current‐controlled current source (F element)   CCVS : current‐controlled current source (H element)   They are described in the following form. AC analysis   .DC VARIABLE start_value stop_value increment_value   HSPICE will step throught the VARIABLE value start from the start_value in increment of  increment_value until the VARIABLE reaches the stop_value. Analysis B.AC LIN n_point fstart fstop   . and there are n_point points within one octave if OCT  is used.PLOT control line which will cause an output  to be written to the HSPICE output. and ends when frequency =  fstop. frequency is sweeped from fstart.3.DC control should be a .PRINT or . The  frequency of any AC source in the circuit is set to fstart.AC OCT n_point fstart fstop   HSPICE calculates the operating condition.   GXX N+ N‐ NC+ NC‐ Gain   EXX N+ N‐ NC+ NC‐ Gain   FXX N+ N‐ NC+ NC‐ Gain   HXX N+ N‐ NC+ NC‐ Gain     B. you use the .3.DC control line.3.3. Then it performs ac analysis.Dependent  sources  are  very  useful  elements  in  HSPICE. The frequency increment value is defined by  the increment option.   B. DC analysis   When you want to perform a DC analysis.PLOT or .AC DEC n_point fstart fstop   . there are  going to be n_point points within one decade.2.PRINT or . If DEC is used.AC statement should be a .     Associated with any .3.1. You need to have at least one AC independent source. Total number of frequency points used in this simation is n_point. Its format is   . and form a small‐signal equivalent circuit for the given  netlist.3.PROBE.     Associated with any .     Suppose you have a simulation setup like the following :   134    . If LIN is used.

3..4 References [1] Online: http://en..  use  a smaller number.engr.3.   will  print  out  the  transfer  gain  from  the  source  specified  as  vin  to  the  voltage  of  node  10.Vin 1 0 DC=1 AC   .   B...3.   .  It  is  also  used  in  the  internal  time‐step  control  algorithm. It will print out the phase of node 10.3.  so  when  a  accurate  simulation  is  required.4 TF analysis   .uiuc.  The  internal  timing  step  is  adjusted  automatically  to  get  the  required  accuracy. too.3.TRAN t_increment t_stop   HSPICE  will  start  simulating  the  circuit  from  time  0  to  t_stop. there will be 10 points (in log scale) within each decade.wikipedia.     The value specified when vin is defined (3 volt in this example) is used for bias calculation. then the printed output Vdb(10) will be the gain of your circuit  from node 1 to 10.AC DEC 10 10 100MEG   ..  Parameter  t_increment  is  used  for  output  printout.   VIN 1 0 3v   .     If node 1 was the input for the circuit. Transient analysis.TF v(10) vin   .     B..edu/OCEE/webcourses/ece497am/quick_hspice.org/wiki/HSPICE  [2] Online: http://www.print ac vdb(10) vp(10)   Then HSPICE will print out the voltage at node 10 with various frequency from 10Hz to 100MegHz in  decibel scale.3.html#misc            135    .   B. Since 'DEC 10' is used.