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A Senior Project Presented to The Faculty of the Electrical Engineering Department California Polytechnic State University, San Luis Obispo
In Partial Fulfillment Of the Requirements for the Degree Bachelor of Science
By John Brewer, Jr. And Kamaljit Bagha June, 2010
© 2010 John Brewer, Jr. and Kamaljit Bagha
Table of Contents
Section Title Page Table of Contents List of Table and Figures Acknowledgements I. II. 2.1 III. IV. 4.1 4.2 4.3 4.4 V. 5.1 5.2 5.3 5.4 5.5 INTRODUCTION BACKGROUND Predator® - Too Versatile For Its Own Good REQUIREMENTS DESIGN Inverter Project Design Overview The Power Stage The PWM Control Circuit and Signal Flow The LC Output Filters CONSTRUCTION PWM Control Circuit Assembly Inductor Construction Wire Harnesses, Connectors, and Cable Fabrication Power Plane Construction Enclosure Fabrication Page i ii iv vi 1 3 3 5 7 7 10 17 28 32 32 33 35 36 36
5.6 VI. VII. VIII.
System Assembly TESTING CONCLUSION AND RECOMMENDATIONS BIBLIOGRAPHY
37 38 45 48
Appendices A. Schematic B. Bill of Materials C. Circuit Board Layout D. Circuit Board IC and Component Locations E. Hardware Configuration and Layout 50 66 69 70 71
6 4.2 4.1 3.2 B. originally named “Predator B” IGBT Half-Bridge Configuration Block Diagram of Inverter Project Bootstrap Supply Topology with Protection Nomenclature Used for IGBT Switching Transition PWM Control Signal Flowchart dsPIC-based Function Generator Passive Component Nomenclature for UC3637… Generating a Trigger Pulse Bode Plot of Second Order LC Filter Portion of Circuit Board Layout Graphic Wire Wrapping Inductor Bobbin Tightly Wound Inductor 3 4 7 9 11 15 18 19 21 25 28 32 33 33 34 MIL-STD-704F AC System Requirements  Summary of Inverter Project Requirements Bill of Materials and Donated Items Page 5 6 66 .1 Figures 2.iv List of Tables and Figures Table 3.2 4.8 4.9 5.2 5.4 4.3 4.1 5.4 MQ-1 Predator Drone MQ-9 Reaper Drone.1 4.5 4.3 5.7 4.1 2.
1 6.7 6.3 6.9 6.5 5.2 Wood Handle to Support Bobbin Finished Inductor with Connectors and Mylar Tape Fabricated Wire Harnesses Top and Bottom Sides of Copper-Clad Board Inverter System Assembly Ideal Inverter Pspice Simulation Output Voltage Waveform of Ideal Inverter Simulation IGBT Gate Driver and Half-Bridge Pspice Simulation High-side (green) and low-side (blue) IGBT… Adjustable Three-Phase Sinusoidal Reference… Trigger Pulse successfully generated by AD823AN… Square wave with 97% duty cycle successfully generated… Three-phase and Neutral-phase Duty Cycle limited… Three-phase Inverter Output Voltage referenced… Three-phase Inverter Output Voltage referenced… Microsoft PowerPoint Circuit Board Layout IC and Component Circuit Board Location Hardware Configuration and Layout Test Bench Setup 34 34 35 36 37 38 39 39 40 42 42 43 43 44 44 69 70 71 72 .1 E.4 6.8 6.8 5.2 6.v 5.9 6.5 6.6 6.7 5.10 C.1 D.6 5.1 E.
Dr. for providing and funding a challenging project for us to work on and offering the technical support needed to complete this project. and Kamaljit Bagha . Cal Poly EE Department Electronics Technician. equipment. San Luis Obispo. as our faculty advisor for this project. Cal Poly mechanical engineer and friend. We appreciate him sharing his knowledge and insight of the broad range of topics that this project covers and have been inspired to work hard and never stop learning as electrical engineers. John (Jeff) Brewer. His teaching curriculum and techniques significantly contributed to our ability to “Learn by Doing” here at Cal Poly. testing. Taufik. His dedication and excellence as a teacher both in the classroom and lab have equipped us with a solid foundation of knowledge and understanding in the field of power electronics. for his assistance in metal parts fabrication Our families for supporting our educational endeavors. Professor of Electrical Engineering at California Polytechnic State University. Inc. Cole Brooks. John Brewer. Jaime Carmo. Jr. Mr. Sincerely.Acknowledgements Acknowledgements We would like to thank – Mr. Mr. for his support and generous donation of time. and parts throughout the construction. Director of Electrical Engineering for the Aircraft Systems Group at General Atomics Aeronautical Systems. and fabrication stages of our project.
variable speed drives. power MOSFETs in the late 1970s. bipolar transistors in the 1960s. in 1952. and power supplies. The successive arrival of thyristors in 1957. INTRODUCTION With the advent of the first power rectifier by an American engineer and applied physicist. and IGBTs in the 1980s led to the rapid advancement of power electronics in all fields of electrical engineering .1 I. Robert Hall. More efficient than linear power regulation which uses variable resistance to regulate power flow. PWM is a technique where the duty cycle of the semiconductor switch is manipulated to control power flow through the switch. a new form of power control and conversion was born – Power Electronics. These fields include utility power distribution. As a result. switching semiconductor devices by using a technique called “Pulse Width Modulation (PWM)” is the method used in a modern “switching” or “switched-mode” power supply (SMPS). the output voltage delivered to the load can be . Power electronics is unique in its method of power control and conversion in that it is based on the switching fully-on and fully-off of semiconductor devices to regulate power flow. and especially aircraft electronics because of the small size of power electronic components. A few applications of power electronics in these fields include power quality controllers. industrial electronics.
Transformers are used in the design of isolated converters to provide flexibility in circuit design by allowing for separate (isolated) input and output current return paths to “ground. For our application. It uses the common method of Pulse Width Modulation to switch Insulated Gate Bipolar Transistors (IGBTs) to control the flow of power from ±DC input voltage “rails” to three-phase. In the next section of this report. sinusoidal AC output voltage.” Non-isolated converters. simply. do not use transformers and the input current ground is used as the ground for the output load current. an inverter. There are two types of converter topologies used in SMPS design – isolated and non-isolated. however. we have designed a non-isolated SMPS that produces AC output voltage from DC input voltage – this is known as a DC/AC converter or.2 well regulated to produce a fixed Direct Current (DC) voltage or a desired Alternating Current (AC) voltage. . we will present the background and application of our inverter design.
S. This project began the development process for a high-voltage three-phase AC power supply for use on any of the Predator® Unmanned Aircraft Systems (UAS) that GA-ASI manufactures. Army. 2. and communications equipment can be mounted.1 Predator® – Too Versatile For Its Own Good Predator® aircraft like the ones shown in Figure 2. Customs and Border Protection. search and rescue. Fig. 2. Predator® systems are versatile aircraft platforms upon which an increasingly large array of electronic device payloads like sensors.1 and Figure 2. Central Intelligence Agency. (GA-ASI). the Director of Electrical Engineering at General Atomics Aeronautical Systems. weapons.3 II. U. and surveillance. They are popular for their wide range of applications including remote sensing. sinusoidal inverter project was sponsored by Jeff Brewer.1 – MQ-1 Predator Drone Source: Public Domain . reconnaissance. and NASA.2 are used by multiple branches of the United States’ military and homeland security including the Air Force. Inc. BACKGROUND Our three-phase. weapons delivery. The purpose of this project was to design and build a proof-of-concept high-power switched-mode inverter.
2. the weight of the cables in the aircraft needed to deliver 28 VDC power to these payloads exceeds practicality. These plans include the provision of a 270VDC system and a three-phase AC system as outlined in the next section of this report. It is estimated that the cable weight required to distribute power on the aircraft will be reduced by a factor of ten when high-voltage power is provided .4 Currently. plans to provide highvoltage power systems in accordance with MIL-STD-704F on Predator® aircraft are in effect.2 – MQ-9 Reaper Drone. Because these aircraft are required to support an increasing number of electronic payloads. originally named “Predator B” Source: Public Domain . Fig. to counteract this problem. these devices are powered by 28 VDC power on the aircraft – one of three standard aircraft power systems prescribed by MIL-STD-704F . So.
REQUIRE REQUIREMENTS The purpose of our project was to design and build a non-isolated DC/AC SMPS capable of supplying 10 kW for a standard three-phase AC aircraft power system.1 – MIL-STD-704F AC System Requirements  Characteristics Steady State Voltage: Voltage Unbalance: Voltage Modulation: DC Component: Voltage Phase Difference: Steady State Frequency: Frequency Modulation: Peak Voltage: Limits 108.5 VRMS (maximum) +0.1 Volts 116° to 124° 393 Hz to 407 Hz 4 Hz ±271. However.8 Volts .1.0 VRMS (maximum) 2. Because MIL-STD-704F also prescribes AC system requirements like the sample shown in Table 3.5 III.0 VRMS to 118. the production level version of our inverter will require the use of closed-loop feedback to provide adequate line and load regulation. so an open-loop system was required. Table 3.1 to -0. According to MIL-STD-704F. “AC systems shall provide electrical power using single-phase or three-phase wire-connected grounded neutral systems.0 VRMS 3. The voltage waveform shall be a sine wave with a nominal voltage of 115/200 volts [115 VRMS] and a nominal frequency of 400 Hz” . designing a closed-loop system was beyond the scope of this project.
In the following section of this report. Sinusoidal 400 Hz 10 kW .2. variable frequency engine alternator power will be rectified and regulated to produce ±190 VDC rails from which the inverter will draw its power .2 – Summary of Inverter Project Requirements Nominal System Requirements Converter Topology: Input Voltage: Output Voltage: Output Voltage Waveform: Steady State Frequency: Maximum Output Power: Non-Isolated SMPS ±125 VDC 85 VRMS AC Three-Phase. the production level version of our inverter will be powered by the engine alternator on the aircraft.6 Lastly. we will present a system overview of our inverter project followed by a more detailed discussion of the circuit design process. variable voltage. The nominal requirements of our inverter project are summarized below in Table 3. This requirement was limited by the available test equipment in Cal Poly’s EE Department Power Electronics Lab. The three-phase. Since this rectification and regulation of engine alternator power is beyond the scope of this project. Table 3. it was required that our proof-of-concept inverter work from ±125 VDC rails for three-phase operation given 10Ω resistive loads.
signal flow. they connect the load to the +DC and -DC Rails. 4. 4.1. and discrete components used. DESIGN This section of our report represents a majority of the work that went into this project – circuit design.7 IV. respectively.1 Inverter Project Design Overview The design of our three-phase sinusoidal inverter is based on the PWM switching of N-Channel IGBTs connected in a half-bridge configuration as shown in Figure 4. . In this section. Jr. Because the output voltage is effectively an amplified version of the PWM Control Input. we will present an overview of our inverter project followed by a series of discussions covering the details of the circuit design.1 – IGBT Half-Bridge Configuration Source: John Brewer. this stage of the inverter system can be considered the Fig. Since the output is connected to one of two voltage polarities during this method of switching.2. Power Amplification stage and is shown in the System Block Diagram in Figure 4. it is known as Bipolar Switching. As the high-side and low-side IGBTs are complementarily switched fullyon and fully-off.
These will be discussed in Section 4.3. An important characteristic to note about our inverter design is the fourth IGBT Half-Bridge “leg” which is used to create a virtual ground (neutral) through which phase currents from an unbalanced three-phase load can return to the DC input supply. A thorough discussion of the PWM Control Circuitry will be presented in Section 4. . establishing the switching frequency.126.96.36.199 and will be discussed in Section 4. The creation of this neutral return is necessary in the case that a bipolar DC supply with ground connection is unavailable and a unipolar DC supply must be used.2. The final piece of our inverter design is the inductor/capacitor (LC) output filters on each phase.8 The IGBT Gate Drivers and Floating Bootstrap Supply topology required to drive N-Channel IGBTs in this configuration are also indicated in Figure 4. The PWM Control Input is generated by the PWM Control Circuit block. creating PWM signals. The LC output filters were designed to smooth the PWM output of the Power stage and filter out high-frequency harmonics introduced by IGBT switching. The PWM Control Input to this neutral leg will have a nominal 50% duty cycle. The PWM Control Circuitry is responsible for generating the sinusoidal reference waveforms. limiting the duty cycle of the PWM signals. creating a voltage that is one-half the DC supply voltage upon which the three-phase sinusoidal output voltages will be centered.2 of this report. and interfacing logic-levels.
and Kamaljit Bagha 9 .2 – Block Diagram of Inverter Project Source: John Brewer. Jr.Fig. 4.
and Neutral. we will discuss the floating bootstrap supply topology required for (Eq. using these IGBTs will fulfill our requirement to design a threephase inverter capable of supplying 10kW with an output voltage of 115VRMS. Four identical half-bridge legs form the foundation of our three-phase inverter and are responsible for controlling power flow from the DC Input Supply to each phase output voltage – Phase A. WARP2 Series IGBT with Ultrafast Soft Recovery Diode from International Rectifier (IR). These IGBTs are high-speed. Jeff Brewer donated the IGBTs that were to be used for this project – IRGP50B60PD1. these IGBTs can source 33A with maximum turn-on and turn-off delay times of 40ns and 150ns.1.10 4. With an operational output voltage of 115VRMS. the resulting power output capability of all three inverter phases combined can then be calculated to be: ܲை் = 3 ∗ ܫை் ∗ ܸை் ∴ ܲை் = 3 ∗ 33 ∗ ܣ115ܸோெௌ = 11. high-power. Phase B. the Power Stage consists of two IGBTs connected in a Half-Bridge configuration. In the next section. SMPS. N-Channel IGBTs capable of withstanding a collector-to-emitter voltage of 600V. Driven with a gate-to-emitter voltage of 15V. respectively . Phase C.385ܹ݇ In conclusion.2 The Power Stage As mentioned in Section 4. 4-1) .
the same supply would be unable to turn on the corresponding high-side device as the high-side emitter follows the output voltage of the half-bridge – a much larger voltage than the supply voltage.3. providing the Fig. While this does not present a problem for turning on low-side devices with a power supply referenced to the –DC rail. 4. . these N-channel devices require a charge applied to the gate that is positive with respect to the emitter such that (VGE > VTH).1 Bootstrapping. However. IGBT Gate Drivers. Due to the charge storage characteristics of a capacitor. VCC. and design measures taken to protect the IGBTs. a bootstrap capacitor is connected from the power supply. Therefore. 4. the IGBT Gate Driver design process.2.3 – Bootstrap Supply Topology with Protection Source: John Brewer. to the high-side emitter.11 switching N-Channel devices. a bootstrap supply topology is required. and Transient Voltage Protection N-Channel semiconductor devices are commonly used in half-bridge configurations as our IGBTs are used in the power stage of our inverter. As illustrated by the schematic of a typical bootstrap supply topology in Figure 4. the bootstrap capacitor voltage will rise +VCC above the high-side emitter. Jr.
Also note that we have incorporated the Disable pin of the Si8234BB device into our circuit design to provide the functionality of being able to turn combinations of our phase output voltages on or off . we decided to use the Si8234BB ISOdriver manufactured by Silicon Labs as our High-Voltage Integrated Circuit (HVIC) Gate Driver. However. the high-side device will turn on. while the output side can support the 15V supply used to switch our IGBTs. For our project. This recently released HVIC Gate Driver contains two completely isolated high-side/low-side drivers in one package that are each capable of sourcing 4. Because of this.12 necessary gate drive voltage to turn on the high-side device. The isolated drivers are controlled by a single PWM Control Input signal and an external resistor used to program the deadtime created between the switching of the high-side and low-side devices.0A peak output current. The input logic side of the device is 5V TTL compatible. the duty cycle of the high-side device switching must be limited and the bootstrap capacitor sized accordingly to prevent premature/uncontrolled turn-off of the high-side device. We consulted IR’s “Design Tips for Using Monolithic High Voltage Gate Drivers” during the design process for our HVIC gate drivers and floating bootstrap . When an internal switch in the Gate Driver Integrated Circuit (IC) connects node VB to the high-side gate. It will then turn off when the gate is disconnected from VB and connected to VS by internal switches in the Gate Driver IC. the high-side device will also turn off if the charge on the bootstrap capacitor is depleted due to parasitic gate current.
10V as indicated in Table 1 of the “Si823x” datasheet from Silicon Labs .13 supply . The next step in sizing the bootstrap capacitor was to consider the following factors contributing to a decrease in VBS: . we decided from Fig. we started by calculating the maximum voltage that the bootstrap capacitor voltage was allowed to drop (∆VBS) when the high-side IGBT was supposed to be on. Also.IGBT turn-on required Gate charge (QG) = . 8 of our IGBT datasheet that the minimum gate-to-emitter voltage to allow should be 11V in order to guarantee a collector-to-emitter voltage of about 2V given a collector-toemitter current around 33A.Bootstrap diode instantaneous reverse current (ILK_D) = 50μA . ∴ ∆ܸௌ = 15ܸ − 1ܸ − 11ܸ − 2ܸ ≅ 1ܸ We then confirm that VGE. To do this.Bootstrap capacitor leakage current (ILK_C) = .0mA (max) .3 .min > VBSUV. − ܸா. As a result.Output supply quiescent current (IDDAQ) = 3. To size the bootstrap capacitor.High-side on time (TH.5μs 0μA (use ceramic capacitors) (98% duty cycle at 40kHz) .IGBT Gate-Emitter leakage current (IGES) = 308nC (max) 100nA     (Eq.is the high-side supply undervoltage negative going threshold of 8.where VBSUV.on) = 24. we obtain ∆ܸௌ = ܸ − ܸி − ܸீா. we used a value of 1V for the typical forward voltage drop of the MUR460 power rectifier used to protect VCC as shown in Figure 4. 4-2) .
almost twice as big as the calculated CBOOT.min. MUR460 power rectifiers are an ideal choice for use as the bootstrap diode in our bootstrap supply design. and measures taken for protecting the IGBTs and HVIC Gate Drivers. Sufficient decoupling capacitance was added to our gate driver design by placing ceramic and electrolytic capacitors in parallel with the gate drive supply voltage very close to both the low-side Gate Driver output pins and the bootstrap diode. = ொೀಲಽ ∆ಳೄ ଷ଼ଷ ଵ (Eq. we decided to use a bootstrap capacitance of 660nF.0݉ ܣ+ 50ߤ ܣ+ 0ߤܣሻ ∗ 24. 4-4) ≅ 383݊ܨ ∴ ܥைை். = So. (Eq. The ceramic capacitor provides a fast charge tank and limits ܸ݀ൗ ݀ ݐby reducing the equivalent series resistance while the electrolytic provides a longer lasting charge tank.5ߤ ≅ ݏ383݊ܥ And the minimum size of the bootstrap capacitor can be calculated by ܥைை். . 4-3) ∴ ்ܳை் = 308݊ ܥ+ ሺ100݊ ܣ+ 3. As mentioned earlier.14 Then we have ்ܳை் = ܳீ + ൫ீܫாௌ + ܣܦܦܫொ + ܫ_ + ܫ_ ൯ ∗ ܶு. These devices were also donated to our project and can withstand a reverse voltage of 600V and have a reverse recovery time of less than 100ns . sizing of gate resistances. to account for estimation error and temperature drift. The final design issues to be mentioned regarding the design of the IGBT gate drivers are the addition of decoupling capacitors.
the switching time is defined as the time spent to reach the end of the plateau voltage resulting from charging the IGBT gate capacitances with QGC and QGE. From “Design Tips for Using Monolithic High Voltage Gate Drivers. respectively. Estimating Fig. we can calculate ܫாோீா = ொಸ ାொಸಶ ௧ೞೢ ଵହାସହ ଵଵହ௦ (Eq. 17 of our IGBT datasheet .” we can estimate the necessary size of the turn-on gate resistor by fixing the switching-time.2V from Fig.4. (Eq. and ்ܴை் ൌ ܴைேሺ௦௨ሻ ܴீ. 4-7) . 4.4 – Nomenclature Used for IGBT Switching Transition Source: International Rectifier  an appropriate switching time to be about 115ns and knowing QGC and QGE to be 105nC and 45nC. As shown in Figure 4. 4-5) ≅ 1.3ܣ ∴ ܫாோீா = And ்ܴை் ൌ ି כ ூಲೇಶೃಲಸಶ (Eq. 4-6) where Vge* is approximated to be 6.15 The process for sizing the gate resistances consisted of both calculations to derive ballpark figures and hardware experimentation.
7Ω ≅ 4Ω And following IR’s Design Tip. = ଵହି.ଷ − 2. Zener clamp diodes with a reverse voltage breakdown voltage of 16V are added across the gate-to-emitter junctions of both high-side and low-side devices.3. the design of the Power stage includes devices added to protect IGBTs and HVIC Gate Drivers from transient voltage spikes caused by parasitic inductances in the circuit. and RG. these Zener clamps protect the HVIC Gate Driver output. we have ܴீ. As a result. The purpose of this clamp device is to guarantee that VS does not exceed maximum undervoltage limits when negative voltage transient spikes are induced by parasitic inductances.on is the value for the high-side IGBT gate resistor .ଶ ଵ. we size the low-side IGBT gate resistor to be larger than the gate resistor of the high-side device – about 5Ω. sink current generated by transient voltage spikes occurring on the collector. First. This will result in softer switching of the low-side device and a reduction in magnitude of the voltage transients caused by parasitic inductances during switching. Lastly. and keep the IGBT gate-to-emitter voltage from exceeding the maximum limit of 20V . Another clamp device used is the series combination of a 16V Zener diode and MUR460 Power Rectifier positioned between the VS pin of the HVIC Gate Driver and the –DC rail also shown in Figure 4.16 Where RON(source) is 2.7Ω according to the Si8234BB datasheet. Shown in Figure 4. The production level version of our inverter will include the placement of reverse-biased transient voltage .3.
limiting the duty cycle of the PWM Control signals.3 The PWM Control Circuit and Signal Flow The PWM Control Circuit is the “brain” of our inverter project and is responsible for generating our three-phase sinusoidal reference signals. The circuit schematics for the four Power Stages of our inverter design can be found on Sheets 11. Considerations for choosing the discrete analog devices we used included availability. Due to the DC input supply test limits. we omitted these diodes from our proof-of-concept design. proven reliability. and extreme temperature tolerance for military temperature requirements. In the next section of this report. These will protect the IGBTs from damage caused by voltage transients on the DC supply rails or half-bridge output node. and interfacing logic levels. . 12. low replacement cost.17 suppression diodes with a reverse breakdown voltage <600V across the collector-toemitter IGBT terminals. ease of prototype implementation. and 14 of the system schematic in the Appendices. 13. we will discuss the PWM Control Circuit and signal flow. It was designed using discrete analog components with the exception of a Microchip dsPIC 16-bit Digital Signal Controller-based function generator. 4. producing PWM Control signals for all three-phases and neutral.
Jr. Fig.18 In this section of the report. Figure 4.5 – PWM Control Signal Flowchart Source: John Brewer. we will present a discussion of the circuit components used to perform these tasks and cover the details of the circuit design required to interface these components and generate PWM Control Input signals for the HVIC Gate Driver of each IGBT half-bridge. 4.5 illustrates the general flow of a single phase PWM Control signal. .
19 4.3. low Total Harmonic Distortion of 0. Jr. Source: John Brewer. and buffer the reference sinusoids. each having 120° of phase displacement from the others. Manufactured and donated by GA-ASI.6 supplies three-phase sinusoidal waveforms with accurate sine shape and phase displacement. but for our application they are set to have a frequency of 400 Hz and peak-topeak amplitude of 2V.003%. In order to make the amplitude of our inverter output Fig.1 Generating Three-Phase Sinusoidal Reference Signals The first step in the design of the PWM Control Circuit was to generate three sinusoidal reference voltages. we AC coupled each of the sinusoidal phase voltages from the function generator to adjustable gain. Fortunately. The TL082 op-amps were chosen because of their suitable slew rate of 13V/μs.6 – dsPIC-based Function Generator voltage waveforms adjustable. this step was already complete before we began our project. remove the DC offset from the reference sinusoids. ability to operate from . 4. The frequency and amplitude of the output sinusoids are adjustable. non-inverting amplifiers designed using TL082 JFET Input Op-Amps. Simple RC highpass filters with a cutoff frequency of 1 Hz were used for the AC coupling. the Microchip dsPIC Digital Signal ControllerBased Function Generator shown in Figure 4.
The UC3637 was chosen because of its high reliability. under-voltage lockout. 4. robustness. It is easy to program and provides a built in error amplifier. and can operate from dual power supplies .2 Generating PWM Signals from Reference Sinusoids The next step in the design of the PWM Control Circuit was to generate the PWM Control signals for each phase including neutral by comparing the reference sinusoids to a triangle wave having a frequency equal to the desired IGBT switching frequency. Using a PWM Controller IC is the most efficient way to do this. so we chose the Unitrode UC3637 Switched-Mode PWM Controller for DC Motor Drives.20 ±15V supplies. and compact 8-pin packages containing two op-amps each. This IC was “programmed” with the passive components shown in Figure 4.7 according to the following design requirements: . and widespread use in industry. We arbitrarily decided to establish the Neutral phase PWM Controller as the Master PWM device. Concurrently. The circuit schematic for this step in the PWM Control Circuit can be located on Sheet 3 of the system schematic in the Appendices.3. This was an important quality of the UC3637 since four PWM Controller ICs were required in the PWM Control Circuit and the ability to synchronize them would simplify circuit construction. multiple UC3637 ICs can be readily synchronized according to Unitrode’s Design Note about “Design Considerations for Synchronizing Multiple UC3637 PWMs” .
21 • • • Triangle Wave frequency of 40kHz (same as the IGBT switching frequency). Triangle wave amplitude of 20 VP-P (large to increase noise immunity). Consulting the Unitrode UC3637 Datasheet and following the Unitrode Application Note U-102.ହ (4-8) = 50݇Ω ≅ 47. we calculated the following  : ்ܴ ൌ ሺାಹ ሻିሺିೄ ሻ ூೄ ሺାଵ ሻିሺି ଵହ ሻ .75V (to prevent switching IGBTs when there is not enough supply voltage to fully turn them on). Modulation scheme with no deadtime (since the Si8234BB IGBT Gate Driver supplies the necessary high-side/low-side switching deadtime). 4.5݇Ω ∴ ்ܴ ൌ . • Under-voltage lockout level of 10.7 – Passive Component Nomenclature for UC3637 Master Device Programming Source: John Brewer. Fig. Jr.
as used in Eq. REQ. Using an iterative process to determine values for R1 and R5. we • • Calculated REQ Calculated the approximate bias current. Because the amplitude of the triangle wave has been designed fairly large. we note that the Unitrode Application Note U-102 suggests that the constant current used to charge the external capacitor.5 mA.ହ ூೄ (4-9) ∴ ்ܥൌ ଶ∗ସு௭∗ሾሺାଵ ሻିሺିଵ ሻሿ = 313 ≅ ܨ300 ܨ For clarity. and R5 between +VS and -VS. CT. IBIAS. This will produce a buffered triangle wave used to drive the UC3637 slave devices and the AD823AN op-amp used for generating a trigger pulse for the HCF4538B Monostable Multivibrator Since +VTH and -VTH should be symmetrical at ±10V in our application. that will be able to store enough charge to drive the input of a TL082 op-amp configured as a voltage-follower. 4-9. be within the range of 0. 0.22 ்ܥൌ ଶככሾሺାಹ ሻିሺିಹ ሻሿ . through the resistor divider created by R1. Using this higher charging current performs a secondary feature of allowing the use of a larger capacitor. we set R1 = R5 and calculate REQ (where REQ = R2 + R3 + R4) after choosing reasonable values for R1 and R5.5 mA. we programmed ISET to a value on the higher end of this range. This prevented unnecessary power loss while .3 to 0. CT. • Adjusted values accordingly to limit the bias current to an order of hundreds of microamps.
However. Following the procedure outlined in Unitrode Design Note DN-53A. ܴଶ = ܴସ = 5. required between +VTH and +VSLV.5V.ସஐ ∗ ଵ ଵହ ି ଵ (4-10) = 81.600 Ω ∴ ܴாொ = We also needed to ensure that the +VSLV node voltage indicated in Figure 4. based upon the hardware available during the construction phase of our project. we needed to determine the minimum voltage difference. or the AD823AN op-amp characteristics.4݇Ω ܴாொ = ଶ ∗ ோయ ∗ ಹ ೄ ି ಹ ଶ ∗ ଶ.23 maintaining the ability to adequately charge the PWM controller comparator inputs. requiring a ballpark resistance for R2 and R4 to be 6.7 was always less than the magnitude of the triangle wave despite any drift in resistance.1݇Ω (4-11) . As a result.3kΩ . we determined ∆Vmin to be about 1.62݇Ω Yielding ܫூௌ = ାೄ ିሺିೄ ሻ ோభ ାோమ ାோయ ାோర ାோఱ and ܴଷ = 68. the UC3637 Master PWM device characteristics. ∆Vmin. This will guarantee the generation of a trigger signal for the HCF4538B Monostable Multivibrator which is used to create a square wave with frequency equal to the triangle wave and duty cycle of 98%. ܴଵ ൌ ܴହ ൌ 20. In order to do this.
ଶஐ ା ଼. 8.4V low/+5V high. In the next sections of this report. the SD pin of the master device to the SD pins of the slave devices. and the buffered triangle wave output from the TL082 voltage-follower to pins 2. Using a 100kΩ resistor for R6. The -15V low/+15V high PWM Control Input signals are each interfaced with their respective 74AC00 CMOS NAND Gates by a current limiting resistor/voltage divider/Schottky diode network that reduces the signal to 0.24 ∴ ܫூௌ ൌ ଶ.ଵஐ ା ହ. we simply connect the +VSLV node to the +VTH slave device pins.ହ∗ሺோల ାோళ ሻ ோల ାଵହ ି ሺିଵହሻ (4-12) − ܴ = ଵ. Besides adding 0.ହ ଶ.1μF decoupling capacitors to all device pins that are tied to a fixed voltage. and 10 of the slave PWM devices. we used the equation provided in the UC3637 IC datasheet to establish an undervoltage lockout level of 10.75V. we calculated ܸௌ்ோ் = ∴ ܴ = ೄಲೃ ∗ ோల ଶ.ସஐ ≅ 250ߤܣ Lastly.ଶஐ ା ଶ. we will discuss the portions of the PWM Control Circuit that limits the duty cycle of the PWM Control Inputs to 98%. the –VSLV node to the –VTH slave device pins.ହ − 100݇Ω = 330݇Ω At this point.ହ∗ଵஐ ଶ. .ସஐ ା ହ. the simplicity of synchronizing the other three UC3637 slave devices becomes evident.
only one of the op-amps is needed by our control circuit.8. Although the AD823AN is a dual op-amp package. With the buffered triangle wave tied to the positive input and the +VSLV voltage tied to the negative input of the comparator. our PWM Control Circuit design includes the use of an AD823AN rail-to-rail FET Input op-amp as a comparator.25 4.3 Generating a Trigger Pulse As mentioned in the previous section.3. a +15V pulse with duration of about 1μs is generated when the triangle wave is at its peak and exceeds the +VSLV threshold as illustrated in Figure 4. the HCF4538B Monostable Multivibrator configured as a non- .4V low / +15V high pulse. this op-amp provides the speed needed for a short switching transition time and required no voltage level shifting to interface the ±20V buffered triangle wave.4 Monostable Multivibrator After being triggered by the trigger pulse delivered by the AD823AN comparator. This -15V low/+15V high trigger pulse is interfaced with the HCF4538B Monostable Multivibrator through a current limiting resistor and Schottky diode network that reduce the trigger Fig. 4. According to the AD823AN datasheet.3. Source: John Brewer.8 – Generating a Trigger Pulse pulse to a 0. As a result. this op-amp has a high slew rate of 22V/μs and can operate from ±15V supplies . Jr. 4.
. As illustrated in our schematic (See Appendix) we paired a 5. Since the trigger pulse is delivered every 25μs. according to the equation ܶ ൌ ܴଶଶ ܥ כଷ଼ ∴ ܴଶଶ ൌ ൌ ହ. C38. R22.5μs pulse. T.600pF timing capacitor. By “ANDing” the PWM Control input signal for each phase of our inverter with the square wave output by the One-Shot. the equivalent waveform produced is a 40kHz square wave with a duty cycle of 98%. so we could adjust the output pulse of width. the duty cycle of the PWM Control Input signals are effectively limited to 98%. with a 10kΩ potentiometer.ி = 4. This 0V low/15V high signal is interfaced with the 74AC00 CMOS NAND Gates through a simple resistor divider reducing it to a 0V low/+5V high signal.26 retriggerable one-shot generates a 24. This provides the high-side IGBT off-time necessary for recharging the bootstrap capacitor as discussed in Section 4.375݇Ω యఴ (4-13) ் ଶସ.ହఓ௦ 4.1. The timing equations and wiring configuration for a non-retriggerable oneshot design were given by the HCF4538B datasheet .2.5 High-speed CMOS NAND Gates The 74AC00 CMOS NAND Gates used in our PWM Control Circuit provide the logical AND function needed to limit the duty cycle of the PWM Control Input signals to 98% .3.
. we needed to figure out how to supply power to the low-voltage side of our project. and +5 VDC to our circuit. -15 VDC. The use of 0.3. 4. It is also important to note the use of sufficiently larg electrolytic bias supply capacitors located at the circuit board D-sub connector where the power is delivered to the board.3.” Since these adapters are isolated. we only needed to supply +15 VDC. Since the function generator donated to our project by GA-ASI came with its own power supply. we bought two 15V and one 5V isolated AC/DC wall adapters – the first two sold as “Notebook Adapters” and the latter as an “Internet Router Adapter.7 Using Decoupling Capacitors As we complete our discussion of the PWM Control Circuit.1μF ceramic capacitors tied between logic ground and any IC pin connected to a bias voltage provides sufficient AC decoupling and noise immunity.6 Supplying Power to the PWM Control Circuit and Bootstrap Supply After having figured out how to drive our inverter IGBTs and design the PWM Control Circuit. we were able to reference our PWM Control Circuit DC Bias Supply voltages to the most negative voltage used for the DC Input Supply to our inverter – a requirement for properly driving our Half-Bridge IGBT topology with a Bootstrap Supply. For these voltages.27 4. it is important to note the use of decoupling capacitors throughout our circuit design.
As illustrated by the Bode plot in Figure 4. ݂ ൌ Source: John Brewer.4 The LC Output Filters The design process for our inverter project included the design of three Second-Order LC filters to be used for smoothing the output voltage waveforms for each phase of our inverter. Fig. using L = 159μH and C = 40μF.995 ݖܪ؆ 2݇ݖܪ ∴݂ ൌ . we designed the LC output filter to have a corner frequency of 2kHz so it would effectively pass the 400Hz voltage waveform while sufficiently attenuating the 40kHz PWM switching frequencies. 4.9. The design of these LC output filters was based on the 400Hz output voltage frequency and the 40kHz PWM switching frequency. ଶగ√ ଶగඥଵହଽఓுכସఓி ଵ ଵ (4-14) ൌ 1. Jr.9 – Bode Plot of Second Order LC Filter Therefore.28 4. We also designed the LC filter to have a low output impedance of 2Ω.
4. we designed the inductors for our inverter to be able to carry up to 50A. Although the nominal output current of each inverter phase is 33A.2 ܿ݉ସ ∴ ܣ = where AP = area product in cm4. The most significant factor in the inductor design process was the desired inductance and maximum amount of current that would flow through an inductor during inverter operation. we received some much needed help from Jeff Brewer .29 And. ܼை் ൌ ට ଵହଽఓு (4-15) ∴ ܼை் ൌ ට ସఓி ൌ 1.99Ω ≅ 2Ω 4. Based on the equation for energy stored in an inductor. we needed to design inductors that could each store ܧ = ݅ܮଶ ଶ ଵ ଶ ଵ (4-16) ∴ ܧ௦௧ௗ = ∗ 159ߤ ∗ ܪሺ50ܣሻଶ = 0.19875 ݏ݈݁ݑܬ Then using ܣ = ଶ∗ாೞ ∗ଵర ೌೣ ∗ೕ ∗ೠ ଶ∗.ହ (4-17) = 34.ଵଽ଼ହ∗ଵర ହ∗ସ଼∗. .1 Inductor Design During the design process of the inductors for our inverter.
size 10. Nmin.ೌೣ ∗ଵఴ ೌೣ ∗ೌ (4-18) = 49 ݏ݊ݎݑݐ ∴ ܰ = where L= IDC. Total cross sectional area of the air gap including fringing. These PowerLite cut C-cores are made out of Metglas iron alloy material and will not only make our inductors easy to fabricate but also allow for fine tuning of inductance by adjusting the air gap and using an Impedance Bridge To determine the minimum number of turns.304 ݅݊ܿℎ݁ݏ. Bmax = the maximum flux density in Gauss.ଶమ Inductance of the inductor in microHenries.ଶ∗గ∗ೌ ∗ଵషమ ∗ேమ . Maximum current through the inductor in Amps.max = Agap = And ܮ = ଵହଽఓு∗ହ∗ଵఴ ହ. we used ܰ ൌ כூವ. from selecting an AMCC-50. ∴ ܮ = .30 Kj = the current density coefficient for a given core and a given temperature rise. and the length of air gap. Ku = the cross sectional area of copper to the total window area or packing factor.்∗ଷ. PowerLite C-Core   . Lgap.ଶ∗గ∗ଷ. .ଶమ ∗ଵషమ ∗ସଽమ ଵହଽఓு (4-19) = 0. needed in each leg of the cut C-core inductor.
we chose 10AWG magnet wire with a heavy insulation build for withstanding temperatures up to 200°C to wrap our AMCC-50 cores with . it would be hard to fabricate for a prototype. So.31 Lastly. We were able to successfully wrap our inductor bobbins with 49 turns and connect two bobbins in parallel. . one on each inductor leg. we will discuss the construction phase of our inverter project. for a generous inductor current capacity of 50A. In the next section of this report. we determined that although making an inductor by wrapping insulated Copper Foil around a Ferrite Core would result in lower core losses for the beneficial design tradeoff of higher copper loss.
To make connections on our circuit board. label. . Inductor construction. however.1 PWM Control Circuit Assembly Before starting construction of the PWM Control Circuit. components. CONSTRUCTION The construction and assembly phase of our proof-of-concept inverter project consisted of six main parts – PWM Control Circuit assembly. Figure 5.1 – Portion of Circuit Board Layout Graphic of soldering and wire wrapping. Jr. and “wire” components according to our circuit design. 5.32 V. and System assembly. we used a combination Fig. Connectors.1 shows a part of our Circuit Board Layout. Power Plane construction. we used Windows Paint to create scale drawings of our perforated circuit board (PerfBoard). 5. place. Source: John Brewer. Enclosure fabrication. We then copied these scale drawings into Microsoft PowerPoint where we were then able to freely move. Wire Harnesses. and ICs. and Cable fabrication. soldering was only used to solder short connections like decoupling capacitors to IC pins while wire wrapping constitutes a majority of our connections.
Source: John Brewer. we needed to guarantee that the wire was wrapped very tightly around each bobbin so that two bobbins would fit on one core. In order to prevent cracking a bobbin during the wrapping process. Fig. we needed to wrap 10AWG enameled wire 49 times around the inductor bobbins shown in Figure 5.3. wire wrapping uses a wire wrap tool to tightly wrap 30AWG Kynar wire around special wire wrap “posts.33 A common prototype technique.” Using two PerfBoards. Figure 5.5 to fit snugly inside each bobbin as it was wound.2 – Wire Wrapping modifications difficult. 5. provides a much stronger circuit board to work with and helps keep wire wrap posts straight. Jeff Brewer fabricated the wood handle shown in Figure 5.3 – Inductor Bobbin Source: John Brewer. Jr.2 illustrates this technique. 5.4. one on top of the other. Jr. As shown in Figure 5. 5. the design and fabrication of a Printed Circuit Board (PCB) would not have been cost effective and would have made circuit Fig.2 Inductor Construction To construct the inductors. For our proof-of-concept prototype. .
. Source: John Brewer. Jr. we used the right-hand-rule to determine the orientation of the bobbins on the core to guarantee that the flux induced by the coiled wire on each bobbin was flowing through Fig. We then used small squares of PerfBoard as spacers inside the bobbins between the core halves to maintain the necessary air gap of each inductor. Lastly. we adjusted the air gap of Source: John Brewer. Fig.6. Jr. we crimped and soldered them to a connector and wrapped up the inductor using hightemperature Mylar tape as shown in Figure 5.34 When it was time to put two wire-wrapped bobbins on a core.5 – Wood Handle to Support Bobbin Using a sharp edge. Fig. 5. Jr.6 – Finished Inductor with Connectors and Mylar Tape Source: John Brewer. 5. we scraped about an inch of enamel coating from each end of the wires to be connected.4 – Tightly Wound Inductor the core in the same direction. each inductor to obtain our desired inductance at 2kHz – 159μH. Using an Impedance Bridge. 5.
35 5.7. we used the mating female crimp contact receptacle also shown in Figure 5. we wired. Jr. we used Fig.7. testing. 5. • To connect to the output enable switch voltages from the front panel of our enclosure. and modification process. • To connect to the function generator 8-pin inline header output pins. we used a 10-pin inline header with mating crimp contact receptacle also shown in Figure 5. stranded 10AWG wire with crimp/ring connectors. connectors. . soldered. and cables: • For signals and voltages delivered to our circuit board from the function generator and low-voltage bias power supply jacks. and applied heat-shrink to the 15-pin D-sub connector shown in Figure 5.3 Wire Harnesses. Connectors. transportation.7.7 – Fabricated Wire Harnesses three parallel lines of Source: John Brewer. we designed and fabricated the following wire harnesses. • To connect the DC Input Voltages to our Input Capacitors and Power Planes. and Cable Fabrication In order to simplify the assembly.
8. These ring connectors in conjunction with nuts. Fig.5 Enclosure Fabrication For ease of transportation. prototype. 5. and testing of our inverter Source: John Brewer.8 – Top and Bottom Sides of Copper-Clad Board setup.4 Power Plane Construction In order to effectively reduce parasitic inductances in the DC Input Voltage supply path. and lock washers made it quick to assemble and disassemble our prototype for modifications. We used a combination of precise cutting and drilling to create isolated copper pads with at least a 3:1 ratio of length to width for current flow. . This enclosure allowed us to effectively and efficiently mount all of our system components and display our project for exhibition. bolts. we used double-sided copper-clad board for the ±input voltage delivered to the IGBTs. A section of both the top and bottom power planes are shown in Figure 5. Jaime Carmo generously donated his time and materials to fabricate a Plexiglas enclosure for us. we used stranded 10AWG wire with crimp/ring connectors. Jr. 5. 5. washers.36 • To connect output voltage nodes from the copper-clad circuit board to the inductors and the LC output filters to the enclosure panel.
6 System Assembly System assembly consisted of placing and arranging system components.37 5. nuts. Fig. Our final System Assembly is shown in Figure 5. washers.9 – Inverter System Assembly Source: John Brewer. . and lock washers. circuit board standoffs. drilling mounting holes in the Plexiglas enclosure. 5.9. bolts. and fastening components together or to the enclosure with wire ties. Jr.
TESTING For our project. For the Ideal Inverter Pspice simulation. Jr. 6. Fig.1 – Ideal Inverter Pspice Simulation Source: John Brewer. we performed several stages of testing – Ideal Inverter Pspice simulation. PWM Control Circuit and single IGBT Half-Bridge hardware low power testing. IGBT Gate Driver and Half-Bridge Pspice simulation.1 to obtain the output sinusoidal waveform shown in Figure 6. . and full system testing.38 VI. we simulated an open-loop switched-mode single phase PWM inverter circuit with Neutral phase using ideal components as shown in Figure 6. PWM Control Circuit hardware testing.2.
5ms 49.0ms 49.5ms 50. Jr. 6. 50% duty cycle square wave with 1μs of deadtime programmed in between high-side and low-side switching.3. Jr. The gate-to- Fig. we were still able to analyze the bootstrap power supply topology used to turn the high-side IGBT on.39 120V 80V 40V -0V -40V -80V -120V 45.2 – Output Voltage Waveform of Ideal Inverter Simulation Source: John Brewer.5ms V(R_LOAD:1).0ms 48.0ms 45. For the IGBT Gate Driver and Half-Bridge Pspice simulation shown in Figure 6.0ms Fig. we simulated an IR2113 Gate Driver and IRGP50B60PD1 Half-Bridge driven with a 40kHz. Despite not being able to use the Si8234BB IGBT gate driver in our simulation.0ms 47.5ms 47.V(R_LOAD:2) 46.5ms Time 48. 6. .0ms 46.3 – IGBT Gate Driver and Half-Bridge Pspice Simulation Source: John Brewer.
tested it. Load current waveform (top). we were able to fully tune the prototype design. Concurrently. At this point in the testing. As a result. 6.V(U3:3) 15us 20us 25us 30us Fig. Jr. our detail-oriented approach to the design of the PWM Control Circuit and the thorough analysis of the aforementioned design tips and application notes published by International Rectifier and Silicon Labs regarding HVIC Gate Drivers and the bootstrap supply topology warranted immediate prototyping and hardware testing. Source: John Brewer.V(U2:3) 10us V(U3:2). and observed successful results.4. we constructed a low-power single phase prototype of the IGBT Gate Driver with bootstrap supply and Half-Bridge topology. We tried to limit the time spent developing and 40A 20A 0A -20A I(Rload) 20V 10V analyzing the Pspice 0V simulations for our inverter project because it was difficult to accurately model all of the parasitic elements that would SEL>> -10V 0s 5us V(U2:2). Because we implemented resistance trimmers at critical points in the circuit.4 – High-side (green) and low-side (blue) IGBT gate-to-emitter voltage waveforms.40 emitter voltage waveforms and output current waveform are shown in Figure 6. . we constructed a prototype of our PWM Control Circuit design. Next. affect the high-power performance of our hardware design in the end.
these tests were all successful. However. After doing so.10: . and output voltage. After powering-up the PWM Control Circuit with the inverter outputs disabled. we performed full system tests. After reaching test equipment current limits. IGBT gate. collector. low-side decoupling capacitor sizing. and gate resistance sizing which caused us to take a closer look at IR’s design notes and modify our circuit design. and emitter voltages. we reported the following about Figure 6.41 we encountered problems regarding bias supply ground referencing. we were only able to test all three-phases of our inverter with a ±DC input supply voltage of ±48V due to test equipment voltage and current limits. supply voltages. our testing yielded successful results for low-power switching of our IGBTs using ±39VDC input supply and less than 1A output current.5 through Figure 6. Due to a miscommunication during a discussion about the DC Power available for testing in Cal Poly’s EE labs. After completing assembly of the final version of our proof-of-concept threephase inverter design. we turned on each phase and gradually increased the ±DC input supply voltage while monitoring all node voltages on the high-voltage side of our circuit – IGBT Gate Driver pin voltages.
6 – Trigger ger Pulse successfully generated by AD823AN Op-Amp Op Amp Comparator.42 Fig. 6. 6. .5 – Adjustable Three-Phase Three Sinusoidal Reference signals successfully generated. UC3637 38kHz Triangle Wave successfully generated and compared with with Sinusoidal Reference signals to produce three three-phase PWM Control Input signals. Fig.
7 – Square wave with 97% duty cycle successfully generated by Trigger Pulse and HCF4538B One-Shot.8 – Three-phase phase and Neutral-phase Neutral Duty Cycle limited PWM Control Input signals sign successfully generated. Fig. 6. . 6.43 Fig.
61 VRMS. Output voltage is 86 VP-P. Input RMS current is supply limit of 6. Output voltage is 87 VP-P.9 –Three-phase phase Inverter Output Voltage referenced to supply ground with ±48VDC Input Voltage. .5 A.2 A.44 Fig. 61 VRMS. 6. Output RMS current is 6. Input RMS current is supply limit of 6. Output RMS current is 6. 6. Fig.10 –Three-phase phase Inverter Output Voltage referenced reference to virtual ground with ±46VDC Input Voltage.5 A.2 A.
design.45 VII. CONCLUSIONS CONCLUSIONS AND RECOMMENDATIONS Designing and fabricating a proof-of-concept high-voltage switched-mode three-phase inverter capable of supplying 10kW covered a multitude of design processes and proved to be a challenging endeavor. ensuring that a detail-oriented approach was taken in the research. construction. While the original requirements for this project were not met due to limitations in lab test equipment. Continued development of the proof-of-concept inverter system that has been designed and fabricated for this project will assuredly lead to a productionlevel version with closed-loop feedback and possibly the following recommendations. limitations to this increase in current output capability will rise from parasitic inductance in the supply current path and action will be necessary to protect against . Given the relatively high-current output capabilities of the Si8234BB HVIC IGBT Gate Driver. and testing stages of this project contributed to its successful completion and thorough presentation in this report. observed test results yielded successful system performance at lower power levels than intended for nominal operation. up to two more IGBTs can be placed in parallel with each high-side and low-side IGBT in the power stage to increase the system current output capability while maintaining suitable IGBT switching transition times. However. However.
the design of a well laid-out surface mount technology PCB is recommended.2. As mention in Section 4.1. . Limitations will also rise from the inability to sufficiently cool IGBTs while minimizing parasitic inductance by maintaining close IGBT proximity. The development of a floating supply to replace the bootstrap supply topology designed for this project would eliminate the duty cycle limitations on the high-side IGBT.3. using a ferrite core wrapped with insulated copper foil for the system inductors would result in lower core and copper losses than the inductors in the current proof-of-concept system exhibit. This would decrease the amount of cooling required by the inductors which would increase the system quality. A digital PWM control system could also have improved noise immunity and temperature tolerance. If analog PWM control is desired. Development of a digital microprocessor-based PWM Control system could potentially reduce the amount of space required by the PWM Control block and allow for more versatile or accurate control performance.46 transient voltages. The signal voltages of the analog system designed for this project could then be reduced for faster edge transitions so long as the control circuit is effectively protected from noise and electromagnetic interference (EMI). A floating supply able to be ground referenced to the switching output of the half-bridge would provide for unlimited high-side IGBT on time under closed-loop control.
.47 Having made these recommendations. tuning. we maintain that the High-Voltage Switched-Mode Power Supply for Three-Phase AC Aircraft Systems that we have designed for this senior project presented to the Electrical Engineering faculty at California Polytechnic State University. and no significant design changes have been made. San Luis Obispo will fulfill the requirements set by the sponsor. Jeff Brewer. after proper high-power testing.
International Rectifier Design Tips DT04-4 Rev A.onsemi.        .com/product-info/datasheets/data/irgp50b60pd1. International Rectifier Datasheet PD-94625B.pdf. Inc. Interview.ti. MIL-STD-704F. Accessed June 7. Director of Electrical Engineering. Aircraft Systems Group. 2010.irf. General Atomics Aeronautical Systems. 2010. 2010. Accessed June 6.com/pub_link/Collateral/MUR420-D. Accessed June 7. http://focus.48 VIII.wbdg.silabs.org/wiki/Power_semiconductor_device.org/ccb/FEDMIL/std704f. Accessed June 4. http://www.pdf. Accessed June 7. 2010.irf. Accessed June 7. http://www. Accessed June 5. Silicon Labs Datasheet Si8234x. http://www.com/technical-info/designtp/dt04-4. http://www.pdf. BIBLIOGRAPHY  Power Semiconductor Device.PDF. http://www. http://en. 2010.pdf.com/Support%20Documents/TechnicalDocs/Si823x. John (Jeff).pdf.wikipedia. ON Semiconductor Datasheet MUR460.com/lit/ds/symlink/uc1637. Brewer. 2010. Unitrode Datasheet UC3637. 2010.
Accessed June 7.metglas. Accessed June 8.fairchildsemi.pdf.pdf. 2010.st. Transformer and Inductor Design Handbook.magnet4less.tij. STMicroelectronics Datasheet HCF4538B. 2010. http://www.pdf. McLyman. Accessed June 8. http://www. http://www.jp/jp/lit/an/slua184/slua184. Unitrode Application Note U-102. http://www. Colonel Wm. Applied Magnets AWG10-11.. Analog Devices Datasheet AD823AN. Accessed June 7.co. http://www. 2010. Accessed June 7. Marcel Dekker Inc. 2010. Fairchild Semiconductor Datasheet 74AC00.com/downloads/powerlite. 2004 PowerLite C-Cores. Accessed June 7.com/static/imported-files/data_sheets/AD823.pdf. 2010. Accessed June 7. Monticello.com/lit/an/slua137/slua137. T.php?products_id=175.pdf. http://focus.49  Unitrode Design Note DN-53A.com/ds/74%2F74AC00.        . http://focus. 2010.com/product_info.com/stonline/books/pdf/docs/2089. New York.pdf.analog.ti. 2010.
. 51 through 65.50 APPENDICES A. Schematic The following pages. contain the Three-Phase Sinusoidal Inverter schematic generated for this project.
5 4 3 2 1 NOTES: UNLESS OTHERWISE SPECIFIED 1. THREE PHASE INVERTER Sunday. BREWER. ALL RESISTORS ARE 1/8W. 2010 2 Rev E Sheet 1 1 of 15 5 . THREE PHASE INVERTER CONTENTS D D 1 11 PHASE-A GATE DRIVER 12 PHASE-B GATE DRIVER TABLE OF CONTENTS 10 PWM LIMIT LOGIC 2 IO CONNECTORS 3 13 PHASE-C GATE DRIVER 14 NEUTRAL GATE DRIVER 15 OUTPUT FILTERS SIGNAL BUFFERING C C 4 NEUTRAL PWM 5 PHASE-A PWM 6 PHASE-B PWM 7 PHASE-C PWM B B 8 PWM LIMIT TIMING 9 PWM LIMIT LOGIC A A Engineer: J. ALL CAPACITORS ARE 10%. Size A Date: 4 3 Document Number SCHEMATIC. June 06. 1% 2. JR. 50V.
June 06.15] SPARE SPARE SIN_A  C 9 6 5V_RTN 10 13 7 SIN_B  14 8 SIN_C  15 B B DGND -190V_SUPPLY 15V_RTN 5V_RTN 12V_RTN +15V -15V +5V C1 820uF 25V C91 560uF C2 4. JR. BREWER. 2010 2 Rev E Sheet 2 1 of 15 5 .5 4 3 2 1 THREE PHASE INVERTER IO CONNECTORS J2 +15V 15V_RTN -15V +5V 5V_RTN +12V 12V_RTN D D J1 1 9 +5V 1 NC 2 C_SD_SWCH  2 3 3 5V_RTN 4 10 +5V 5 4 N_SD_SWCH  6 11 5V_RTN 7 5 +5V C 8 12 A_B_SD_SWCH [14.7uF C5 820uF 25V C6 4.7uF DGND 15V_RTN 15V_RTN 5V_RTN A A Engineer: J. Size A Date: 4 3 Document Number SCHEMATIC. THREE PHASE INVERTER Sunday.7uF C3 820uF 25V C4 4.
0k R3 20k 1/4W C11 0.1uF C12 0.1uF +15V 15V_RTN U2B 5 + 8 V+ 15V_RTN 15V_RTN OUT VR7 100k 6 TL082 7 SIN_C_BUF  B B V+  SIN_B + OUT 4 V6 TL082 7 5 10uF 16V SIN_B_BUF  DGND -15V R4 100k DGND -15V R8 1. BREWER. THREE PHASE INVERTER Monday.9]  SIN_A 10uF 16V TL082 V-15V 2 R1 100k DGND C +15V 15V_RTN 15V_RTN -15V R2 1.0k R6 20k 1/4W Engineer: J.5 4 3 2 1 THREE PHASE INVERTER SIGNAL BUFFERING +15V +15V U2A 8 V+  TRI_WAVE + OUT 1 SIN_A_BUF  4 TL082 V2 1 U1A V+ 3 + OUT 4 -15V +15V -15V C D D 3 C7 8 TRI_BUF [5. 2010 2 Rev E Sheet 3 1 of 15 5 . Size A Date: 4 3 A 15V_RTN Document Number SCHEMATIC.1uF C13  SIN_C +15V 10uF 16V C9 0.1uF C8 0.7.6. JR. June 07.0k 4 R9 20k 1/4W 15V_RTN C10 U1B A 8 R5 1.
2010 2 Rev E Sheet 4 1 of 15 5 . Size A Date: 4 3 Document Number SCHEMATIC. BREWER.1uF B R11 5.7] A -15V Engineer: J.7.9] SLV_THRSH+ [5.1uF +C/L -C/L +E/A -E/A CT ISET SD +VTH -VTH UC3637 C17 0.1uF 6 15V_RTN 4 7 NEUTRAL_PWM  R20 150k C87 0.[5.5k C14 300pF -VS 5 C19 0.6.1uF -15V 15V_RTN C15 0.1k R13 5.5 4 3 2 1 THREE PHASE INVERTER MASTER PWM SLV_THRSH.5k A PWM_UVLO [5. JR.1uF 15V_RTN -15V 15V_RTN -15V 15V_RTN 2 +15V R15 47.62k R14 20.7. THREE PHASE INVERTER Monday.6.5k 1 3 R17 100k R16 10k 1/4W 18 14 15 16 12 13 +AIN -AIN +BIN -BIN C +15V R10 20.1uF 15V_RTN R18 330k C16 0.6. June 07.62k B R12 68.9] TRI_WAVE  +15V +15V C18 R19 150k U3 11 10 8 9 +VS AOUT BOUT E/AOUT 17 C D D 0.
1uF C22 0. THREE PHASE INVERTER Monday.1uF B B C20 0.5 4 3 2 1 THREE PHASE INVERTER PHASE-A PWM D D +15V C23 0.1uF 15V_RTN 15V_RTN C21 0. BREWER. June 07. Size A Date: 4 3 Document Number SCHEMATIC.1uF 15V_RTN -15V 15V_RTN A A Engineer: J. JR.1uF U4 11 10 8 9 +VS AOUT BOUT E/AOUT 17 C 6 15V_RTN 4 7 A_PWM   SIN_A_BUF  TRI_BUF +AIN -AIN +BIN -BIN +C/L -C/L +E/A -E/A CT ISET SD +VTH -VTH UC3637 C 12 13 15 16 2 18 14 1 3  PWM_UVLO  SLV_THRSH+  SLV_THRSH- -VS 5 C24 0. 2010 2 Rev E Sheet 5 1 of 15 5 .
Size A Date: 4 3 Document Number SCHEMATIC. BREWER.5 4 3 2 1 THREE PHASE INVERTER PHASE-B PWM D D +15V C28 0.1uF U5 11 10 8 9 +VS AOUT BOUT E/AOUT 17 C 6 15V_RTN 4 7 B_PWM   SIN_B_BUF  TRI_BUF +AIN -AIN +BIN -BIN +C/L -C/L +E/A -E/A CT ISET SD +VTH -VTH UC3637 C 12 13 15 16 2 18 14 1 3  PWM_UVLO  SLV_THRSH+  SLV_THRSH- -VS 5 C29 0.1uF 15V_RTN 15V_RTN C26 0.1uF C27 0. 2010 2 Rev E Sheet 6 1 of 15 5 . JR. THREE PHASE INVERTER Monday.1uF 15V_RTN -15V 15V_RTN A A Engineer: J. June 07.1uF B B C25 0.
2010 2 Rev E Sheet 7 1 of 15 5 .1uF 15V_RTN 15V_RTN C31 0. JR.1uF B B C30 0. THREE PHASE INVERTER Monday. Size A Date: 4 3 Document Number SCHEMATIC.1uF U6 11 10 8 9 +VS AOUT BOUT E/AOUT 17 C 6 15V_RTN 4 7 C_PWM   SIN_C_BUF  TRI_BUF +AIN -AIN +BIN -BIN +C/L -C/L +E/A -E/A CT ISET SD +VTH -VTH UC3637 C 12 13 15 16 2 18 14 1 3  PWM_UVLO  SLV_THRSH+  SLV_THRSH- -VS 5 C34 0. BREWER.1uF 15V_RTN -15V 15V_RTN A A Engineer: J. June 07.1uF C32 0.5 4 3 2 1 THREE PHASE INVERTER PHASE-C PWM D D +15V C33 0.
June 07. Size A Date: 4 3 Document Number SCHEMATIC. THREE PHASE INVERTER Monday.1uF 15V_RTN -15V C38 5600pF 15V_RTN C C DUTY_LIMIT [10.1uF 11-TR(2) 12+TR(2) Q2 10 Q2/ 9 Q1 6 U8 16 VDD V2 1 U7A 3 + AD823AN R21 1.1uF 15V_RTN 15V_RTN 13RESET(2) 14RxCx(2) 15Cx(2) +15V Vss HCF4538B 8 C37 0. 2010 2 Rev E Sheet 8 1 of 15 5 .0k R22 10k 1/4W  SLV_THRSH+ C35 0.11] B B 8 V+ AD823AN 7 15V_RTN OUT -15V A U7B 5 + 4 15V_RTN A V- 6 Engineer: J.1uF V+  TRI_BUF OUT 4 D1 SD103A 15V_RTN 1 Cx(1) 2 RxCx(1) 3 RESET(1) +15V -15V 4 +TR(1) Q1/ 7 5 -TR(1) C36 0. BREWER. JR.5 4 3 2 1 THREE PHASE INVERTER PWM LIMIT TIMING +15V D D 8 +15V C39 0.
5 4 3 2 1 THREE PHASE INVERTER PWM LIMIT LOGIC R24 10.2k B R28  B_PWM 10. Size A Date: 4 3 Document Number SCHEMATIC.2k 74AC00 74AC00 C D D R23  A_PWM R25 10.5k R27 10. 2010 2 Rev E Sheet 9 1 of 15 5 .1uF R29 5V_RTN 10.2k 15V_RTN U9D 12 8 13 11 A_DRIVE   DUTY_LIMIT C 15V_RTN +5V C40 0.2k B 15V_RTN U9B  DUTY_LIMIT 15V_RTN A A Engineer: J.2k 74AC00 3 5 74AC00 4 6 B_DRIVE  R30 10. THREE PHASE INVERTER Sunday.2k D2 SD103A 15V_RTN U9C 9 R26 10 20.5k R32 10. JR. June 06.2k 10.2k D3 SD103A 15V_RTN U9A 1 R31 2 20. BREWER.
1uF R39 5V_RTN 10. June 06.5k R42 10.2k 74AC00 74AC00 C D D R33  C_PWM R35 10. THREE PHASE INVERTER Sunday. Size A Date: 4 3 Document Number SCHEMATIC.2k B R38  NEUTRAL_PWM 10.5k R37 10.2k D5 SD103A 15V_RTN U10C 9 R41 10 20.2k B 15V_RTN U10D  DUTY_LIMIT 15V_RTN A A Engineer: J.2k 15V_RTN U10B 4 3 5 6 C_DRIVE   DUTY_LIMIT C 15V_RTN +5V C41 0.5 4 3 2 1 THREE PHASE INVERTER PWM LIMIT LOGIC R34 10.2k D4 SD103A 15V_RTN U10A 1 R36 2 20. 2010 2 Rev E Sheet 10 1 of 15 5 .2k 74AC00 8 13 74AC00 12 11 NEUTRAL_DRIVE  R40 10. BREWER. JR.2k 10.
1uF 5V_RTN 15V_RTN -190V A A Engineer: J.1uF R43 100k 1/4W 3 +5V B C86 0.5 4 3 2 1 THREE PHASE INVERTER PHASE-A GATE DRIVER D D +15V C44 10uF +190V C45 0. THREE PHASE INVERTER Monday.1uF D6 MUR460 15V_RTN U12 R44 U11 1 2 3 4 5 10uF 6 0.1uF Si8234BB 4. Size A Date: 4 3 Document Number SCHEMATIC.33uF 7 C49 8 0. June 07.9 C47 0. JR.1uF 5V_RTN  A_B_SD_SWCH B 1 C43 0. BREWER.33uF D9 16V 2 2 3 IRGP50B60PD1 1 1 C C  A_DRIVE C42 PHASE_A  0.7 D10 16V VDDI GNDB 9 R45 2 2 3 3 NC VOB 10 DT VDDB 11 C82 U13 1 D8 MUR460 DISABLE NC 12 C48 GNDI 13 NC +15V D7 16V VDDI GNDA 14 NC VOA 15 PWM VDDA 16 C46 0. 2010 2 Rev E Sheet 11 1 of 15 5 .33uF 3.
33uF 3. BREWER.7 D17 16V VDDI GNDB 9 R48 2 2 3 3 NC VOB 10 DT VDDB 11 C83 U16 1 D15 MUR460 C56 DISABLE NC NC +15V D14 16V GNDA 14 4 5 NC VOA 15 PWM VDDA 16 C54 0.1uF 5V_RTN  A_B_SD_SWCH B 1 C51 0.9 C55 0.33uF D16 16V 2 2 3 IRGP50B60PD1 1 1 C C  B_DRIVE C50 PHASE_B  0.1uF 5V_RTN 15V_RTN -190V A A Engineer: J. Size A Date: 4 3 Document Number SCHEMATIC.1uF Si8234BB 4. June 07. JR.1uF R46 100k 1/4W 3 +5V B C88 0.33uF 7 C57 8 0. THREE PHASE INVERTER Monday.1uF D13 MUR460 15V_RTN U15 R47 U14 1 2 3 VDDI GNDI 13 12 10uF 6 0.5 4 3 2 1 THREE PHASE INVERTER PHASE-B GATE DRIVER D D +15V C52 10uF +190V C53 0. 2010 2 Rev E Sheet 12 1 of 15 5 .
1uF 5V_RTN 15V_RTN -190V A A Engineer: J. THREE PHASE INVERTER Monday.1uF R49 100k 1/4W 3 +5V B C89 0.5 4 3 2 1 THREE PHASE INVERTER PHASE-C GATE DRIVER D D +15V C60 10uF +190V C61 0. June 07.9 C63 0.1uF D20 MUR460 15V_RTN U18 R50 U17 1 2 3 VDDI GNDI 13 12 10uF 6 0. BREWER. 2010 2 Rev E Sheet 13 1 of 15 5 .33uF D23 16V 2 2 3 IRGP50B60PD1 1 1 C C  C_DRIVE C58 PHASE_C  0. JR.1uF 5V_RTN  C_SD_SWCH B 1 C59 0. Size A Date: 4 3 Document Number SCHEMATIC.1uF Si8234BB 4.7 D24 16V VDDI GNDB 9 R51 2 2 3 3 NC VOB 10 DT VDDB 11 C84 U19 1 D22 MUR460 C64 DISABLE NC NC +15V D21 16V GNDA 14 4 5 NC VOA 15 PWM VDDA 16 C62 0.33uF 3.33uF 7 C65 8 0.
7 D31 16V VDDI GNDB 9 R54 2 2 3 3 NC VOB 10 DT VDDB 11 C85 U22 1 D29 MUR460 C72 DISABLE NC NC +15V D28 16V GNDA 14 4 5 NC VOA 15 PWM VDDA 16 C70 0.1uF 5V_RTN  N_SD_SWCH B 1 C67 0.1uF D27 MUR460 15V_RTN U21 R53 U21 1 2 3 VDDI GNDI 13 12 10uF 6 0. 2010 2 Rev E Sheet 14 1 of 15 5 . BREWER. Size A Date: 4 3 Document Number SCHEMATIC.33uF 7 C73 8 0. THREE PHASE INVERTER Monday.1uF 5V_RTN 15V_RTN -190V A A Engineer: J. June 07.33uF D30 16V 2 2 3 IRGP50B60PD1 1 1 C C  NEUTRAL_DRIVE C66 NEUTRAL  0.33uF 3.1uF R52 100k 1/4W 3 +5V B C90 0. JR.9 C71 0.1uF Si8234BB 4.5 4 3 2 1 THREE PHASE INVERTER NEUTRAL GATE DRIVER D D +15V C68 10uF +190V C69 0.
BREWER. Size A Date: 4 3 Document Number SCHEMATIC. June 06. THREE PHASE INVERTER Sunday. 2010 2 Rev E Sheet 15 1 of 15 5 .5 4 3 2 1 THREE PHASE INVERTER OUTPUT FILTERS D D L1 SIN_A_OUT  PHASE_A 160uH C74 20uF 400V L3 PWR_GND  PHASE_C 160uH C78 20uF 400V L2 SIN_B_OUT PWR_GND 160uH C76 20uF 400V C77 20uF 400V +190V C79 20uF 400V C C75 20uF 400V SIN_C_OUT C  PHASE_B B PWR_GND L4  NEUTRAL 160uH C80 3300uF 350V B C81 3300uF 350V PWR_GND -190V A A Engineer: J. JR.
38 3.49 2.7 1. Bill of Materials Table B.5 7. 1' x 72 yds SPDT 6A F.85 1 2 1 1 1 3 3 1 21 2 4 2 15 2 4 8 13 12 4 10 16 16 28 40 8 8 5 16 9 8 59 75 69 1 13.45 0.35 0. 2.69 3.LVR Switch SPDT 6A R.5 1.6 0.Slotted Bolt #10-32 x 5/8" Round Head .1 0.94 6.99 3.49 2.07 9.48 1.Phillips Bolt #10-32 Nut #10 Lock Washer #10 SAE Washer Aluminum Flat Plate Unit Price ($) Quantity Total Price ($) 13.5 3.1 0.99 0.06 0.68 1.97 5.LVR Switch D-Sub 15 Pin Male D-Sub 15 Pin Female Pre-Punched IC-Spacing Perfboard 2-3/4"x6" 2-Sided Cooper Clad Board 4.Slotted Bolt #10-32 x 1" Rounded .1 – Bill of Materials and Donated Items Item Hardware CS Hyde Metalized Mylar Tape.Slotted Bolt #10-32 x 1/2" Flat Head.5 1 2.8 0.8 0.1 0.52 3.99 2.25 1.Slotted Bolt #10-32 x 3/4" Round Head .03 0. Thick.Phillips Bolt #4-40 Nut #6-32 x 3/8' Round Head .5"x6.03 0.49 0.9 0.63 0.66 B.1 0.125" Assorted Cable Ties 8" 8-10 Stud Ring Terminals Door Handles PCB Standoff 1" PCB Standoff 2 1/4" Crimp Pins Male Plastic Rectangular Crimp Pin Receptacle Corner Brace 1-1/2" White Screw Bumper Ring Tongue Connector #4-40 x 1/2' Round Head .2 mil.1 0.1 0.1 0.85 .1 0.2 0.03 0.14 3.2 0.1 0.5 2.98 1.8 0.Slotted Bolt #6-32 Nut #6 Lock Washer #6 SAE Washer #10-32 x 3/8" Round Head .1 0.3 1.06 0.77 4.8 1.49 0.69 2.25 0.03 0.Slotted Bolt #4-40 x 1/2' Round Head .49 3.69 2.6 0.Slotted Bolt #10-32 x 1/2" Round Head .99 5.4 0.97 11.92 3.49 11.5 0.03 9.
Polyolenfin Heat Shrink Tubing 3/32" Polyolenfin Heat Shrink Tubing 3/32" IC Socket Mach Pin WW 8Pos Gold - AR08-HZW/T-R IC Socket Mach Pin WW 14Pos Gold - AR14-HZW/T-R IC Socket Mach Pin WW 16Pos Gold - AR16-HZW/T-R IC Socket Mach Pin WW 18Pos Gold - AR18-HZW/T-R Square Machine Post - 100 Coaxial DC Power Jack Coaxial DC Power Plug Electronics Texas Instruments - OpAmp Dual JFET Input TL082CP Unitrode - SM Crtl for DC Motor Drive - UC3637 Analog Devices Inc - OpAmp JFET R-R Dual AD823AN Fairchild Semiconductor - Quad 2 Input Nand 74AC00B International Rectifier - IGBT - IRGP50B60PD1 STMicroelectronics - Multivibrator - HCF4538B Silicon Labs - High Side / Low Side Driver - Si8234BB Mallory CGS332T350X5L 3300μF 350VDC Capacitor United Chemi-Con - Cap Elect 820uF 50V Panasonic - ECG - Cap 4.7uf 25V Cer - PCC2251CT-ND TDK Corp - Cap Cer 10uF 16V X7R RAD FK20X7R1C106K Panasonic - ECG - Cap Elect 10uF 400V - EEUED2G100 BC Components - Cap Cer .10UF 50V K104K15X7RF5TH5 Murata Electronics NA - Cap Cer 300pF 50V Murata Electronics NA - Cap Cer 5600pF 50V TDK Corporation - Cap Cer 0.33uF 50V FK24X7R1H334K United Chemi-Con - Cap Elect 560uF 50V Diodes Inc - Diode Schottky 40V 400MW - SD103A-T ON Semiconductor - Switchmode -Diode 4A 600V Murata Electronics NA - Trim Pot Cerm 100kOhm Stackpole Electronics Inc - RES 1kOhm 1/8W 5% Murata Electronics NA - Trim Pot Cer 20kOhm Yageo - Res 20.5kohm 1/4W 1% Metal Film Stackpole Electronics - Res MF 1/8W 5.62kOhm 1% Stackpole Electronics Inc - Res MF 1/8W 68.1kOhm 1%
1.79 1.95 1.69 2.53 2.9 2.9 4.99 3.29 3.29
1 1 3 2 5 4 1 4 4
1.79 1.95 5.07 5.06 14.5 11.6 4.99 13.16 13.16
0.77 7.28 5.64 0.6 8.28 0.65 3.71 71.45 1.29 0.79 0.83 0.67 0.06 0.3 0.62 0.21 0.86 0.65 0.65 1.38 0.09 1.38 0.57 0.15 0.15
2 4 1 2 16 1 4 2 3 3 3 8 51 1 1 12 1 5 8 8 4 3 6 2 1
1.54 29.12 5.64 1.2 132.48 0.65 14.84 142.9 3.87 2.37 2.49 5.36 3.06 0.3 0.62 2.52 0.86 3.25 5.2 11.04 0.36 4.14 3.42 0.3 0.15
Stackpole Electronics Inc - Res MF 1/8W 47.5kOhm 1% Murata Electronics NA - Trim Pot Cerm 10kOhm 12Trn Stackpole Electronics Inc - Res MF 1/8W 330kOhm 1% Stackpole Electronics Inc - Res MF 1/8W 150kOhm 1% Stackpole Electronics Inc - Res MF 1/8W 10.2kOhm 1% Stackpole Electronics Inc - Res MF 1/8W 3.9Ohm 1% Stackpole Electronics Inc - Res MF 1/8W 4.7Ohm 1% Wire UL- Stranded Hookup Wire - 22AWG - Red 25' UL- Stranded Hookup Wire - 22AWG - Green 25' UL- Stranded Hookup Wire - 22AWG - Black 25' 10AWG - Mil Spec - M81044/ 9-10-9 - White 10' 10AWG - Mil Spec - M81044/ 9-10-0 - Black 10' 26AWG - Stranded HookupWire - Red - 25' 26AWG - Stranded HookupWire - Black - 25' 26AWG - Assorted Stranded HookupWire - 25' Magnet Wire / Winding Wire - 10 AWG, 11LBS Wire Roll Repl 30AWG Blue 50' Wire Roll Repl 30AWG Yellow 50' Wire Roll Repl 30AWG Green 50' Wire Roll Repl 30AWG Orange 50'
0.15 1.81 0.15 0.15 0.15 0.15 0.15
1 2 1 2 16 4 4
0.15 3.62 0.15 0.3 2.4 0.6 0.6
2.33 2.33 2.33 4 4 2.25 2.25 4.99 124.99 9.12 9.12 9.12 9.12
1 1 1 1 1 1 1 1 1 1 1 1 1 Grand Total
2.33 2.33 2.33 4 4 2.25 2.25 4.99 124.99 9.12 9.12 9.12 9.12 757.27
Donated Items Plexiglass Project Box 22 3/8"X 20 1/8" X 9 1/4" dsPIC Funtion Generator Electrocube 945B 20μF 400VDC Capacitor Powerlite C-Core AMCC 50 Powerlite Bobbin AMCC-50BOB
Quantity 1 1 6 8 8
Circuit Board Layout
Fig. C.1 – Microsoft PowerPoint Circuit Board Layout Source: John Brewer, Jr. and Kamaljit Bagha
D. Jr. and Kamaljit Bagha .1 – IC and Component Circuit Board Location Source: John Brewer. Circuit Board IC and Component Locations Fig.70 D.
71 E. Hardware Configuration and Layout Fig. E.1 – Hardware Configuration and Layout Source: Kamaljit Bagha .
72 Fig. E.2 – Test Bench Setup Source: Kamaljit Bagha .
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