Homework #9 Solution

1. Create Verilog modules that implement each of the following: a) b) c) d) An inverter. A 5-input AND gate. A 4-to-1 multiplexer. A J-K flip-flop with enable, asynchronous set and reset (i.e., preset and clear), and true and complemented outputs. e) A circuit that, when enable is true, counts clock transitions and generates a high output every 8 clock cycles.
module inverter(a, not_a); input a; output not_a; assign not_a = ~a; endmodule module and_5_inp(x, y); input[4:0] x; output y; assign y = x[0] & x[1] & x[2] & x[3] & x[4]; endmodule module mux_4_to_1(x, s, y); input[3:0] x; input[1:0] s; output y; assign y = x[s]; endmodule

snext. input preset. tick). output reg tick. 3'b100: q <= 1'b1. output reg q. endcase assign not_q = ~q. posedge clear. en. /* Output */ always @(s) if (s == 3'b000) tick <= 1'b1. output not_q. not_q). j. j. clear. clk. else tick <= 1'b0. always @(posedge preset. k. j. 3'b011: q <= 1'b1. 3'b110: q <= 1'b1. 3'b001: q <= 1'b0. input clk.module jk_flip_flop(preset. 3'b111: q <= 1'b0. /* Advance state */ always @(negedge clk) if (en) s <= snext. q. /* Next state */ always @(s) snext <= s + 1'b1. clear. k}) 3'b000: q <= 1'b0. else if (clear) q <= 1'b0. 3'b101: q <= 1'b0. endmodule . en. else if (en) case ({q. k. endmodule module divide_by_8(clk. reg[2:0] s. clk. negedge clk) if (preset) q <= 1'b1. 3'b010: q <= 1'b1. en. en.

if it is in the armed state. it will transition to the armed state if the RDY signal is asserted without regard for the FRE signal. /* Advance or reset */ always @(negedge clk. rdy) case (s) 2'b00: if (rdy) snext <= 2'b01. A clocked sequential circuit has three states: rest. a) Create a Verilog module for this state machine. fre. else snext <= 2'b00. /* Next state */ always @(s. /* Use this to test state machine */ reg[1:0] s. Here is the state diagram: 0x Rest 00 1x xx Armed 01 11 Fire 11 01. 10 module state_machine(rdy. 2'b10: snext <= 2'b00. fre. output[1:0] q. 00. rst. if it is in the fire state. posedge rst) if (rst) s <= 2'b00. fre. it will transition to the fire state if the FRE signal is asserted and the RDY signal is asserted. fire. clk. 2'b01: if (rdy & fre) snext <= 2'b10. The transitions are caused by external inputs according to the following rule: if the system is in the rest state. clk.2. armed. snext. else s <= snext. input rdy. else snext <= 2'b01. q). rst. endmodule . it will transition to the ready state always without regard for the inputs. endcase /* Output */ assign q = s.

fre = 1'b0.b) Write a test-bench for the FSM that shows its correct behavior. end endmodule . clk. #10 #10 #10 #10 #10 rst = 1'b0. rst. /* Instantiate FSM */ state_machine M1(rdy. rdy=%b. Run the simulation and attach the obtained outputs (text output of iverilog or waveforms on Xilinx). q=%b". clk. q). reg clk. rdy = 1'b1. fre=%b. q). reg rdy. fre = 1'b0. fre = 1'b0. wire[1:0] q. rdy = 1'b0. end /* Explore inputs */ initial begin $monitor("%d clk=%b. fre = 1'b0. $realtime. rst = 1'b1. module test_state_machine. rdy = 1'b0. /* Clock signal */ initial begin clk = 1'b1. rst. rdy = 1'b0. rdy. forever #5 clk = ~clk. fre. fre. $finish. fre.

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