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EE8501/ELE863 - VLSI Systems Laboratory Manual

F. Yuan, PhD., P.Eng. Professor Department of Electrical and Computer Engineering Ryerson University Toronto, Ontario, Canada Copyright c Fei Yuan 2011

Preface
This laboratory manual is an essential component of EE8501/ELE863 VLSI Systems oered by Professor F. Yuan in the Department of Electrical and Computer Engineering at Ryerson University, Toronto, Ontario, Canada. Permission to duplicate and distribute this document is granted for educational purpose only. This laboratory manual consists of four laboratories. Laboratory 1 studies the cross-coupled CMOS current-controlled oscillators. In Laboratory 2, the design of a D-ipop phase/frequency detector is explored. Laboratory 3 deals with the design of a phase-locked loop. In Laboratory 4, the eect of package parasitics is investigated. An complete chip set of the phase-locked loop designed in the preceding four laboratories is analyzed in this laboratory. Please report any error in this Laboratory Manual or problem encountered during laboratories to Professor F. Yuan at fyuan@ee.ryerson.ca. Fei Yuan Jan. 2011

Calendar Description of EE8501/ELE863 VLSI Systems


This course deals with the design of low-power high-speed CMOS integrated circuits using deep sub-micron CMOS technology at the system level. The course consists of two essential components: theory and project. The theoretical component consists of : advanced topics on modeling of MOS transistors, modeling of interconnects (lumped, distributed RC, distributed RLC, and transmission line models), impedance matching techniques, layout techniques for high-speed digital and mixed analog-digital circuits, clock generation and distribution on chip, power distribution on chip, analog and digital grounding of mixed analog-digital circuits on chip, I/O and pad design, packaging and ESD protection, switching noise, and high-speed data links. The project component consists of design, layout, and simulation of CMOS circuits using state-of-the-art CMOS technology and CAD tools. 3 hours lecture, 1 hours laboratory each week. Prerequisites ELE704 or ELE734.

Contents
1 Current-Controlled Ring Oscillators 1 Duration : 2 weeks . . . . . . . . . 2 Introduction . . . . . . . . . . . . . 3 Laboratory Work . . . . . . . . . . 3.1 Oscillator . . . . . . . . . . 3.2 Switching Noise Injector . . 3.3 Simulation and Analysis . . 4 Laboratory Report . . . . . . . . . 7 7 7 8 8 9 9 10 13 13 13 14 14 14 14 15 16 19 19 19 20

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2 D-ipop Phase/Frequency Detectors 1 Duration : 2 weeks . . . . . . . . . . . . . . 2 Introduction . . . . . . . . . . . . . . . . . . 3 Laboratory Work . . . . . . . . . . . . . . . 3.1 D-Flipops . . . . . . . . . . . . . . 3.2 D-Flipops with RESET . . . . . . . 3.3 AND2 Gate . . . . . . . . . . . . . . 3.4 D-ipop Phase/Frequency Detector 4 Laboratory Report . . . . . . . . . . . . . .

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3 Phase-Locked Loops 1 Duration: 2 weeks . . . . . . . . . . . . . . . . . . . . . . . . . 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1 Charge Pumps . 3.2 Loop Filters . . . 3.3 Open-Loop Test . 3.4 Closed-Loop Test Laboratory Report . . .

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20 22 22 23 24 27 27 27 27 28 29 29 29 29 30 31 31 31 32 32 33 33 33 34

4 Phase-Locked Loop Chip Set 1 Duration : 4 weeks . . . . . . . . . . . . . 2 Introduction . . . . . . . . . . . . . . . . . 3 Models for Packaging . . . . . . . . . . . . 4 Models for Bond Pads . . . . . . . . . . . 5 Models for Bond Wires . . . . . . . . . . . 6 Schematics . . . . . . . . . . . . . . . . . . 7 Laboratory Work . . . . . . . . . . . . . . 7.1 Complete Test Circuit Construction 7.2 VDD and VSS Pads . . . . . . . . . 7.3 VCO Output Buering . . . . . . . 7.4 PLL Test . . . . . . . . . . . . . . 8 Layout of PLL . . . . . . . . . . . . . . . . 8.1 Floor-Planning of PLL . . . . . . . 8.2 Layout of PLL . . . . . . . . . . . 8.3 I/O Pin Assignment . . . . . . . . 8.4 Layout of Pads . . . . . . . . . . . 8.5 Layout of Output Buers . . . . . 9 Laboratory Report . . . . . . . . . . . . .

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List of Figures
1.1 Four-stage fully dierential current-controlled ring oscillator . 9 1.2 Symbol of the delay cell of fully dierential current-controlled ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 D ip-op phase/frequency detector. . . . . . . . . . . . . . . 15 2.2 D ip-ops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Basic conguration of type II phase-locked loops. . . . . . . 3.2 Current-steering charge pump. The charge pump conveys JU P to the downstream loop lter when UP=1 and DN=0. It sinks JDN from the loop lter when DN=1 and UP=0. . . . . . . 3.3 Implementation of the current-steering charge pump. . . . . 3.4 Open-loop test circuit. . . . . . . . . . . . . . . . . . . . . . 3.5 Fully dierential cross-coupled voltage-controlled oscillator. . . 20

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4.1 Simplied schematic of complete chip set . . . . . . . . . . . . 30

List of Tables
4.1 Pad assignment of phase-locked loop chip set. . . . . . . . . . 31

Chapter 1 Current-Controlled Ring Oscillators


1 2 Duration : 2 weeks Introduction

Voltage (current)-controlled ring oscillators are used extensively in computer systems and data communication networks. This laboratory investigates the design of fully dierential CMOS current-controlled ring oscillators with an emphasis on switching noise and their impact on the timing jitter of the oscillators. In this laboratory, you are required to design a four-stage fully differential CMOS current-controlled ring oscillator using TSMC-0.18m 1.8V CMOS technology and analyze the performance of the designed oscillator using Spectre from Cadence Design Systems with BSIM3.3v device models. The oscillation frequency of the oscillator is 900 MHz. The delay cell of the oscillator was the originally reported in [1], as shown in Fig.1.1. This delay cell utilizes a positive latch formed by M12 to combat the switching noise present on the power and ground rails in the following ways : (i) The positive feedback reduces the transition time and sharpens both the rising and falling

CHAPTER 1. CURRENT-CONTROLLED RING OSCILLATORS

edges of the waveform of the oscillator. (ii) A fast transition minimizes the timing jitter of the oscillator. As pointed out in [2] the noise of the MOS devices and the switching noise of the VCOs output at the threshold-crossing shifts the actual threshold-crossing time (timing jitter) by an amount that is proportional to the power of the total noise injected at the threshold-crossing and inversely proportional to the slew rate of the output voltage [2].
2 vn , (dvo /dt)2

2 =

(1.1)

2 is the power of the total noise injected at where 2 is the timing jitter, vn the threshold-crossing, and dvo /dt is the slew rate of the output voltage of the oscillator at the threshold-crossing. (iii) The latch eectively rejects the noise presented on the power and ground rails once the latch is established.

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3.1

Laboratory Work
Oscillator

Design a four-stage CMOS fully dierential current-controlled ring oscillator, as per the schematic of Fig.1.1 where all n-well pickup contacts of pMOS transistors are connected to a clean power supply. The bond wire connecting the VDD bonding pad and the power supply pin is modeled as an ideal inductor with its inductance L = 0.1 nH. The inductance of the bond wire connecting VSS and ground is neglected so that no ground bouncing is considered. The capacitance of the bonding pads is neglected for simplicity. The width of M34 should be at least twice that of M12 in order to be able to break the positive feedback. Over-sizing M34 will result in a large capacitance at the output nodes, slowing down the oscillator.

CHAPTER 1. CURRENT-CONTROLLED RING OSCILLATORS


VDD1 L VDD2 L

I ctrl
Vin+ M3

M5 Vo-

M6 Vo+ Vin-

4 CL

M1

M2

M4

Cross-coupled delay cell (Stage 1)

Switching noise injector

Figure 1.1: Four-stage fully dierential current-controlled ring oscillator

3.2

Switching Noise Injector

A static CMOS inverter whose dimension is much larger than the dimension of the transistors in the delay stage of the oscillator is powered by the same power supply as that of the oscillator. Let the load of the large CMOS inverter be a large capacitor. The input of the large CMOS inverter is an ideal square wave generator whose period is much smaller than the oscillation period of the oscillator. This clocked large inverter is used to simulate the injection of switching noise to the power rail of the oscillator.

3.3

Simulation and Analysis

Construct the symbol of the delay cell of the oscillator that has (i) two input terminals vin+ and vin , (ii) two output terminals vo+ and vo , (iii) one VDD connection terminal, (iv) one VSS connection terminal, (v) one n-well connection terminal vnwell , and (vi) one substrate connection terminal vsub , as per Fig.1.2. Construct the current controlled oscillator by including (i) all delay stags, (ii) the biasing circuit, (iii) the switching noise injection circuit, and (iv) VDD and VSS circuitry including bonding wires. Perform time-domain analysis of the designed oscillator. The start of

CHAPTER 1. CURRENT-CONTROLLED RING OSCILLATORS


VDD Vn-well

10

Vin+ Delay cell Vin-

Vo-

Vo+

VSS

Vsub

Figure 1.2: Symbol of the delay cell of fully dierential current-controlled ring oscillator the oscillation of the oscillators can be activated by connecting a small capacitor to the output node of one of the delay stages of the oscillator with an initial voltage. Note that the value of the capacitor should be small in order to minimize unwanted loading eect. Plot the output voltage of each stage of the oscillator with two dierent transistor widths of the latch. Measure the timing jitter. Comment on the waveform dierence. Plot the output voltage of each stage of the oscillator with two dierent control currents. Measure the rise and fall times of the output voltage in both cases. Measure the timing jitter. Comment on your ndings. Use parametric analysis and calculator tools to obtain the oscillation frequency-control current plot. Estimate the frequency tuning range and frequency control sensitivity of the designed oscillator.

Laboratory Report

A professionally prepared laboratory report containing the followings is due at the start of the next laboratory.

CHAPTER 1. CURRENT-CONTROLLED RING OSCILLATORS

11

The schematic of the current-controlled oscillator (delay cell + entire test circuit) with a boarder section showing your name and student ID. A table tabulating the exact dimension of all transistors used in your design. The waveform of the voltage of the output of each stage of the currentcontrolled oscillator with two dierent transistor widths of the latch. Measure the peak-to-peak timing jitter at the threshold-crossing points of the output waveform of the oscillator. The waveforms of the voltage of the output of each stage of the currentcontrolled oscillator with two dierent control currents. Measured the rise and fall times in these two cases. Measure the peak-to-peak timing jitter at the threshold-crossing points of the output waveform of the oscillator. Oscillation frequency - control current plot. Determine the frequency tuning range and frequency control sensitivity.

Bibliography
[1] X. Mailand, F. Devisch, and M. Kuijk, A 900 Mb/s CMOS data recovery DLL using half-frequency clock, IEEE Journal of Solid-State Circuits, vol. 37, No. 6, pp 711-715, June 2002. [2] T. Weigandt, B. Kim, and P. Grey, Analysis of timing jitter in ring oscillators, in Proc. of IEEE International Symposium on Circuits and Systems, pp. 27-30, London, 1994.

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Chapter 2 D-ipop Phase/Frequency Detectors


1 2 Duration : 2 weeks Introduction

Phase/frequency detectors (PFDs) are one of the vital building blocks of phase-locked loops (PLLs) and delay-locked loops (DLLs). The main functionality of PFDs is to sense the phase/frequency dierence between an input digital stream and a reference clock and to output a pair of phase/frequencymodulated pulses called UP and DOWN whose pulse width is directly proportional to the phase/frequency dierence. The output signals UP and DOWN are then used to control a downstream charge pump whose output voltage controls the oscillation frequency of a downstream voltage (current)controlled oscillator. In this laboratory, you will investigate the characteristics of a widely used phase/frequency detector called D-ipop phase/frequency detector. The D-ipop phase/frequency detector employs two positive edge-triggered resettable D-ipops to detect the phase/frequency dierence of two input

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CHAPTER 2. D-FLIPFLOP PHASE/FREQUENCY DETECTORS

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digital signals, as shown in Fig.2.1. The output voltage waveforms with A leading B are shown in the gure. The waveforms for B leading A are the same as those for A leading B due to the symmetrical structure of the phase/frequency detector.

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3.1

Laboratory Work
D-Flipops

There are a number of ways to construct a D-ipop in CMOS. Conventional implementations of D-ipop, such as the one shown in Fig.2.2(a), suers from a large number of transistors, high power consumption, and a long propagation delay. True-single-phase-clocking (TSPC) logic circuits initially developed in [1] oer the advantages of a low transistor count, a small chip area, and a fast transient response. In this laboratory, TSPC logic circuits are employed to construct the D-ipop, as shown in Fig.2.2(b) [2, 3]. Only 6 transistors are needed for the construction of the positive-edge triggered D-ipop.

3.2

D-Flipops with RESET

Modify the D-ipop of Fig.2.2(b) by adding a RESET control mechanism that resets Q to Logic-0 when RESET=1. Measure the propagation delay from D to Q and record the delay.

3.3

AND2 Gate

Construct the schematic of an static AND2 gate. Construct the symbol of the AND2 gate. Measure the average propagation delay of the AND2 gate and record the delay.

CHAPTER 2. D-FLIPFLOP PHASE/FREQUENCY DETECTORS


D R QA QA Vm 0 2p QB Df QB Vm -2p 0 Df

15

D R

A B QA QB (a) Df=0

Vm 0 0

A B QA QB (b) Df=p/2 Vm /4

Figure 2.1: D ip-op phase/frequency detector.

3.4

D-ipop Phase/Frequency Detector

Construct the schematic of the D-ipop phase/frequency detector. Apply two square waves A and B of the same oscillation period and duty cycle but dierence phases to the phase/frequency detector. Let input A lead input B with a phase dierence . The following simulations are to be carried out in the laboratory work. Plot the waveform of QA and QB when is in the neighborhood of zero. Both QA and QB for > 0 and < 0 are considered. Estimate the average value of QA and QB over a period. Plot the waveform of QA and QB when is in the neighborhood of . Both QA and QB for > and < are considered. Estimate 2 2 2 the average value of QA and QB over a period. Plot the waveform of QA and QB when is in the neighborhood of . Both QA and QB for > and < are considered. Estimate the average value of QA and QB over a period.

CHAPTER 2. D-FLIPFLOP PHASE/FREQUENCY DETECTORS

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Q CLK CLK Q D

CLK Q CLK CLK

(a)

(b)

Figure 2.2: D ip-ops.


Plot the waveform of QA and QB when is in the neighborhood of 32 . 3 3 Both QA and QB for > 2 and < 2 are considered. Estimate the average value of QA and QB over a period.

Plot the waveform of QA and QB when approaches 2 . Estimate the average value of QA and QB over a period. Use the above estimated average value of QA and QB to construct a plot shown the relation between average output voltage and phase dierence, i.e. the transfer characteristics of the D-ipop phase/frequency detector.

Laboratory Report

A professionally prepared laboratory report containing the followings is due at the start of the next laboratory. The schematic of the resetabble D-ipop with a boarder section showing your name and student ID. The schematic of the AND2 gate with a boarder section showing your name and student ID. The schematic of the D-ipop phase/frequency detector with a boarder section showing your name and student ID.

CHAPTER 2. D-FLIPFLOP PHASE/FREQUENCY DETECTORS

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A table tabulating the exact dimension of all transistors used in your design. The waveform of QA and QB when is in the neighborhood of zero. The plot of QA and QB for > 0 and < 0 are required. The waveform of QA and QB when is in the neighborhood of and < are required. The plot of QA and QB for > 2 2
. 2

The waveform of QA and QB when is in the neighborhood of . The plot of QA and QB for > and < are required. The waveform of QA and QB when is in the neighborhood of and < 32 are required. The plot of QA and QB for > 32 The waveform of QA and QB when approaches 2 . The plot Average output voltage versus phase dierence.
3 . 2

Bibliography
[1] J. Yuan and C. Svensson, New single-clock CMOS latches and ipops with improved speed and power savings, IEEE J. Solid-State Circuits, vol. 32, No.1, pp. 62-69, Jan. 1997. [2] J. Rabaey, Digital Integrated Circuits : A Design Perspective, Upper Saddle River, NJ : Prentice-Hall, 1996. [3] K. Martin, Digital Integrated Circuit Design, New York : Oxford University Press, 2000.

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Chapter 3 Phase-Locked Loops


1 2 Duration: 2 weeks Introduction

Phase locked loops are used extensively in data communications, computer systems, RF communications, instrumentation, and signal processing. The basic conguration of type II phase-locked loops is shown in Fig.3.1. The phase/frequency detector detects the phase/frequency dierence between the incoming signal Vin and the output of the local ring oscillator and converts the phase/frequency dierence into two Boolean control signals UP and DN. The pulse width of UP and DN is proportional to the phase dierence. UP and DN are then fed to the downstream charge pump whose mainly function is to convert UP and DN pulses into currents of constant amplitude. When UP=1 and DN=0, JU P is conveyed to the loop lter, increasing the output voltage of the loop lter. When UP=0 and DN=1, JDN is sinked from the loop lter, lowering the output voltage of the loop lter. The loop lter is a low-pass that lters out the high-frequency components of the output current of the preceding charge pump and outputs a voltage. The output of the loop lter is a dc voltage that controls the oscillation frequency of the

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CHAPTER 3. PHASE-LOCKED LOOPS

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downstream voltage-controlled oscillator (VCO). The oscillation frequency (period) of the VCO is proportional to the phase dierence between Vin and Vo of the VCO. By adjusting the oscillation period of the VCO, the phase/frequency dierence can be driven to zero.
Charge pump JUP Vin Vvco UP PFD DN JDN C1 C2 R2

Loop filter Voltage-controlled oscillator

Figure 3.1: Basic conguration of type II phase-locked loops. In this laboratory, you are required to design a phase-locked loop that makes use of the fully dierential cross-coupled 4-stage voltage-controlled oscillator and the D-ipop phase/frequency detector designed in previous laboratories. In order to construct the phase-locked loop, you are also required to design and analyze two additional function blocks of phase-locked loops, namely the charge pump and the loop lter, as shown in Fig.3.1.

3
3.1

Laboratory Work
Charge Pumps

The main functionality of a charge pump is to convert the width-modulated pulses UP and DN from the preceding D-ipop phase/frequency detector into a current whose amplitude is constant and whose direction is controlled by UP and DN signals. A charge pump is essentially a digital-to-analog converter. Fig.3.2 is the schematic of a current-steering charge pump. The charge pump conveys a constant current JU P to or sinks a constant current

CHAPTER 3. PHASE-LOCKED LOOPS

21

JDN from the output node, depending upon the control signals UP and DN from the preceding D-ipop phase/frequency detector. For more information on charge pumps, please read reference [1] and the main reference text of the course. Construct the schematic of the charge pump and its symbol. The charge pump symbol should have the following inputs : UP, UP, DN, DN, Vout , VDD and VSS . All n-well and substrate contacts are connected to the same power supply and ground as those of the charge pump.
M6

M5

vo UP M3 M4 J UP DN M1 M2 J DN

UP

DN

Figure 3.2: Current-steering charge pump. The charge pump conveys JU P to the downstream loop lter when UP=1 and DN=0. It sinks JDN from the loop lter when DN=1 and UP=0. An implementation of the preceding charge pump is shown in Fig.3.3. The current sources JU P and JDN are generated by the current reference circuit consisting of M79 and the two current mirrors M910 and M911 . Vcp is an external voltage that controls the value of JU P and JDN . Vcp should be assigned as a variable so that it can be adjusted during simulation. You can also make use of advanced biasing circuits studied in ELE704. Note that JU P and JDN must not be too small as they directly aect how fast the control voltage can be controlled by UP and DN signals. They must also not be too large to avoid instability of the phase-locked loop.

CHAPTER 3. PHASE-LOCKED LOOPS

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Vcp

M7

M6

M5

M8 UP M9 M3 M10 M4 UP DN M1 M11

vo DN M2

Figure 3.3: Implementation of the current-steering charge pump.

3.2

Loop Filters

In order to convert the output current of the preceding charge pump into a voltage whose value is proportional to the pulse width of the control signals UP and DN of the charge pump, a loop lter consisting of two capacitors C1 and C2 and a resistor R2 is employed at the output of the charge pump, as shown in Fig.3.1. Note that C2 C1 . C2 and R2 form the main part of the loop lter. Note that high-frequency sparks can pass through R2 C2 network and create reference spurs at the output of the oscillator. To minimize this unwanted eect, a smaller capacitor C1 is used in parallel with R2 C2 to lter out the high-frequency sparks. Construct the schematic of the loop lter and its symbol. The value of C1 , C2 , and R2 should be assigned as variables so that they can be tuned when the phase-locked loop is constructed.

3.3

Open-Loop Test

Construct an open-loop test schematic containing (i) the D-ipop phase/frequency detector, (ii) the current-steering charge pump, and (iii) the loop lter design, as per Fig.3.4. Apply two 900 MHz square waves A and B of the same

CHAPTER 3. PHASE-LOCKED LOOPS

23

oscillation period and duty cycle to the D-ipop phase/frequency detector. Let input A lead input B with a phase dierence . Use parametric analysis of Cadence to sweep and plot the waveform of the output voltage of the loop lter. Repeat the simulation with A lagging B.

Charge pump

JUP A B UP PD DN JDN

Loop filter Vc C1 C2 R2

Figure 3.4: Open-loop test circuit.

3.4

Closed-Loop Test

Construct a 4-stage fully dierential cross-coupled voltage-controlled oscillator as per Fig.3.5. The VCO is very similar to the CCO that you designed in previous laboratories except that the oscillation frequency is now controlled by a voltage rather than a current. The oscillation frequency of the oscillator should be in the neighborhood of 900 MHz. Simulate the VCO for a given control voltage Vc and record the oscillation period (frequency). Make sure that the oscillation frequency of the oscillator covers 900 MHz. Construct a test schematic containing (i) the D-ipop phase/frequency detector, (ii) the current-steering charge pump, (iii) the loop lter design, and the 4-stage 900 MHz fully dierential cross-coupled voltage-controlled oscillator as per Fig.3.5. Apply a 900 MHz square wave to the input A of the phase/frequency detector. The other input of the phase/frequency detector B comes from the output of your VCO. Plot the waveform of A and B, as well as the control voltage Vc of the VCO. When a lock state of the PLL

CHAPTER 3. PHASE-LOCKED LOOPS


Vc

24

Vc
Vo+ Vin-

VoVin+

Figure 3.5: Fully dierential cross-coupled voltage-controlled oscillator. is established, the phase dierence between A and B should be zero and the control voltage Vc of the VCO should settle down to a constant value approximately.

Laboratory Report

A professionally prepared laboratory report containing the followings is due at the start of the next laboratory. The schematic of the charge pump with a boarder section showing your name and student ID. The schematic of the open-loop test circuit with a boarder section showing your name and student ID.

CHAPTER 3. PHASE-LOCKED LOOPS The response of the open-loop test circuit.

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The schematic of the closed-loop test circuit with a boarder section showing your name and student ID. The response of the closed-loop test circuit at the locked state. The waveform of the control voltage Vc of the VCO. A table documenting the exact dimension of all transistors used in your design.

Bibliography
[1] M. El-Hage and F. Yuan, Architectures and design considerations of CMOS charge pumps for phase-locked loops, in Proc. Canadian Conf. Electrical and Computer Eng., Vol. 1, pp. 223-226, Montreal, May 2003.

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Chapter 4 Phase-Locked Loop Chip Set


1 2 Duration : 4 weeks Introduction

In this laboratory, you are required to complete the schematic-level design of a complete chip that contains the phase-locked loop that you designed in the previous labs. Your design and simulation must take into account the eect of bond pads used for soldering bond wires, bond wires used to connect bond pads and traces, traces used to connect traces and pins and, textxture used to model the packaging between traces and pins.

Models for Packaging

CMC provides many packaging options, depending upon the operation frequencies of the design chips. In this lab, you will use 24 CFP (Ceramic 27

CHAPTER 4. PHASE-LOCKED LOOP CHIP SET

28

Flat Pack), which has 24 pins, a small cavity and is suitable for highfrequency (up to 4 GHz) designs. CMC has developed a library for both the package and testxture for 24 CFP. These les are located in

Library : package Cellview : 24cfp_140_half_cell, 24cfp_140_test_fixture_half Note that only a half of the package is provided. You need to make a copy and rotate it to complete the package. These models are valid up to 4 GHz. CMC requires that all unused pins be grounded. This will increase the level of signal isolation and improve the performance.

Models for Bond Pads

Bond pads are not part of the above package. You need to add bond pads explicitly in your design to account for their capacitive eect. CMC does not have bond pad cells developed in package library. CMC requires that the bond pads must not be smaller than 6464. We use 6464 in this laboratory. You need to use this value to estimate the parasitic capacitance of the bond pads. Bond pads should be modeled as a shunt capacitor between signal path and the substrate. M6 M5 are to be connected together and used for the bonding pads. You need to look at the electrical parameter le of TSMC-0.18m CMOS technology to nd out the capacitance from M5 to substrate per unit area to estimate the capacitance of the pads.

CHAPTER 4. PHASE-LOCKED LOOP CHIP SET

29

Models for Bond Wires

Bond wires are also not part of the above package. You need to add bond wires explicitly in your design in order to account for their inductive eect. CMC has developed a bond wire cell located at 1) Library : package 2) Cellview : bondwire The bond wires have a diameter of 31.75 m. The length of the bond wires depends upon the pin/pad assignment and the location of pads. They can only be determined once the complete layout is available. For your simulation, we use the default parameters given in the library (hwl (horizontal wire length)=2000 m, d = 31.75m, r = 0.05,...).

Schematics

In order to take into account the eect of bond wires, bond pads, and packaging, you need to add Bond pads Bond wire cells 24cfp_140_half_cell 24cfp_140_test_fixture_half External test devices, such as supply voltage and loads can be connected directly to the testxture. The arrangement is shown in Fig.4.1.

7
7.1

Laboratory Work
Complete Test Circuit Construction

Construct the complete test circuit of the designed phase-locked loop. The test circuit should contain the follows

CHAPTER 4. PHASE-LOCKED LOOP CHIP SET


Cavity Physical boundary of CFP chip Pad Bondwire

30

Your design
Load External voltage source

Parasitic cap. of pad

Testfixture

Figure 4.1: Simplied schematic of complete chip set The phase-locked loop The bonding pads. The bonding wires. The model for the package. The model for the testxture. External power supply, ground, and input signals.

7.2

VDD and VSS Pads

To minimize the eect of switching noise, for each VDD and VSS connection to the outside, four pads/bond wires should be used. The number of pads are as the followings :

CHAPTER 4. PHASE-LOCKED LOOP CHIP SET

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Table 4.1: Pad assignment of phase-locked loop chip set. Type pf pads Number of pads VDD pads 4 4 VSS pads VCO output pads 8 Input signal pad 1 Charge pump control voltage Vcp pad 1

7.3

VCO Output Buering

To bring the output voltage of the VCO to the outside of the chip, buers are needed in order to drive the parasitics of the package and the load. Add eight voltage buers to the eight outputs of the VCO (Two inverters are connected in series with the rst inverter of small dimensions. Note that the rst inverter should not be made large. Otherwise, it will load the VCO.).

7.4

PLL Test

Apply a 900 MHz 50% duty-cycle square wave to the input A of the phase detector. The other input of the phase detector B comes from the output of your VCO. Plot the waveform of A and B, as well as the control voltage Vc of the VCO. When a lock state of the PLL is established, the phase dierence between A and B should be zero and the control voltage Vc of the VCO should settle down to a constant value.

Layout of PLL

Once the simulation of the designed PLL is completed and design specications are met, it is the time to complete the physical design of the PLL chipset. Since all of you already have the experience in layout in either ELE704 or ELE734, you will nd this step a rather enjoyable design expe-

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rience. Note that you should not make any change to the dimension of all transistors used in your schematic-level design.

8.1

Floor-Planning of PLL

Before you proceed with the actual layout of the PLL chipset, the rst step that you should do is the oor planning. You MUST make a decision on critical issues such as (i) where to route your power and ground rails. (ii) Where to route signals, both low-frequency and high-frequency signals. (iii) How to isolate high-frequency signals from others. (iv) How to assign I/O pins. (v) How to ensure that n-wells are properly connected to the most positive voltage. (vi) Where to put guard rails and how to put the guard rails. (vii) How to protect dc biasing circuits from noisy digital circuits, (viii) How to minimize switching noise, and (xi) How to minimize the interaction between analog and digital circuits of the PLL system.

8.2

Layout of PLL

Once the oor of your PLL is planned, you can proceed with the layout of each functional block of your PLL. The following guidelines should be followed in the layout : (i) Try to put all n-wells together. This will reduce the chip area required for n-wells. Use as many as n+ pull-up connections as possible for n-wells to ensure that n-well is uniformly connected to the most positive voltage of the circuit. (ii) Multiple p+ pull-down connections of the substrate should be used throughout your layout to ensure that the substrate of your chip is uniformly connected to the ground. (iii) Use as many as pins/pads as possible for VDD and VSS connections to minimize the inductance of the bonding wires of VDD and VSS pads subsequently the switching noise associated with these pads. (iv) High-frequency signals should be guarded with either ground or VDD rails to minimize their eect on other parts of the circuit. The bottom line here is to minimize the loop area of high-frequency signal lines so that their inductance is minimized.

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Note that the shielding rails increase the capacitance of the high-frequency signal lines.

8.3

I/O Pin Assignment

The following guidelines should be followed in the assignment of I/O pads and pins: (i) Use as many as pads and pins as possible for VDD and VSS connections to minimize switching noise. (ii) Separate analog pins and digital pins as far as possible. Often analog pins should be guarded with VSS pins (shielding pins). (iii) Separate small-signal pins (input pins) and large-signal pins (output pins) as far as possible to minimize cross-talks from the largesignal pins to the small-signal pins. You should assign input pins to one side of the chip and output pins to the other side of the chip to physically separate them. (iv) Avoid using corner pins and pads. They should be left as dummy. (v) DC biasing pins and clock pins should be dealt with caution as the former are high-frequency pins while the latter are analog pins.

8.4

Layout of Pads

Following the design rules of TSMC for pads. Use only M6 and M5 for all pads to minimize the capacitance from the pads to the substrate.

8.5

Layout of Output Buers

Output buers are usually large in size and generate large switching noise and substrate noise. To minimize their eect, the followings guidelines should be followed : (i) Use a separate set of VDD and VSS pads and pins for the output buers to eliminate the injection of their switching noise to the system. (ii) Use guard rings to isolate the output buers from the rest of the system. Guard ring VDD and VSS should be completely separated from those of the rest of the system as they carry a high level of switching noise. (iii) Minimize the length of the interconnects connecting the output buers and their pads. Techniques should be used to minimize the inductance of these interconnects.

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Laboratory Report

A professionally prepared laboratory report containing the followings is due at the start of the next weeks laboratory. The schematic of the complete test circuit with a board section showing your name and student ID. The response of the closed-loop test circuit at the locked state. The waveform of the voltage of all eight outputs of the VCO. The waveform of the control voltage Vc of the VCO. The complete layout of the PLL chipset. The post-layout simulation results of the waveform of the voltage of all eight outputs of the VCO and that of the control voltage Vc of the VCO.