Departamento de Engenharia Elétrica Centro Tecnológico UNIVERSIDADE FEDERAL DE SANTA CATARINA

Interruptores MOSFET, IGBTs e MCTs Principais características para o comando

Textos extraídos de livros, de relatórios internos do INEP e de notas de aplicações da IR e da Motorola: O transistor IGBT aplicado em eletrônica de Potência - BASCOPÉ, René Pastor Torrico; PERIN, Arnaldo José; Editora Sagra Luzzatto, Porto Alegre – RS, 1997.

AN-937 (v.Int)

Gate Drive Characteristics and Requirements for HEXFET®s
Topics covered: Gate drive vs base drive Enhancement vs Depletion N vs P-Channel Max gate voltage Zener diodes on gate? The most important factor in gate drive: the impedance of the gate drive circuit Switching 101 or Understanding the waveforms What happens if gate drive impedance is high? dv/dt induced turn-on Can a TTL gate drive a standard HEXFET® ? The universal buffer Power dissipation of the gate drive circuit is seldom a problem Can a C-MOS gate drive a standard HEXFET® ? Driving HEXFET® s from linear circuits Drive circuits not referenced to ground Gate drivers with optocouplers Gate drive supply developed from the drain of the power device Gate drivers with pulse transformers Gate drivers with choppers Drive requirements of Logic Level HEXFET® s How fast is a Logic Level HEXFET® driven by a logic circuit? Simple and inexpensive isolated gate drive supplies A well-kept secret: Photovoltaic generators as gate drivers Driving in the MHz? Use resonant gate drivers Related topics (Note: Most of the gate drive considerations and circuits are equally applicable to IGBTs. Only MOSFETs are mentioned for the sake of simplicity. Special considerations for IGBTs are contained in INT-990)

The conventional bipolar transistor is a current-driven device. As illustrated in Figure 1(a). a current must be applied between the base and emitter terminals to produce a flow of current in the collector. The amount of a drive required to produce a given output depends upon the gain, but invariably a current must be made to flow into the base terminal to produce a flow of current in the collector.
+ + +



CURRENT SOURCE (a) Bipolar Transistor


Figure 1. Bipolar Transistor is Current Driven, HEXFET is Voltage Driven

The HEXFET®is fundamentally different: it is a voltage-controlled power MOSFET device. A voltage must be applied between the gate and source terminals to produce a flow of current in the drain (see Figure 1b). The gate is isolated electrically from the source by a layer of silicon dioxide. Theoretically, therefore, no current flows into the gate when a DC voltage is applied to it though in practice there will be an extremely small current, in the order of nanoamperes. With no voltage applied between the gate and source electrodes, the impedance between the drain and source terminals is very high, and only the leakage current flows in the drain.

AN-936 (v.Int)

The Do's and® Don'ts of Using MOS-Gated Transistors
(HEXFET is the trademark for International Rectifier Power MOSFETs) In this application note, some of the most common do's and don'ts of using power HEXFET®s are described. The objective is to help the user get the most out of these remarkable devices, while reducing "on the job" learning time to a minimum. Topics Covered: Be Mindful of the Reverse Blocking Characteristics of the Device Be Careful When Handling and Testing Power HEXFET® s Beware of Unexpected Gate-to-Source Voltage Spikes Beware of Drain or Collector Voltage Spikes Induced by Switching Do Not Exceed the Peak Current Rating Stay within the Thermal Limits of the Device Pay Attention to Circuit Layout Be Careful When Using the Integral Body-Drain Diode Be On Your Gaurd When Comparing Current Ratings

IGBTs have a limited reverse blocking capability of approximately 20-30 V, with high leakage. This is characterized in IR’s data sheets with a Reverse Avalanche Energy (EARV). This rating is useful to absorb energy spikes due to the stray inductance in series with the anti-parallel diode. This is a significant advantage over bipolar transistors and power darlingtons. A feature of power MOSFETs is that they inherently have built into them an integral reverse body-drain diode. The existence of this diode is explained by reference to Figure 1. When the source terminal is made positive with respect to the drain, current can flow through the middle of the source cell, across a forward biased P-N junction. In the "reverse" direction, the power HEXFET® thus behaves like a P-N junction rectifier. The integral body-drain diode is a real circuit element, and its current handling capability is typically as high as that of the transistor itself. Some circuits require an "inverse" rectifier to be connected across the switching device, and in these circuits it will often be possible to utilize the body-drain diode of the HEXFET® provided the proper precautions are taken. Figure 1. Basic HEXFET Structure

The user's first "contact" with a MOS-gated transistor could be a package of parts arriving on his desk. Even at this stage, it behooves one to be knowledgeable about some elementary precautions. Being MOS devices, HEXFET®s can be damaged by static charge when handling, testing or installing into a circuit. Power Devices have large input capacitance, and are able to absorb static charge without excessive buildup of voltage. In order to avoid possible problems, however, the following procedures should be followed as a matter of good practice, wherever possible: • • • MOS-gated transistors should be left in their anti-static shipping bags, or conductive foam, or they should be placed in metal containers or conductive tote bins, until required for testing or connection into a circuit. The person handling the device should ideally be grounded through a suitable wrist strap, though in reality this added precaution is seldom essential. Devices should be handled by the package, not by the leads. When checking the electrical characteristics of the MOS-gated transistors on a curve tracer, or in a test circuit, the following precautions should be observed: Test stations should use electrically conductive floor and table mats that are grounded. Suitable mats are available commercially.

and effectively decouples the gate from its drive circuit for the duration of the transient. but also the voltage transient at the gate is contained to a level at which spurious turn-on does not occur. The following simple precautions should be observed: • • Work stations should use electrically grounded table and floor mats. This inductance exhibits a high impedance for short transients. it is convenient to build this resistor into the test fixture. For repeated testing. be quite easily approximated if the gate drive circuit contains inductance—for example the leakage inductance of an isolating drive transformer. Now that the device has been connected into its circuit. success in applying the device becomes a matter of the integrity of the circuit design. If we assume that the impedance. then any positive-going change of voltage applied across the drain and source terminals (caused. voltage should not be applied until all terminals are solidly connected into the circuit. A more fundamental solution. and well in excess of. From here on. The negative-going gate-to-source voltage transient produced under the above circumstances may exceed the gate voltage rating of the device. particularly when a significant amount of stray inductance is present. the amplitude of the applied drive signal. thereby clamping the dv/dt at the expense of a current transient and increased power dissipation. as the gate will not reach the zener voltage. though in practical terms one may grudgingly be able to accept this circuit operating imperfection. of course. provided the safe operating area of the device is not violated. true that since the applied drain transient results in a voltage at the gate which tends to turn the device ON. in fact. BEWARE OF UNEXPECTED GATE-TO-SOURCE VOLTAGE SPIKES Excessive voltage will punch through the gate-source oxide layer and result in permanent damage. causing permanent damage. of the drive source is high. Z. voltage and current settings should be reduced to zero. it is ready for the power to be applied. However. In practice this “aiming” voltage will not appear on the gate if the dv/dt is positive because the MOS-gated device goes in conduction at approximately Vgs = 4V. by the switching of another device in the circuit) will be reflected as a positivegoing voltage transient across the source and the drain terminals. When using a curve tracer. The problem is illustrated by reference to Figure 2. is to make the impedance of the gate circuit low enough that not only is the gate-source voltage rating not exceeded. . The following are the interrelated device and circuit considerations that lead to reliable.• • • • AN-936 (v. This situation can. In many instances the zener is responsible for generating oscillations in the gate circuit. could produce a voltage transient approaching 50V between the gate and source terminals. This means that a change of drain-to-source voltage of 300V. a resistor should be connected in series with the gate to damp spurious oscillations that can otherwise occur on the trace. 3. but it is not so obvious that transient gate-to-source overvoltages can be generated that are quite unrelated to. and of what circuit precautions have been taken to guard against unintentional abuse of its ratings. in the approximate ratio of: 1 C gs C dg 1+ The above ratio is typically about 1 to 6. Notice that a voltage clamp (a conventional zener diode is suitable for this purpose) to prevent the gate-source voltage rating from being exceeded will not prevent the dv/dt induced turn-on. to avoid the generation of potentially destructive voltage surges during switching. Soldering irons should be grounded. of course. trouble-free design. Spurious turn-on is of itself undesirable. for example. A suitable value of resistance is 100 ohms. for example.Int) When inserting the device in a curve tracer or a test circuit. a negative-going dv/dt will not be clamped. the overall effect is to an extent self-limiting so far as the gate voltage transient is concerned. This calculation is based upon the worst case assumption that the transient impedance of the drive circuit is high by comparison with the gate-to-source capacitance of the device. It is. of course. When switching from one test range to another. Whether this self-limiting action will prevent the voltage transient at the gate from exceeding the gate-source voltage rating of the device depends upon the impedance of the external circuit. This seems obvious enough. The next step is to connect the device into an actual circuit.

there will be no tendency for the device to turn ON. Drain-Source Overvoltage Transient when Switching Off with Unclamped Inductive Load Figure 4. Inductive Load It should be remembered that a collapse of voltage across the device (i. a negative-going dv/dt) will produce a transient negative voltage spike across the gate-source terminals. and hence no tendency for the effect to be self-limiting. A zener diode connected to clamp positive transients will automatically clamp negative-going transients.AN-936 (v. . of course.Int) "POSITIVE GOING" CHANGE DRAIN-SOURCE VOLTAGE D "NEGATIVE GOING" CHANGE DRIVE SOURCE IMPEDANCE Z CDG G CDS CGS WITH NO CLAMPING GATE-SOURCE VOLTAGE S WITH NO CLAMPING EXTERNALLY CONNECTED CLAMPING ZENER DIODE Figure 2. limiting them to the forward conduction voltage drop of the zener.e. A Rapidly Changing Applied Drain-Source Voltage will Produce Gate-Source Transients LS +E +E OVERVOLTAGE TRANSIENT DUE TO L R (b) CLAMPED INDUCTIVE LOAD (a) UNCLAMPED INDUCTIVE LOAD L LS D S R LS OVERVOLTAGE TRANSIENT DUE TO LS E L VDS LS = STRAY CIRCUIT INDUCTANCE Figure 3. In this case.. Drain-Source Overvoltage Transient Produced by Stray Circuit Inductance When Switching Off with Clamped.

by means of careful attention to circuit layout. An alternative clamping circuit is shown in Figure 6. and a clamping device should be connected. HEXFET®s have an inductive energy rating that makes capable of withstanding these inductive spikes. In so doing. however. do not have an avalanche rating. peak transient currents can be obtained that are well in excess of the expected normal operating current. the main inductive component of the load will be "clamped". Inductance is always present to some extent in a practical circuit. are satisfactory for this purpose. consume high in-rush currents if not properly controlled. depending on the voltage and current rating of the circuit. or a "transorb" clamping device. or to slow down the switching of the transistor to limit the peak reverse recovery current of the rectifier. The solution is to use a faster rectifier. and overvoltage transients will still be produced as a result—to say nothing of the fact that the clamping diode may not provide an instantaneous clamping action. when a transistor is switched ON rapidly into a conducting rectifier. The waveform of the voltage across the device should be checked with a high-speed oscilloscope at the full load condition to ensure that switching voltage transients are within safe limits. Note. The faster the device is switched. DO NOT EXCEED THE PEAK CURRENT RATING All power transistors have a specified maximum peak current rating. This is illustrated in Figure 8. physically as close as possible to the drain and source terminals. in a practical circuit. Figure 3 shows how a voltage spike is produced when switching the device OFF. not just at the end of it. Heating. Stray circuit inductance still exists.Int) 4. 5. even though the DC supply voltage for the drain circuit is well below the VDS rating of the transistor. unless proper precautions are taken. as shown in Figure 7. Unexpectedly high transient current can also be obtained as a result of rectifier reverse recovery. The capacitor C is a reservoir capacitor and charges to a substantially constant voltage. while the resistor R is sized to dissipate the "clamping energy" while maintaining the desired voltage across the capacitor. STAY WITHIN THE THERMAL LIMITS . IGBTs. it also slows down the effective switching speed. The first approach to this problem is to minimize stray circuit inductance. It is often overlooked that. LS +E R LS OVERVOLTAGE TRANSIENT CLAMPED BY ZENER (c) CLAMPED INDUCTIVE LOAD WITH LOCAL D-S ZENER CLAMP L LS D VDS S CLAMPING ZENER Figure 5. to the point that whatever residual inductance is left in the circuit can be tolerated. BEWARE OF DRAIN OR COLLECTOR VOLTAGE SPIKES INDUCED BY SWITCHING The uninitiated designer is often not aware that self-inflicted overvoltage transients can be produced when the device is switched OFF. as a result of inductance in the circuit. however. Usually. A simple RC snubber can also be used. assuming that the data sheet limits for energy and temperature are not violated. A snubber is therefore less efficient than a true voltage clamping device. the higher the overvoltage will be. however. there is always danger of inducing overvoltage transients when switching OFF. A technique that ensures that the peak current does not exceed the capability of the device is to use a current sensing control that switches it OFF whenever the current instantaneously reaches a preset limit. of course. This is conservatively set at a level that guarantees reliable operation and it should not be exceeded. and therefore. that an RC snubber not only limits the peak voltage. Note that the highest voltage transient occurs when switching the highest level of current. lighting and motor loads. as shown in Figure 5. Overvoltage Transient at Switch-Off Clamped by Local Drain-Source Zener 6.AN-936 (v. due to its "forward recovery" characteristic. it absorbs energy during the whole of the switching period. A conventional zener diode. for example. The diode D must be chosen so that its forward recovery characteristic does not significantly spoil the transient clamping action of the circuit. as shown in Figure 4. as does a voltage clamp.

PAY ATTENTION TO CIRCUIT LAYOUT . and the switching power. RSA. f. P = PT + PS LS +E EC E D 0 C EC R Figure 6. on the contrary. Overvoltage Transient at Switch-Off Limited by Local Capacitor-Resistor Snubber 7. for a given junction temperature rise DTJ-A. plus the sinkto-ambient thermal resistance. This must be taken into account when sizing the heatsink. multiplied by the operating frequency.(RJC + RC-S) +E OVERVOLTAGE TRANSIENT REDUCED BY SNUBBER R LS E L (d) CLAMPED INDUCTIVE LOAD WITH LOCAL D-S SNUBBER VDS SNUBBER LS D S Figure 7. The first two terms are fixed for the device. is the total switching energy. εT. RJA. and the required thermal resistance of the heatsink. Switching time and switching losses of HEXFET®s are essentially independent of temperature.Int) Power transistors are thermally limited. have switching losses that highly dependent of temperature.AN-936 (v. The total switching loss. The required thermal resistance of the heatsink can be calculated as follows: The transistor conduction power. the total power is due to the conduction losses and the switching loss. RJC. PT. because RDS(on) increases with temperature. PS. Overvoltage Transient at Switch-Off Limited by Local Clamp Since: ∆TJA = PRth where: Rth = junction-to-ambient thermal resistance The junction-to-ambient thermal resistance. PT. is given approximately by PT = On-state Voltage x Drain or Collector current The switching energy depends upon the voltage and current being switched and the type of load. while conduction losses are not. PS. RSA. They must be mounted on a heatsink that is adequate to keep the junction temperature within the rated under the "worst case" condition of maximum power dissipation and maximum ambient temperature. plus the case-toheatsink thermal resistance. It must be remembered that in a switching application. but the conduction losses increase with increasing temperature. can be calculated from: RS-A = RJ-A . eT is the sum of the energies due to the individual switchings that take place in each fundamental operating cycle: PS = εT f The total power dissipation is the sum of the conduction power. IGBTs. RCS. is made up of the internal junction-to-case thermal resistance.

as shown in Figure 8. Note also that it is not necessary to slow the switching-OFF of the HEXFET®. the greater the problem. Using this technique. at the expense of prolonging the high dissipation switching period. . slowing the applied gate drive signal to reduce the peak reverse recovery current of the "opposite" rectifier offers a good practical solution.7mJ for the controlled switch-ON of Figure 9(b). Local decoupling capacitors alleviate the affects of any residual circuit inductance.9mJ. Whether this will be so depends upon the circuit and the operating conditions. whereas it is 2. In order to minimize these effects. hence the energy dissipation at switch-OFF will be relatively small by comparison with that at switch-ON. by using twisted pairs of leads. the peak current of the IRF330 has been decreased from 20A to 10A. the peak reverse recovery current of the integral body-drain diode of the opposite HEXFET® will rise too rapidly. This is done by keeping conduction paths as short as possible. slowing down of the switching speed. For operation at frequencies up to a few kHz. Reverse recovery presents a potential problem when switching any rectifier off. by minimizing the area of current loops. the peak current can be reduced to almost any desired extent. This “local” circuit configuration occurs in most chopper and inverter schemes. Local Circuit Configuration and Operating Condition Requiring Special Care When Using the HEXFET's Integral Body-Drain Diode. the peak reverse recovery current rating will be exceeded. and unwanted oscillations. IF: INDUCTIVE LOAD CURRENT IS FREE-WHEELING IN THE BODY-DRAIN DIODE OF THIS DEVICE THEN: TAKE CARE WHEN SWITCHING-ON THIS DEVICE Figure 8. the two devices forming a tandem series connected pair across a low impedance voltage source. The rate of change of current can be controlled by purposefully slowing down the rate of rise of the gate driving pulse. or by individual resistors in series with each gate. The oscillograms in Figure 9 illustrate the effect. and the device may possibly be destroyed.Int) Stray inductance in the circuit can cause overvoltage transients. If the incoming HEXFET® switches ON too rapidly. or the particular application. 8. where ultra-fast switching is not mandatory. and by using ground plane construction. unexpected unbalance of current between parallel connected devices. Circuit layout should be kept as symmetrical as possible in order to maintain balanced currents in parallel connected HEXFET®s or IGBTs. These measures prevent parasitic oscillations. the "local" circuit operating situation that is troublesome occurs when the freewheeling current from an inductive load is commutated from the integral rectifier of one HEXFET® to the transistor of an "opposite" HEXFET®. I I Regardless of the overall circuit configuration. The switching speed of a circuit which utilizes the body-drain diode of the HEXFET® may therefore be limited by the rectifier. the slower the rectifier. The energy dissipation associated with the “unrestrained” switch-ON in Figure 9(a) is 0. By comparison with the HEXFET® itself. The peak reverse recovery current of the rectifier can be reduced by slowing down the rate of change of current during the commutation process. once these measures have been taken. stray circuit inductance must be minimized.AN-936 (v. BE CAREFUL WHEN USING THE INTEGRAL BODY-DRAIN DIODE The HEXFET®'s integral body-drain diode exhibits minority carrier reverse recovery. the switching speed of the integral reverse rectifier is quite slow. The gates of parallel connected devices should be decoupled by small ferrite beads placed over the gate connections.8ms. By slowing the total switch-ON time from 300ns to 1.

The best advice to the user is to compare different types on the basis of high temperature conduction and switching losses. 100V 10mV (a) I(max) = 20A. For MOSFETS.8 ms. Switching time = 300nsec. Switching time = 1. Bottom Trace: Current 4A/div. To be sure.Int) 9. .AN-936 (v. BE ON YOUR GUARD WHEN COMPARING CURRENT RATINGS The user can be forgiven if he assumes that the continuous drain current rating. and this provides a common basis for comparison. Frequently a "continuous" current rating is assigned to the device which in practical terms cannot be used. because the resulting conduction power dissipation would be so large as to require a heatsink with an impractically low thermal resistance. di/dt = 50A/ms. 2µS 10mV (b) I(max) = 20A. Time Scale: 2ms/div. 2µS Figure 9. Top Trace: Voltage 100V/div. is a much better indication of the power MOSFET true current handling capability. and not of current rating.. that's what it should represent. taken in conjunction with the junction-case thermal resistance. it is sufficient to compare RDS(on) at 25° C. This parameter. that appears on the data sheet represents the current at which the device can actually be operated continuously in a practical system. di/dt = 50A/µs. and/or an impractically low ambient operating temperature. unfortunately it often does not. Oscillograms of IRF330 Switching into Reverse Rectifier of Another IRF330 with Freewheeling Current of 4A.

like an NPN transistor. 3. This is explained in more detail in the next section. If this is necessary. If the device is operated as a switch. Being enhancement-mode DIODE CURRENT devices. it would be an indication of a more fundamental problem: a high impedance drive circuit. This can be better understood by analyzing the basic switching waveforms at turn-on and turn-off for a clamped inductive load. an electric field is set up within the HEXFET®. it is advisable to insert a small series resistor (5-10 Ohms) between the zener and the gate. In either case. 2. Enhancement-mode devices need a gate voltage of the same sign as the drain voltage in order to pass current. Depletion-mode devices are naturally on and are turned off by a gate voltage of the same polarity as the drain voltage. A zener would compound this problem. Unfortunately they also contribute to oscillations and have been known to cause device failures. the stray inductance of the gate connection. a few basic considerations have to be kept in mind in order to avoid a loss in performance or outright device failure. Even if the applied gate voltage is kept below the maximum rated gate voltage. a large transient current capability of the drive circuit reduces the time spent in the linear region. whether in the linear region. as shown in Figures . The opposite is true for P-Channel devices.Int) When a voltage is applied between the gate and source terminals. Care should be exercised not to exceed the gate-to-source maximum voltage rating.AN-937 (v. A transient can get to the gate from the drive side or from the drain side. Basic HEXFET Structure on the gate. may generate ringing voltages that could lead to the destruction of the oxide layer. The silicon oxide layer between the gate and the source regions can be punctured by exceeding its dielectric strength. has a drain voltage that is positive with respect to the source. in combination with the input capacitance of the MOSFET. An N-Channel device. if the device is operated in the linear mode. capable of supplying any amount of current in the shortest possible time. Although it is common knowledge that HEXFET®transistors are more easily driven than bipolars. Field-effect transistors can be of two types: enhancement mode and depletion mode. so that a current can flow from drain to source in an uninterrupted sequence of N-type silicon (drain-channel-source). The data sheet rating for the gate-to-source voltage is between 10 and 30 V for most HEXFET®s. Sometimes a zener is added to reduce the ringing generated by the leakage of a gate drive transformer. All HEXFET®s are enhancementmode devices. SOURCE METALLIZATION SILICON GATE CHANNEL INSULATING OXIDE P N SOURCE GATE OXIDE N N TRANSISTOR TRANSISTOR DRAIN DRAIN All MOSFET voltages are referenced to the source CURRENT CURRENT terminal. coupled with the gate capacitance. thereby reducing the switching losses. This field “inverts” the channel (Figure 2) from P to N. A gate drive circuit with very low impedance insures that the gate voltage is not exceeded in normal operation. THE IMPEDANCE OF THE GATE CIRCUIT To turn on a power MOSFET a certain charge has to be supplied to the gate to raise it to the desired voltage. or in the “saturation” (fully enhanced) region. improving the bandwidth of the stage and reducing the harmonic distortion. Zeners are frequently used “to protect the gate from transients”. that are similar to PNP transistors. to prevent oscillations. GATE VOLTAGE LIMITATIONS Figure 2 shows the basic HEXFET®structure. On the other hand. The best way to achieve this is by means of a voltage source. they will be turned on by a positive voltage Figure 2. rather than solving it. a large current from the gate drive circuit minimizes the relevance of the Miller effect. Overvoltages can also be coupled through the drain-gate self-capacitance due to transients in the drain circuit.

and slows down the rate of rise of voltage appearing directly across the gate and source terminals. and the drain-source voltage starts to fall. the equivalent impedance of the drive circuit has been assumed as purely resistive. Figure 3 shows the waveforms of the drain current. t0. Waveforms at Turn-OFF At time. The .AN-937 (v. This is a negative feedback effect: increasing current in the source produces a counteractive voltage at the gate. This voltage counteracts the applied gate drive voltage. two things happen which make the gate-source voltage waveform deviate from its original “path”. this in turn slows down the rate of rise of the source current. inductance in series with the source which is common to the gate circuit (“common source inductance”) develops an induced voltage as a result of the increasing source current. DRAIN-SOURCE VOLTAGE LOAD DRAIN-SOURCE I STRAY INDUCTANCE DRIVE CIRCUIT RESISTANCE G SE UL EP V I R "D UIT C R CI EN "OP VTH t 0 t1 t2 t3 t4 GATE-SOURCE VOLTAGE "OPEN CIRCUIT" DRIVE PULSE SOURCE INDUCTANCE Figure 3. During the period t1 to t2 some voltage is dropped across “unclamped” stray circuit inductance in series with the drain. At this point. Diagrammatic Representation of Effects When Switching-ON Figure 5. First. the drive pulse starts to rise. which tends to resist the change of current.Int) 3 and 5. Waveforms at Turn-On VOLTAGE DROP ACROSS THIS L MEANS THAT THE DRAIN VOLTAGE FALL RESULTING IN DISCHARGE OF THIS CAPACITOR RESULTING IN MORE CURRENT THROUGH THIS RESISTANCE + DRAIN-SOURCE VOLTAGE ID CURRENT - I DRIVE + IS THIS INDUCED VOLTAGE SUBSTRACTS FROM THE DRIVE VOLTAGE RESULTING IN G-S VOLTAGE "OPEN CIRCUIT" DRIVE PULSE t0 t1 t2 t4 GATE VOLTAGE GIVING I VTH t3 RESULTING IN THIS VOLTAGE RISING MORE SLOWLY RESULTING IN SLOW RISE OF IS Figure 4. The second factor that influences the gate-source voltage is the so called “Miller” effect. For the sake of simplicity. At t0 it reaches the threshold voltage of the HEXFET®s and the drain current starts to increase. drain-to-source voltage and gate voltage during the turn-on interval.

This in turn increases the voltage drop across the source impedance of the drive circuit. The rate of fall of drain voltage is now governed almost exclusively by the Miller effect. This state of affairs continues throughout the period t1 to t2. This also is a negative feedback effect. a step VGS Q2 of voltage is applied between drain and source of the other device on the same leg. A low gate drive impedance would keep the voltage coupled to the gate below the threshold. With reference to Figure 6. Obviously. the HEXFET®is switched fully on. Obviously.Int) decreasing drain-source voltage is reflected across the drain-gate capacitance.AN-937 (v. The drain-tosource voltage now starts to rise. at time t4. which in turn slows down the rise of gate-source voltage. even when A TRANSIENT switching performance is of no great concern. it ON THE GATE is important to minimize the impedance in the VGS Q1 gate drive circuit to clamp unwanted voltage transients on the gate. Finally. the gate voltage reaches a level that just sustains the drain current and the device enters the linear mode of operation. and the gate voltage and drain current start to fall at a rate determined by the gate-source circuit impedance. while the drain voltage falls. Similar considerations apply to the turn-off interval. and increasing the effective capacitive load on the drive circuit. At t3 the rise of drain voltage is complete. and it can be large enough to Changes on the Drain-to-Source Voltage turn the device on for a short instant (“dv/dt induced turn-on”). The Miller effect governs the rate-of-rise of drain voltage and holds the gate-to-source voltage at a level corresponding to the constant drain current. and it continues into the next period. A STEP OF VOLTAGE CAUSES VDS Q1 We have seen how and why a low gate drive VDS Q2 impedance is important to achieve high switching performance. the higher the discharge current through the drain-gate self-capacitance. under which the drain voltage falls at just the rate necessary for the voltage between gate and source terminals to satisfy the level of drain current estab-lished by the load. already flowing in the freewheeling rectifier. IM. at time t3 the freewheeling rectifier starts to support voltage and drain current and voltage start to fall. the lower the impedance of the gate drive circuit. when the freewheeling rectifier goes into reverse recovery. as the current in the HEXFET®rises to the level of the current. This is why the gate-to-source voltage falls as the recovery current of the freewheeling rectifier falls. and the faster will be the rise time of the drain voltage. the lower the impedance of the gate-drive circuit. pulling a discharge current through it. Once again. and the gate-to-source voltage rises rapidly towards the applied “open circuit” value. and an equilibrium condition is reached. when one HEXFET®is turned on or off. This step of voltage is coupled to the gate through the gate-toFigure 6. . These effects are illustrated diagramatically in Figure 4. the less this effect will be. at tl . and decreases the rate of rise of voltage appearing between the gate and source terminals. Finally. Figure 5 shows theoretical waveforms for the HEXFET®in the circuit of Figure 4 during the turn-off interval. Transients of Voltage Induced on the Gate by Rapid drain capacitance. t2 to t3. and tends to resist the increase of drain current. At to the gate drive starts to fall until. the lower the impedance of the drive circuit. then stays constant at a level corresponding to the drain current. the faster will be the fall time of the drain voltage and the switching losses. However. the greater the charging current into the drain-gate capacitance. increasing current in the drain results in a fall of drain-to-source voltage.

4V 7ns Table 1.5mA >2. possibly with several drivers connected in parallel as shown in Figure 9. Section 8 covers the drive characteristics of the logic level devices in detail.4 mA. the guaranteed logic one voltage is 2. interface circuits should be added to provide fast current sourcing and sinking to the gate capacitances. The use of a pull-up resistor in the output.4V 54H / 74H 20mA < (0. 7407. -9 3 PULL-UP RESISTOR VH TTL (TOTEM POLE) LOAD Figure 7.5) / 2. DRIVING STANDARD HEXFET®S FROM C-MOS While the same general considerations presented above for TTL would also apply to C-MOS. With a gate charge of 60 nC and at a switching frequency is 100kHz. DRIVING STANDARD HEXFET®S FROM TTL Table 1 shows the guaranteed sourcing and sinking currents for different TTL families at their respective voltages. Logic Conditions Logic Zero Min. data sheet on-resistance.5V -0.4V) / (54L) / 74L 20mA < (0.4mA > (2.3V) / 0.Int) In summary: MOS-gated transistors should be driven from low impedance (voltage) sources. To drive a MOSFET with a gate charge of 60 nC in 60 ns an average gate current of 1 A has to be supplied by the gate drive circuit.4V 50ns (54LS) / 74LS (4) / 8 < (0. The impedance of this drive circuit. Whenever better switching performance is required.7V 12ns 74S 20mA 0. as necessary to drive the gate of Logic Level HEXFET®s. This is lower than the possible threshold of a HEXFET ®. taking as an example of the 74LS series. it is apparent that. takes the drive voltage up to 5 V. 4. as indicated in INT-944.2mA >2. but is not sufficient to fully enhance standard HEXFET®s. From this table. etc.0mA >2. there are three substantial differences that should be kept in mind: 1.4V -0.7 for 74LS and 74S).4V (2. Driving HEXFET®s from TTL (Totem Pole Outputs) Open collector buffers. but hardly any power is dissipated in them. i.. however. the power lost in the gate drive circuit is approximately: P = VGS x QG x f = 12 x 60 x 10 x 100 x 10 = 72mW The driver devices must be capable of supplying 1A without significant voltage drop.4V 10ns -0. . even with a sourcing current as low as 0.4V) / 0.e. give enough voltage to drive standard devices into “full enhancement”. not only to reduce switching losses. like the 7406. as shown in Figure 7. gives relative long switching times. The on-resistance of the gate drive MOSFETs has to be low enough to support the desired switching times.7V 4ns Logic One Max. C-MOS has a more balanced source/sink characteristic that. but to avoid dv/dt induced turn-on and reduce the susceptibility to noise. sink current for VOL 54 / 74 16mA < 0. One simple interface circuit is the complementary source-follower stage shown in Figure 9.AN-937 (v. source current for VOH Typical Gate Propagation Delay -0. Direct Drive from TTL Output 5. can be thought of as a 500 ohm resistance for operation over 8V and a 1k ohm for operation under 8V (Table 2). on a first approximation.5V -1.4mA >2.

A larger bandwidth can be obtained with better operational amplifiers followed by a current booster. It will certainly not be able to turn OFF the HEXFET®as fast as the TTL. buffer circuits. but also to improve over the switching times of the CMOS output itself and the dv/dt noise immunity. Of course. Switching times are longer than those for TTL (Table 2). but they do not yield any significant improvement in current sourcing. but the internal impedance (assuming that C-MOS are operated from a 10V or higher voltage supply). DRIVING HEXFET®S FROM LINEAR CIRCUITS The complementary source follower configuration of Figure 9 can also be used in linear applications to improve drive capability from an opamp or other analog source. For a system bandwidth of 1MHz. Drivers can also be used. . should be considered. High Voltage TTL driver and its waveforms When C-MOS outputs are directly coupled to the gate of a HEXFET®. gates can be paralleled in any number to lower the impedance and this makes C-MOS a very simple and convenient means of driving HEXFET®s. C-MOS can operate from higher supply voltages than 5V so that HEXFET®saturation can be guaranteed. not only to provide better current sourcing and sinking capability. like the 4049 and 4050 which have a much higher current sinking capability (Table 2). in the order of few V/microsec. 3. Most operational amplifiers have a very limited slew rate. the dominant limitation to performance is not the switching time. like the one shown in Figure 9. the opamp bandwidth must be significantly higher than 1MHz and its slew rate at least 30V/µs. VH 12V 680 Ω 680 Ω IRF320 7407 Figure 8. For better switching speeds. This would limit the bandwidth to less than 25kHz.Int) 2. IRF7307 OR IRF7507 +12V VH LOAD 7 8 1 K 2 1 INPUT 7407 4 3 5 6 Figure 9. like the ones shown in Figures 10 or 11. Simple Interface to Drive HEXFETs from TTL 6.AN-937 (v. while the turn-ON waveform will be slightly better than what can be achieved with a 7407 with a 680 ohm pull-up resistor.

5V > 13. the limiting factors are the slew rate of the comparator and its current drive capability. this transfer can occur in such a short time as to cause a reverse recovery current in the diode high enough to short out the dc bus.6V > 9.1 µF CER 7 8 2 1 Figure 10.75mA > 13.5mA 4mA 20mA Approximate sink current for VOL < 1.1 µF CER 5 6 Figure 11. In many applications. If better switching speeds are desired. ® +12V VH LOAD IRF7309 OR IRF7509 FET INPUT OP AMP INPUTS + 4 -12V 5 6 3 0.5mA 3.5V 40ns 15ns 15V 5V Logic Conditions 5V 10V Logic Zero: 1.4mA -1. Single Supply Op-Amp Drive Circuit (Voltage Follower) .AN-937 (v. an appropriate voltage must be applied between the gate and source.Int) Standard Buffered Outputs Logic Supply Voltage 4049 / 4050 Drivers 10V 40mA -1. Once again.25mA Logic One: > 4.5V 50ns 20ns 15V 40mA -3. a fast op-amp should be used. when the HEXFET is turned on. Driving HEXFET s from C-MOS (Buffered) When analog signals determine the switching frequency or duty cycle of a HEXFET®. 2 CA3103 LOAD IRF7307 OR IRF7507 7 8 2 1 3 + 4 3 0.25mA > 9. too. the gate drive circuit is normally referenced to the source rather than to the ground. and the drive voltage is applied between gate and ground. Response times under 40ns can be obtained at the price of low output voltage swing (TTL compatible).5V -0. it may be necessary to slow down the turn-on of the HEXFET®while leaving the turn-off as fast as practical. the effective voltage between gate and source decreases as the device turns on. like the ones in Figures 12 and 13.5mA -13mA -3. For this reason. If the switching speed is high and the stray inductances in the diode path are small. a voltage comparator is normally used to command the switching.5V Minimum source current for VOH Typical switching times of logic drive signals: 100ns 50ns 40ns 100ns RISE 100ns 50ns 40ns 40ns FALL ® Table 2. For this reason. An equilibrium point is reached in which the amount of current flowing in the load is such that the voltage between gate and source maintains that amount of drain current and no more. as in PWM applications.5V > 2. current transfers from a freewheeling diode into the HEXFET®. DRIVE CIRCUITS NOT REFERENCED TO GROUND To drive a HEXFET®into saturation. There are FET INPUT OP AMP. Under these conditions the voltage drop across the MOSFET is certainly higher than the threshold voltage and the power dissipation can be very high. the use of output buffers like the ones shown in Figures 9. Low impedance pulse shaping circuits can be used for this purpose. Here. If the load is connected between source and ground. Dual Supply Op-Amp Drive Circuit VH +12V 7. may be necessary to improve drive capability and dv/dt immunity.

1 MGDs with optocouplers Most optocouplers require a separate supply grounded to the source on the receiving end of the optical link and a booster stage at the output. This enables the operation of the optocoupler. This is of particular relevance in applications where high currents are being switched rapidly.5V. in the order of 10 V/ns.9V. When powered with a 19 V floating source. the optocoupler needs to be rated for high dv/dt.AN-937 (v. The start-up wave forms are shown in Figure 16.9V. . D2 and R5 form the under voltage lockout circuit. Pulse shaper implemented with an integrator voltage swings between +15V and 3.Int) basically three ways of developing a gate drive signal that is referenced to a floating point: 1. the gate drive Figure 13. Because of the dv/dt seen by the VEE pin.7K 7 8 +12V VH LOAD 3 Figure 12. The tripping point of the under voltage lock-out circuit is 17. VINPUT SLOPE OF V V/SEC RC WITH DIODE CONNECTED AS SHOWN +12V VH LOAD C 7 8 2 R CA3103 1 INPUT + 4 C 5 6 3 Figure 15a shows an MGD with under-voltage lockout and negative gate bias. The LED D2 is used as low voltage. Q3. The switching waveforms shown in Figure 15b are similar to those in Figure 14b except for the negative bias. 2. A pulse shaper. as shown in Figure 14a. By means of pulse transformers. By means of DC to DC chopper circuits with transformer isolation. One of the major difficulties encountered in the use of optocouplers is their susceptibility to noise. INPUT PULSE T = RC WITH DIODE CONNECTED AS SHOWN IRF7307 OR IRF7507 8 INPUT 2 4 2 1 555 6 1 3 R C 5 6 4 4. By means of optically coupled isolators. Q3 turns on when the voltage at the anode of D2 exceeds the sum of the forward voltage of LED and the base-emitter voltage of Q3. D1 and R2 offset the emitter voltage by 3. low current reference diode. The 555 is used as an illustration of a Schmitt Trigger pulse shaper 7.

6k. By changing C1 to 680pF and R3 to 5. in principle. Output : 5V/div Horiz: 500ns/div Figure 14b: Waveforms associated with the circuit of Figure 14a when loaded with 100nF IRF7309 OR IRF7509 7 8 R3 10k R5 4. Other methods of developing isolated supplies are discussed in Section 9. The circuit in Figure 17a can be modified to provide higher output current. as shown in Figure 23.9V EMITTER 3 C VEE Figure 14a. 21 and 22.1 R4 1K Q3 R5 1K 5 6 4 3 2 C2 10 D1 3. 18 and 19.3k 2 ISO1 A VCC OUT EN BATT1 15V 8 7 6 5 C1 0. its performance changes to what is shown in Figures 20. Consequently.2 Pulse transformers A pulse transformer is.AN-937 (v.3k D2 LED 8 7 6 5 2N2222 UNDERVOLTAGE LOCK-OUT OUTPUT BUFFER C1 0. This supply can be used in conjunction with the UV-lockout shown in Figure 15 to provide a simple high-quality optoisolated drive. as shown in Figure 17.9V GATE EMITTER C3 10 3.7K 2 1 ISO1 A VCC OUT EN BATT1 19V IN+ R1 3. As a stand-alone component they can be used for duty cycles between 35 and 65%. Unfortunately it has many limitations that must be overcome with additional components. a simple. Simple high current optoisolated driver The auxiliary supply for the optocoupler and its associated circuitry can be developed from the drain voltage of the MOSFET itself. their output voltage swings from negative to positive by an amount that changes with the duty cycle.9V IN- 3 C VEE HCPL2200 SINGLE TO SPLIT POWER SUPPLY Figure 15a: Optoisolated driver with UV lockout and negative gate bias . Input: 5V/div 7.Int) IRF7307 OR IRF7507 7 8 2 1 GATE R1 3.1 4 3 + C2 10 5 6 3. A transformer can only transfer to the secondary the AC component of the input signal. reliable and highly noise-immune method of providing isolated gate drive.

Gate Voltage: 10V/div VCC(300V) Q1 IRF840 R1 DRIVE 10 DRVRTN Q2 IRF840 R4 R 15VRTN R2 100 D1 1N4148 C2 0.Int) VBATT1 5V/div Input: 5V/div Output: 5V/div Output : 5V/div FILE: 01A-POL. Horiz. Zener current (max output current) for the circuit in Figure 23a. Start-up voltage at 50 kHz for the circuit in Figure 23a.: 500µs/div File: GPS-3.6 k.5V/div Horiz: 5µs/div File: GPS-1. 1 0 20 30 40 50 60 70 Frequency (kHz) 80 90 100 Figure 18.1 D3 15V C1 D2 1N4148 R3 +15V Q1 drain voltage: 200V/div G2 C2 ripple voltage: 0. Waveforms of the circuit in Figure 23a.DAT Horiz: 500ns/div Figure 15b: Waveforms of the circuit in Figure 21a when loaded with 100nF Horiz: 20ms/div File: 01-UV.dat Figure 16. R3 = 5.PLT Figure 19. Drive supply developed from the drain voltage Figure 17b.C1 = 100 pF. . Start-up waveforms for the circuit of Figure 15a.plt Figure 17a. f = 50 kHz 3 Zener Current (mA) 2 C2 voltage: 5V/div.AN-937 (v.

Best results are normally obtained with a few turns of twisted AWG30 wire-wrap wire on a small ferrite core. 20 Gate voltage: 10V/div. The output stage is fed by a dc restorer made by C2 and D1 that references the signal to the positive rail. The complementary MOS output stage insures low output impedance and performs wave shaping. The turn-on and turn-off delays are 50ns. R3 = 1k C2 voltage: 5V/div VGS 0 Figure 23. Figure 21. Start-up voltage at 100 kHz for the circuit in Figure 23a. with C1=680pF.Int) They have the additional advantage of providing a negative gate bias. The power-up wave forms at 50kHz switching frequency and 50% duty cycle are shown in Figure 25.AN-937 (v. In this circuit. . with on/off times from 0. One additional limitation of pulse transformers is the fact that the gate drive impedance is seriously degraded by the leakage inductance of the transformer. and drops back below 10V at the fifth pulse. D1 and D2 are also used to generate the gate drive voltage. f=100kHz. The rise and fall times are determined by the 10 Ohm resistor and the capacitive load. the power-up and power down behavior of the circuit is important. Volt-seconds across winding must balance Horiz: 100µs/div. File: GPS-6. with C1=680pF. Lower gate drive impedance and a wider duty-cycle range can be obtained with the circuit in Figure 24a.plt 20 30 40 50 60 70 Frequency (kHz) 80 90 100 Figure 20.5 to 15 microsecs. R3=R3=1k Due to the lack of an under voltage lock-out feature. Zener current (max output current) for the circuit in Figure 23a.plt Figure 22. with C1 = 680pF. This circuit will operate reliably between 20 and 500 kHz. 10 C2 ripple voltage: 1V/div 0 Horiz: 2µs/div 10 File: gps-4. R3=1k. Q1 and Q2 (a single Micro-8 package) are used to buffer the input and drive the primary of the transformer. Waveforms of the circuit in Figure 23a. During the first pulse. the output voltage is 10V only. Zener Current (mA) Drain voltage: 200V/div. The input and output wave form with 1nF load capacitance are shown in Figure 24b. Intentionally C1 and C2 are much bigger in value then C3 so that the voltage across C3 rises to an adequate level during the first incoming pulse.

Waveforms during start-up for the circuit in Figure 24a.Int) +12V 8 2 IN 4 Q2 IR7509 12VRTN 3 1 Q1 IR7509 D1 IN4148 1 2 3 Q3 1 C1 T1 C2 1 R2 10 R3 G Q4 3 2 10 C4 0.153CM^2) PRIMARY: 17T. FILE: X2-START. OD=0. AWG 28 SEC: 27T.1 R1 100K E 1n LOAD D2 5 6 1 IN4148 IRFL014 OR IRFD014 T1: CORE: 331X1853E2A A1=2600 (PHILIPS. SEC.47 C2 1 D4 11DQ04 100K C1 1 T1 2 3 4 U2 VCC IN VB HO R3 8. Ae=0. Output: 5V/div. Transformer-coupled MGD with UV lockout and short-circuit protection . AWG 28 Figure 26a. +12V 7 8 2 1 INPUT 4 C1 0.625". Ae=0. Improving the performance of a gate drive transformer Input: 5V/div. A1=2600 (OD=0.: 27T Figure 24a.1 12VRTN 5 6 3 0.153 CM^2) PRIMARY: 17T.625". Figure 24b.PLT Figure 25.2K 8 7 6 5 R4 220 D5 C 11DF6 R2 1K G FAULT CS COM VS IR2127/8 C5 10n E T1: CORE: 331X185 3E2A.AN-937 (v. Waveforms associated with the circuit of Figure 24a HORIZ: 50µS/div.

FILE: X1-ERR. It has the following features: . achieves operation over a wide range of duty cycles by using the MGD as a latch. Figure 27.Turn-off delay 200ns . IR2121 ERR pin: 5V/div.Undervoltage lock-out at Vcc = 9. several options are available. The MGD on the secondary side of the transformer is latched by the feedback resistor R4. The fault to shut-down delay is approximately 2 microsecs. D5 is reverse biased and the voltage on C5 keeps raising. The circuit shown in Figure 26a has the following features: . the C2 capacitor keeps the input of the CMOS inverter high and R1 discharges C3. . Shutdown due to high VCEsat The short circuit protection is implemented with a Vce sensing circuit in combination with the current sense input (CS) of IR2127/8.5 Hz .Nominal operating frequency 50kHz (20kHz to 100kHz) . When the HO pin if U2 goes high R3 starts charging C5.5V .PLT Figure 26b.AN-937 (v.Over voltage lock out at Vcc = 20V Input: 5V/div.Duty cycle range from 1% to 99% at 100kHz.Duty cycle range 5% to 85% . Waveforms associated with the circuit of Figure 26a. When the pulse train is interrupted at the input.Optional short circuit protection. . For operation with a large duty cycle. The circuits described in AN-950 use a saturating transformer to transfer the drive charge to the gate.: 500ns/div. Output: 5V/div. Output: 5V/div.Frequency range from DC to 900kHz. . on the other hand.No secondary supply required . as shown in Figure 26a In the circuit of Figure 28a the transformer is small (8 turns). When the collector voltage is high. When C5 voltage exceeds 250mV the IR2127/8 shuts down the output. . Horiz: 1µs/div.Under voltage and over voltage lockout. Threshold Vce = 7.Short circuit protection with Vce sensing. Figures 28b and 28c show the performance of this circuit at the two extremes of 900 kHz and 2. D5 goes into conduction and C5 discharges. The addition of a MOS-Gate Driver IC improves the performance of the circuit in Figure 24a. By the time the input to the CMOS inverter drops below the threshold voltage of Q4. since it transmits only short pulses to the secondary side. The circuit shown in Figure 28a. Horiz. Input: 2V/div.5V . Meanwhile the IGBT turns on.Turn-on delay: 250ns. the collector voltage drops to the saturation level. at the expenses of prop delay.Int) The power down of the circuit is smooth and free from voltage spikes. C3 is completely discharged the output remains low.Propagation delay ~500ns (CL= 10nF) .

ns/div. like short-circuit protection. AWG 28 6 2 1 C2 R2 T1 4. 8. The basic operating principle is shown in Figure 29. A1=2135) PRIMARY: 8T. The on-resistance of standard power MOSFETs is specified at 10 V gate drive. . In addition to providing the gate drive signal. the isolated supply can be avoided.PLT Figure 28b. Input: 2V/div.325". Transformer-coupled MGD for operation from DC to 900 kHz Input: 5V/div.2 Chopping gate drives Chopper circuits can maintain a gate drive signal for an indefinite period of time.AN-937 (v. The diode and the bipolar transistor form a crowbar that rapidly discharges the gate. To turn on the MOSFET. the high frequency transformer is frequently used to power auxiliary circuitry. a burst of high frequency is transmitted to the secondary side. Horiz. Output: 10V/div. Reference 60Hz: 10V/div.7K R3 18K 1 2 3 4 R4 18K U1 VCC IN ERR VSS VB HO CS VS +15V 8 7 6 5 R5 18K G C3 1 E 15VRTN IR2121 Figure 28a. thus avoiding a dedicated supply. File: XP-900K. The MOSFET is turned off by interrupting the high frequency. and are generally not suitable for direct interfacing to 5V logic unless an oversized MOSFET is employed.072cm. Waveforms associated with the circuit of Figure 28a operated at 900 kHz Figure 28c. File: XP-2P5HZ. (OD=0. Ae=0. with some additional circuitry. Output: 25.PLT Horiz: 50ms/div.^2.5 Hz 7. AWG 28 SEC: 8T.Int) IRF7509 OR IRF7309 +12V 7 8 C1 1 IN 4 3 1nF R1 560 5 12VRTN TRANSFORMER: CORE: 266CT125-3E2A. Waveforms associated with the circuit of Figure 28a operated at 2.: 25. have good noise immunity performance and.ns/div. DRIVE REQUIREMENTS AND SWITCHING CHARACTERISTICS OF LOGIC LEVEL HEXFET®S Many applications require a power MOSFET to be driven directly from 5 V logic circuitry.

however. Table 3 summarizes the essential comparisons between standard and logic level HEXFET®s. 8. Gate-source breakdown voltage is lower. reverse transfer capacitance.2V Logic level HEXFET has same value of RDS(on) VGS = 5V as standard HEXFET®at VGS = 10V ® RDS(on) of logic level HEXFET also speed at VGS = 4V Typically 39% larger for logic level HEXFET® Typically 33% larger for logic level HEXFET® Essentially the same Essentially the same Essentially the same Essentially the same Essentially same as VGS = 10V Essentially same at VGS = 5V Same Same ID Same EAS + 20V +10V VGS Table 3: Essential Comparisons of Standard and Logic Level HEXFET®s The gate charge for full enhancement of the logic level HEXFET®is.5 V gate voltage. The logic-level version uses a thinner gate oxide and different doping concentrations.AN-937 (v. The equivalence of switching times at one half the gate resistance for the logic level HEXFET®is illustrated by the typical switching times for the IRL540 and the IRF540 HEXFET®s shown in Table 4. for the same switching speed as a standard HEXFET®power MOSFET. on-resistance. Some important considerations for driving logic level HEXFET®s are discussed in this section and typical switching performance of these is illustrated when driven by some common logic drive circuits. using data sheet test conditions. Gate-Source Voltage VGS(on) RDS(on) gfs Crs Crss Crss Qgs Qgd Qg BVDSS Standard HEXFET® (IRF Series) 2 . Since the gate voltage is halved. Some have guaranteed on-resistance at 2. Since the logic level HEXFET®needs only one half the gate voltage. and output capacitance are all essentially the same. Transconductance is higher. In other words. relative to a standard HEXFET®. drain-source breakdown voltage. the drive energy is only about one half of that needed for the standard HEXFET®. the drive circuit impedance for the logic level HEXFET®must be approximately halved. about the same as for a standard HEXFET®because the higher input capacitance is counteracted by lower threshold voltage and higher transconductance. Characteristics and Ratings Gate Threshold Voltage On-Resistance Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Charge Gate-Source Gate-Drain Total Drain Source Breakdown Voltage Continuous Drain Current Single Pulse Avalanche Energy Max. This has the following effects on the input characteristics: • • • • Gate Threshold voltage is lower.4V ® Comparable Logic Level HEXFET® (IRL Series) 1 . Input capacitance is higher. the gate drive resistance needed to deliver the gate charge in a given time is also halved.Int) Logic level HEXFET®s are specifically designed for operation from 5V logic and have guaranteed on-resistance at 5 or 4.1 Comparison to Standard HEXFET®s Some devices are available as Logic-level HEXFET®s as well as standard HEXFET®s. avalanche energy rating.7 V. While input characteristics are different. .

At high temperature it can approach the VOL(max) specification of the logic driver. +VDD RL D LD DRIVE R1 G R1 G D LD RL +VDD LS LS S LW SIG. and the value specified at VGS = 4V should be used for worst case design. Care should be exercised to insure that VTH(min) at the highest operating temperature is greater than VOL(max) of the various logic families in order to guarantee complete turn off. High common mode inductance Figure 31b. as illustrated in Figure 30. be reached by the addition of a pull-up resistor from the output pin to the 5V bus. RET.Int) Gate Resistance RG (Ω ) 9 4.5 Gate Voltage Drain Current Typical Values (ns) tr 50 56 VGS tr tD on ID tD on (V) (A) 10 28 15 72 40 5 28 15 72 44 Table 4: Typical Resistive Switching Times for IRL540 and IRF540 TTL families do not actually deliver 5V in their VOH condition. S LW RET. The 5V level can. Figure 31a. Minimum common mode inductance . however. the RDS(on) value at VGS = 5V may not be attained. 8.AN-937 (v. even into an open circuit. CONTROL INPUT 15 V +5V 4 8 7 3 555 2 5 8 LOAD 470 LOAD LOGIC INPUTS RET Figure 30. Without the pull-up resistor. RET. SIG. Pull-up resistor used to deliver 5V gate drive Figure 29.2 Driving Logic Level HEXFET®s The gate threshold voltage of MOSFETs decreases with temperature. RET.

RL was built by paralleling 0. The following precautions were also observed: 1. GEN. In the case of logic level HEXFET®s.Int) Common source inductance plays a significant role in switching performance. To minimize inductance in the load circuit. only the internal source inductance LS is common to both load and drive circuits. Only the 5 volt families have been tested as logic level HEXFET®drives: bipolar and CMOS (and their derivatives). To reduce stray inductances and thus achieve maximum switching speeds.AN-937 (v. By eliminating LW from the drive circuit. the source of the DUT was the common return point of all ac and dc system grounds. +5V +VDD = 0. the load current ID does not flow through any of the external wiring of the drive circuit. In the circuit of Figure 31a the switching performance is degraded due to the fact that VGS is reduced by (LS + LW) di/dt.1pF SCOPE 15 Figure 32. as shown in Figure 31b. consequently. This can be done by separately connecting the power return and the drive signal return to the source pin of the switching HEXFET®.5 BVDSS RL DUT +5V 0 SIG. a 0. 10 µF) was reduced to the smallest practical limits. for which VGS is 5V and not 10V.1pF 50 Ω 7. To provide minimum common source impedance. Switching test circuit. even though actual values of LS and LW are the same. 4. 5. VSS 1 2 3 0. 8. 2. Logic level driver is one-quarter of a quad NAND gate. 13 0. 9 10. VGS can approach the applied drive voltage because only LS (the internal source inductance) is common. 4. 3. 12. the loss of drive voltage due to common mode inductance has proportionately twice the effect as it would on a 10V drive signal. TTL GATES DM7400N: 74F00PC: DM74S00N: DM74LS00N: DM74AS00N: Standard TTL High Speed TTL Schottky TTL Low Power Schottky TTL Advanced Schottky TTL . DUT. a 10 µF low-ESR low-ESL capacitor was connected directly from +VDD to the source of the DUT. the physical size of the high current loop (RL.1 µF low-ESR low-ESL capacitor was connected directly between pin 14 and pin 7 of the driver IC. the physical layout of the test circuit was carefully executed so to minimize the common source inductance.5W resistors to achieve the desired load resistance (see Table 5).3 Resistive Switching Tests In the following tests of switching performance. To provide a low source impedance for the 5V gate pulse of the DUT. as indicated below. 5. Thus. where di/dt is the rate of change of the drain current.

092 0.041 0.186 0.133 0.700 0.213 0.173 0. .146 0.036 0.012 0.027 0.120 0.012 0.038 0.269 0.020 0.006 0. LOGIC LEVEL HEXFET® IRLZ14 IRLZ24 IRLZ34 IRLZ44 IRLZ514 IRLZ524 IRLZ524 IRLZ544 SWITCHING VOLTAGE (V) SWITCHING CURRENT (A) RDSON (Ω ) 0.057 0.06 0.25 1.429 0.863 1.041 0.149 0.122 0.068 0. The resistive switching times obtained with the above TTL and CMOS gates are tabulated in Table 6.240 0.174 0.142 0. 0.005 0.007 1.127 0.004 0.161 0.567 0.060 0.0 1.016 0.146 0.033 0.616 0.051 0.Int) CMOS GATES 74AC00PC: 74ACT00PC: MM74HC00N: MM74HCT00N: Advanced CMOS TTL Compatible CMOS Micro CMOS TTL Compatible Micro CMOS BIPOLAR DS0026: High Speed MOSFET Driver The test conditions for the resistive switching performance is shown in Table 5.016 0.139 0.066 0.446 0.052 0.085 RL (Ω ) 3.179 0.159 0.491 0.032 0.008 0.9 8 30 16 30 24 30 40 30 5 50 8 50 12 50 25 50 Table 5.092 0.060 0.227 0.127 0.508 0. In this table ton = Time in microseconds from 90% to 10% VDD and toff = Time in microseconds from 10% to 90% VDD.5 1.199 0. Resistive Switching Conditions Logic Family Quad.176 0.18 0.012 0.233 0.014 0.212 0.328 0.058 0.035 0.060 0.059 0.013 0.125 0. Voltage fall times are essentially the same.126 0.023 0.125 0.036 0.267 0.034 0.018 0.125 0.251 0.183 0.030 0.503 0.60 0.068 0.147 0.007 0.026 0.124 0.179 0.232 0.121 0.132 0.005 IRL544 ton toff 0.111 0. IRLZ34 IRLZ44 IRL514 IRL524 ton toff ton toff ton toff ton toff 0.116 0. N-Channel.090 0.004 0.490 0. Dual Input Nand Gate DM7400N STANDARD TTL 7400FDOPC HIGH SPEED TTL DM7400 SCHOTTKY TTL DM74LS LOW POWER SCHOTTKY TTL DM4SDON ADVANCED SCHOTTKY TTL 74ACOOPC ADVANCED CMOS 74ACTOOPC TTL COMPATIBLE CMOS MM74CHCOON MICRO CMOS MM74HCTCO4 TTL COMPATIBLE MICRO CMOS DS0026 HIGH SPEED MOSFET DRIVER IRLZ14 ton toff 0.062 0.004 IRL534 ton toff 0.052 0.441 0.227 0.12 0.009 Table 6.076 0.086 0.066 0. Results of the resistive load switching test Typical Test Oscillograms IRLZ24: 60V.342 0.005 IRLZ24 ton toff 0.005 Logic Level HEXFET®.146 0.706 0.130 0. TO-220 logic level HEXFET®was driven by each of the logic families listed in Table 4 and the comparative resistive switching times photographed.096 0.7 9.004 0.022 0.111 0.040 0.263 0.028 0.068 0.125 0.068 1.176 0.021 0.036 0.093 0.5 5.136 0.058 0.052 0.044 0.032 0.1 Ohm.896 0.027 0.232 0.029 0.24 0.123 0.663 0.2 0. Inductive switching gives faster voltage rise times than resistive switching due to the resonant charging of the output capacitance of the device.104 0.039 0.016 0.336 0.111 0.238 0.092 0.011 0.124 0.151 0.044 0.549 0.006 0.9 4.008 0.055 0.372 0.AN-937 (v.30 0.438 0.055 0.120 0.778 0.013 0.504 0.066 0.155 0.091 0.034 0.567 0.

the secondary winding is used to demagnetize the transformer and transfer the magnetizing energy to the load. 35 Drain voltage: 10V/div. The switching waveforms are shown in Figure 33b. In several applications. the secondary side of the converter is connected to the output of the power circuit. Horiz: 2µs/div. 100 kHz Forward converter SMALL SIZE. A minimum load of 5mA is required to limit the output voltage at 15V. Waveforms associated with the circuit in Figure 33a Figure 34. The load current vs. Load current vs. causing false triggering and shoot-through.148CM^2. When the MOSFET is off. in about 33% of the cycle. Although the gate drive requires little power. 30 Output Voltage (V) Gate voltage: 5V/div. output voltage characteristic of the circuit is shown in Figure 34. Therefore a transformer with high voltage isolation. The rapid change of high voltage at the output of power circuit stresses the isolation of the transformer and injects noise to the primary side of the transformer. Figure 33a shows a forward converter made with two CD4093 gates to generate the clock and drive the MOSFET. Its key parameters are listed below: OUTPUT VOLTAGE. CURRENT. AI=3000) PRIMARY: 14 TURNS. When the DCDC converter powers a high side switch. 4X IN4148 12K 1N4148 20K IRFD110 5 6 1n 12V RTN 4 13 12 11 100 1µF T1 +12V V0 1µF RL CD4093 f = 100kHz (OD = 0. dv/dt CAPABILITY. The load current required from the DC-to-DC converter is the sum of the current consumption of the drive circuit and the average drive current to the gate. AWG 30 TEFLON INSULATED WIRE SECONDARY: 24 TURNS. 25 20 15 10 0 20 40 60 80 100 120 Load current (mA) Figure 33b. Energy as transferred to the secondary when the MOSFET is on. Switching noise at the primary side disturbs the operation of the converter and the control circuit for the power stage.Int) 9. the noisy environment.AN-937 (v. appropriate creepage distances and low winding-towinding capacitance is required in this application. the circuit works as flyback converter because the demagnetizing current flows through the output. AWG 30 TEFLON INSULATED WIRE T1 TRANSFORMER: DORE: PHILIPS 240XT250-3EA2 TOROID Figure 33a.7 Ohms . Small size and compact layout help reducing the EMI and RFI generated by the converter. thus eliminating the need for a demagnetizing winding. This implies operation at high frequency. To reduce the interwinding capacitances the transformer must be made small. When the output current falls below 5 mA. The output voltage of the DC-to-DC converter is the sum of the positive and negative drive voltage to the gate. SIMPLE AND INEXPENSIVE METHODS TO GENERATE ISOLATED GATE DRIVE SUPPLIES . The ringing in the drain voltage during the fly-back period is due to the loose coupling between the primary and the secondary windings. output voltage at 100 kHz. Ae=0. dc-to-dc converters are used to power the MOS Gate Driver.75". the isolation voltage and creepage distance requirements and the high dv/dt between the primary and secondary size make the design of the DC-to-DC converter somewhat complicated. Rout = 27.

AL=2135 switching losses. The combination of the LED and the photovoltaic generator in one package is called a Photovoltaic Isolator or PVI and is available in a 8-pin DIP package. T1 14 1 1µF 3 1K 1N4148 Otherwise a three-terminal regulator 2 or a small zener-driven MOSFET may IRFD110 9 6K be necessary. Horiz. The switching waveforms are shown in Figure 35b. . The IGBT can only conduct current in one direction while the power MOSFET has an anti-parallel diode that will conduct during every negative half-cycle.: 250ns/div. the PVI1050. except that the 11 4 6 12 higher switching frequency is higher (500 kHz) and the transformer is f = 500kHz 220p smaller. output voltage. Rout = 27. as shown in Figure 39. mainly because the stray inductance of the smaller transformer is higher and the effects of the stray inductance are higher. Bidirectional blocking capability can be achieved by connecting two power MOSFETs source to source. however. 10 1µF 8 The circuit in Figure 35a is similar to 100 RL 13 5 the previous one. A typical application is the ac switch described below. Its simplicity. Waveforms associated with the circuit in Figure 35a Figure 36. while the remaining gates in the package are used to drive the push-pull output stage. 500 kHz Forward converter circuit is higher than the circuit shown in Figure 33a. Load current vs. As a voltage source. AWG30 The output resistance (Rout) of this Figure 35a. or two IGBTs with anti-parallel diodes emitter to emitter. As a gate driver the PVI has significant limitations: its short circuit current is in the order of 30 microA with a very high internal impedance. Figure 37a shows a pushpull operated at 500 kHz. a zener IN4148 V0 +12V can provide the necessary regulation. More information on the PVI can be found in Application Note GBAN-PVI-1 which appears in the Microelectronic Relay Designer’ s Manual. where switching times are not important and switching transients are not present.375".AN-937 (v. Ae=0.072CM^2. PRIMARY: 4T. the PVI can function as a “dc transformer” by providing an isolated low current to a load. makes it appealing in solid-state relay replacements. 25 Output voltage (V) Gate voltage: 5V/div. PHOTOVOLTAIC GENERATORS AS GATE DRIVERS A photovoltaic generator is a solid state power supply powered by light. The IGBT and the power MOSFET are not suited to switching AC waveforms directly.Int) If the converter is loaded with a 4X constant and predictable load. While an optoisolator requires a bias supply to transmit a signal across a galvanic barrier. normally an LED.7 Ohms 10. 30 Drain Voltage: 10V/div. 20 15 10 0 10 20 30 Load current (mA) 40 50 Figure 35b. A circuit is also provided in the AN to significantly speed up turn off of the switch. SECONDARY: 7T. The single gate oscillator produces a 50% duty cycle output. This data book also contains the data sheet for the photovoltaic isolator. The primary of the transformer sees half the voltage compared to the previous circuit. The remaining three gates in 7 CD4093 12V the package are connected in parallel RTN to drive the MOSFET and reduce the T1: CORE: PHILIPS 266CT125-3E2A (od=0. the PVI actually transmits the energy across the barrier. therefore the number of turns at the primary were reduced to half. AWG 30.

Int) In the case of the MOSFET. the gate drive losses are proportional to the resistance of the gate drive circuit.: 500ns/div Figure 37b.072CM^2.AN-937 (v. output voltage. Ae=0. as shown in Figure 40. to achieve hard switching at this frequency. Clearly. RESONANT GATE DRIVE TECHNIQUES As indicated in Section 14. an isolated drive is necessary. The design and layout of such a circuit is not an easy task.7 Ohms . Furthermore. The gate drive for both the MOSFETs and IGBTs must be referenced to the common sources or emitters of the devices. while simplifying the design of the gate drive circuit itself. there is the possibility that. 500 kHz Forward converter 11. AWG30 Figure 37a. Waveforms associated with the circuit in Figure 37a 20 19 18 17 16 Related Topics 15 MOS-Gate Driver Ics Transformer drive with wide duty cycle capability Gate Charge Three-phase MOS-Gate Driver Photovoltaic Isolators (PVI) 14 13 0 10 20 30 40 50 60 Figure 38. SECONDARY: 7T. Buffer Output: 5V/div. independent from the value of the gate drive resistor. Horiz. that is. The MOSFET channel is a bidirectional switch. the current flows through both MOSFET channels. then the majority of the current will flow through the MOSFET channel instead of the intrinsic diode. adding whatever inductance is necessary to achieve resonance at the desired frequency.6 W. If the voltage across the MOSFET channel is less than the VF of the intrinsic diode (which typically has a higher VF than discrete diodes). An IRF630 operated at 10 Mhz with a gate voltage of 12 V would have gate drive losses of 3. AL=2135 PRIMARY: 4T. This method can reduce the peak of the gate drive current and losses in half. May 1994. Load current vs. thereby achieving lower overall voltage drop. page 297). AWG 30. for low current levels. the stray inductance of the gate drive circuit must be limited to tens of nH. An alternative method to drive the gate in such an application is to design a resonant circuit that makes use of the gate capacitance and stray inductance as its reactive components. +12V 1 10K 5 6 2 9 4 CD4093 12V RTN 220p 8 13 12 14 3 10 100 11 4 1µF 2 7. More information on this gate drive method can be found in an article by ElHamamsy: Design of High-Efficiency RF Class-D Power Amplifier and in references at the end of this article (IEEE Transactions on Power Electronics. 6 1N4148 V0 1µF RL IRF7307 7 f = 500kHz 1N4148 T1: CORE: PHILIPS 266CT125-3E2A (od=0. it can conduct current in the reverse direction. The PVI can be used. gate drive losses in hard switching are equal to Qgs x Vgs x f. Since the gate charge is not dissipated at every switching transition. Since this node will be swinging with the AC waveform. instead that one MOSFETs and diode. the resistance of the gate drive circuit is limited to whatever is associated with the internal impedance of the driver and with the gate structure of the device itself. 8 100nF 100nF T1 1 3 7T 2T 5. rather than being independent from it. Buffer input: 5V/div. Rout=27. but stored in a reactive component.375".

the gate-to-drain capacitance though smaller in static value than the gate-to-source capacitance. .1 microfarad capacitor C1. In actuality. This affects the total input admittance of the device which results in the total dynamic input capacitance generally being greater than the sum of the static electrode capacitances. a phenomenon by which a feedback path between the input and output of an electronic device is provided by the interelectrode capacitance.1µF charge is defined as 22pF . the circuit is not open but involves a capacitance that is a function of the voltage gain. but to a much lesser extent. The phenomenon of the effects of the plate impedance and voltage gain on the input admittance was first studied in vacuum tube triode amplifier circuits by John M. at high frequencies where the grid-to-plate (gate-to-drain) capacitance is not negligible. Gate C1 . A constant current in the drain circuit is set by setting the voltage on the gate of HEXFET POWER MOSFET 1.Int) Use Gate Charge to Design the Gate Drive Circuit for Power MOSFETs and IGBTs Topics covered: • • • • • Background Test method How to interpret the gate charge curve How to estimate switching times How to compare different devices 1. Although the gate-to-source capacitance is an important value. This gate-to-drain capacitance function is similar to that found in vacuum tube amplifiers.1µF drive circuit +20V +20V HEXFET 1 requirements. even with vacuum tubes where much is known.AN-944 (v. In this circuit. or input. Test Circuit Figure 1. so the net measurement of the charge consumed by the gate is relative to a given current and voltage in the source-to-drain path. HEXFET POWER MOSFET Gate Charge Circuit. the gate-to-drain capacitance is actually more significant—and more difficult to deal with—because it is a non-linear capacitance affected as a function of voltage. capacitance listed on the data sheet. through the regulator diode D1. Therefore. Essentially. The gate-to-drain capacitance effect is akin to the “Miller” effect. U1B IG VGS 2. A typical test circuit that can be used to measure the gate charge is shown in Figure 1. or to achieve 4 U1A full switching. the gate-to-drain or “Miller” capacitance typically requires more actual charge than the input capacitance. International Rectifier supplies a “gate charge” specifications . either to swing 5 1 3 1/2 7 DUT DS0026 the gate by a given 1N414B 4. an approximately constant current is supplied to the gate of the device-under-test from the 0. Input behavior of a MOS-gated transistor Designers unfamiliar with MOSFET or IGBT input characteristics begin drive circuit design by determining component values based on the gate-to-source.1µF 100pF 5V ID MONITOR the charge that must 5-10 MSEC +V + 1W5301 500Hz be supplied to the 8 .68µF for its IGBTs and + HEXFET POWER ID SET 100Ω 9V 100K MOSFETs.7K 1K 100Ω V51Ω amount. goes through a voltage excursion that is often more than 20 times that of the gate-to-source capacity.D1 gate. RC value based on the gate-to-source capacitance normally lead to a gate drive that is hopelessly inadequate. but is even more difficult in MOSFETs. To account for both gate-to-source and gate-to-drain capacitance in a way readily usable by designers. the gate-to-source capacitance is also affected as a voltage function. that can 2W be used to calculate . Solving for the "Miller" effect is not exactly a straightforward process. Miller.

then the total gate charge actually consumed would be about 20 nanocoulombs. The graph in Figure 3 represents gate voltage versus gate charge in nanocoulombs for an IRF130. The importance of the gate charge data to the designer is illustrated as follows. therefore. The total charge consumed by the gate will therefore in practice be higher than the minimum required-but not necessarily significantly so. the device will be drain voltage of 80 volts and a drain current of 12 amps. the horizontal time scale is directly proportional to the charge supplied to the gate. Gate Voltage Versus Gate Charge for the IRF130. For example. and decreases with increasing voltage. Consider a typical practical example of a 100 kHz switcher. about 15 nanocoulombs of gate if 1.e. ID =1A.5 amps is supplied to the gate. relates the gate voltage to time. then switching occurs in 1 ms.AN-944 (v. both capacitances are charged to the extent needed to switch the given voltage and current.5 mA. A more detailed explanation of the interpretation of this data is given later.Int) OPW 2 VZR 0 2V 2µS 1 WFM 2 WFM WFM 2µS OPW 0 VZR 0 2V 0 WFM 0 WFM WFM OPW 3 VZR 0 2V 2µS An oscillogram of the gate-to-source voltage during testing. the designer can develop a drive circuit appropriate to the switching time required. As shown on the graph. and the corresponding gate voltage is about 7 volts. Since the 15 nC gate charge is the product of the gate input current and the switching time. With gate charge known. If the applied drive voltage has an amplitude of 10 volts (i. there is a much less than proportional difference in the charge required. These simple calculations immediately tell the designer the trade-offs between the amount of current available from the drive circuit and the achievable switching time. During the first voltage rise. C VDS = 10V 10V 80V 80V B 14 2 WFM 3 WFM WFM 12 10 Figure 2. whether switching 10 volts or 80 volts in the drain circuit. normal design safety margins will dictate that the level of drive voltage applied to the gate is greater than that which is just required to switch the given drain current and voltage. VGS VOLTS 8 A 6 4 ID = 1A 2 ID = 12A 0 5 10 15 20 25 30 QG NANOCOULOMBS Figure 3. a 3 volt margin). . in which it is required to achieve a switching time of 100 nanoseconds. switched in 10 nS. 40 and 80 volts). the gate-to-source capacitance is charging. the gate charge required to switch 12 amps at 80 volts is 15 nanocoulombs (point A). (point B). This oscillogram therefore clearly differentiates between the charge required for the gate-source and gate-to-drain (“Miller”) capacitances. and so on. this oscillogram is a plot of gate voltage versus charge. and during the flat portion. Although the second voltage rise indicates the point at which the switching operation is completed. This is because the “Miller” capacitance is a nonlinear function of voltage. It follows that if 15 mA is supplied to the gate. VDD = 10. Gate Charge Waveform for Different Values of Drain Voltage (IRF130: lG = 1. shown in Figure 2. At the second voltage rise. With a suitable scaling factor. the gate-to-drain capacitance is charging. The point on the oscillogram of the second voltage rise indicates where the device is fully switched on. Since a constant current is supplied to the gate. Taking the charge are required to switch a previous example.

the designer can further arrive at the drive circuit impedance. the gate voltage now stays constant because the “enforced” drain current is constant. Since the gate voltage is inextricably related to the drain current by the intrinsic transfer characteristic of the DUT (so long as operation remains in the ID “active” region). VDD. the device under test (DUT) supports the full circuit voltage. PDRIVE. no further charge is consumed by the gate-to-source capacitance. the freewheeling rectifier stays in conduction. The Gate Charge Curve The oscillograms of the gate-to-source voltage in Figure 2 neatly delineate between the charge required for the gate-to-source capacitance. So long as the actual drain current is still building up towards the available drain current. From this calculation. because charge is equal to the product of current and time. or “Miller” capacitance.AN-944 (v. is QGVGf. and the gate-to-source voltage increases. the potential of the drain now is no longer tied to the supply voltage.9W. the gate voltage continues to rise and the drain current rises proportionally. and is free to increase. and for practical purposes it can be neglected. and the drive circuit charge now contributes exclusively to discharging the “Miller” G capacitance. the switch S is closed. the gate-to-source capacitance continues to charge. and the gate voltage and drain current are zero. for instance. the gateto-source capacitance starts to charge. 100 X 10-9.038 Watts. VDD. (In bipolar transistor Figure 4. it has reached “saturation. The additional charge consumed after time t3 does not represent “switching” charge. Thus the length of the period t0 to t1 represents the charge QGS consumed by the gate-to-source capacitance. This is because the drive current flows for such a short period that the average power is negligible. Thus actual drive power for MOSFETs is minute compared to bipolar requirements. Basic Gate Charge Test Circuit terms.Int) The required gate drive current is derived by simply dividing the gate charge. The accompanying simplified test circuit and waveform diagram ( Figures 4 and 5 respectively) give the explanation. and the charge required for the gate-to-drain. whilst the drain voltage starts to fall. Before time t0. the average power is minuscule (0. and assuming a gate drive voltage VG of 14 volts. the gate voltage is constant at about 7 volts. but even at 5 MHz it would be only 1. the appropriate value of gate charge QG is 27 nanocoulombs (point C on Figure 3).” The gate voltage is now no longer constrained by the transfer characteristic of the device to relate to the drain current. The average drive power is therefore 27 X 10-9 X 14 X 105 = 0. The drain current now stays constant at the value ID enforced by the circuit. into the “Miller” capacitance CAD. Taking the above 100 kHz switcher as an example. ID. of course. The top end of the drain-to-gate capacitance CAD therefore remains at a fixed potential. For the time being therefore. Average drive power. The charging current taken by CAD during this period is small.004%) in relation to the power being switched in the drain current. The total charge at time t3 is the charge required to switch the given voltage VDD and current ID. until time t4. VDD. increases at higher frequencies. During period T1 to t2. S is opened at time t0. which must sustain switching current during the entire ON condition. it is simply the excess charge which will be delivered by the drive circuit because the amplitude of the applied gate drive voltage normally will be higher (as a matter of good design practice) than the bare minimum required to accomplish switching. 15 X 10-9. when the gate voltage becomes equal to the voltage “behind” the gate circuit current source. The gate charge data also lets the designer quickly determine average gate drive power. Note that throughout the “flat” part of the switching period (Figure 3). because the gate voltage remains constant. . If the drive circuit applies 14 volts to the gate. then a drive impedance of about 50 ohms would be required. and the voltage across the DUT continues to be virtually the full circuit voltage. the voltage across it remains low. since CAD is numerically small by comparison with GCS. No current flows in the drain until the gate reaches the threshold voltage. by the required switching time. The time scale on the oscillogram of the gate-to-source voltage is directly proportional to the charge delivered by the drive circuit. and the current remains constant throughout the whole sequence. the drain current reaches ID. At t3 the drain voltage falls to a value equal to ID x RDS(ON) . At time t2. CDG D in its entirety. The average gate drive power. 3. This it does. The drain voltage excursion during the period t2 to t3 is relatively large. whilst the potential of the lower end moves with that of the gate. giving 150 mA. Thus the drive current now diverts. whilst the length of the period t2 to t3 represents the charge QGD consumed by the gate-to-drain or "Miller" capacitance. and the DUT now comes out of the “active” region of operation. The difference between the applied 14 volts and 7 volts is what is available to drive the required current through the drive circuit resistance. and hence the total drive charge is typically higher for the “Miller” S IG S CGS capacitance CAD than for the gate-to-source capacitance GCS. and the freewheeling rectifier +VDD shuts off. Even though the 150 mA drive current which flows during the switching interval may appear to be relatively high.

about the same as that of device Y. because it has a higher transconductance and therefore requires less voltage on its gate for the given amount of drain current (VGX is less than VGY) The “Miller” charge consumed by device X is considerably less than that consumed by device Y. QX. of “bottom line” importance is the total gate charge required for switching. Beware When Comparing Different Products Manufacturers sometimes make technical claims for their products that appear to be plausible. Had the comparison between devices X and Y been made on the more superficial basis of input capacitances. To summarize: beware of superficial comparisons. (Point 1 for device X. The energy is the product of the gate charge and the gate voltage. but which in actuality do not stand up to scrutiny. Related Topics: Gate drive considerations for IGBT modules Gate drive characteristics of IGBTs Gate drive requirements of MOS-gated transistors High-voltage gate drive ICs Three-phase gate drive IC Gate drive IC for ballasts Transformer-isolated gate driver . A general comparison between hypothetical MOSFETs brands “X” and “Y” is illustrated in the Figure. ergo Y is a faster switch than X”. QY. is considerably less than that required to switch device Y. Check the full facts before deciding which MOSFET really has the edge in switching performance. Apart from the obvious speciousness of many such statements — “apples” are frequently not compared with “apples”. Statements such as “the input capacitance of device Y is less than that of device X.Int) 4.AN-944 (v. Again. and is represented by the area of the rectangle whose corner lies at the “switching point”. Device X has a higher input capacitance. however. and point 2 for device Y. A case in point concerns the input capacitance of a power MOSFET. The lower the charge.) It is obvious that X requires significantly less gate energy than Y. are frequently bandied about.2 DIAGONAL CORNERS) IS GATE ENERGY FOR DEVICE Y Q AREA OF THIS RECTANGLE (0. As this application note shows. device X scores handsomely over device Y in this example. but are just as frequently erroneous. QGS of device X is. QGS QGD VG GATE VOLTAGE VG(TH) t0 t1 t2 DRAIN VOLTAGE t3 t4 t DRAIN CURRENT VDD ID WAVEFORM Figure 5. and obviously larger chips have more self capacitance than smaller ones—the more basic fundamentals are generally overlooked. The overall result is that the total charge required to switch device X. hence the initial slope of its gate charge characteristic is less than that of device Y. Another consideration is the energy required for switching. Comparison of Gate Charge Characteristics of Different Device Types. it would have been concluded— erroneously— that Y is “better” than X. Basic Gate Charge Waveforms VG QY QDGY QDGY DEVICE Y DEVICE X VGX 0 QDGX QX 1 2 AREA OF THIS RECTANGLE (0.1 DIAGONAL CORNERS) IS GATE ENERGY FOR DEVICE X VGY Figure 6. the lower is the gate drive current needed to achieve a given switching time.

a large duty cycle is required (Figure 1). and provides electrical isolation. Unfortunately. This “constant volt seconds” property of transformers results in large voltage swings if a narrow reset pulse. shown as a MOSFET. furthermore. which is used to control the drive signals to Q2.AN-950 (v. In Figure 2. typical of power devices. transformers can deliver only AC signals since the core flux must be reset each half cycle. DC isolation and either step up or step down capability. Most of them require a buffer stage to handle the large gate capacitances. Waveform Characteristics of HEXFET POWER MOSFET Driver Circuit The circuit in Figure 2 provides a low impedance turn-on drive. THIS CAUSES RESET VOLTAGE TO BE 3 TIMES APPLIED VOLTAGE E.. providing the switching function for a switching power supply. B 0 -12V +12V C 0 -12V VDS POWER HEXFET Q2 VGS POWER HEXFET Q2 T1 WINDING VOLTAGE Optoisolators for power electronics require high dV/dt capability and are expensive. Constant-Volt-Seconds Characteristics of Transformers Q2 POWER SWITCH 1:1 Figure 2. it can have any desired voltage ratio. Ql is a low power HEXFET Power MOSFET such as the IRLML2803. If duty cycles are such that optoisolators are the only alternative. i. and coupling to. They also require additional floating power sources which add complexity and cost. and minimum pulse widths (on or off) of approximately 1 microsecond. E T -3E T/3 NOTE: VOLT-SECONDS PRODUCT IN SHADED AREAS MUST BE EQUAL. For large duty cycle ratios designers must choose an A LOW LEVEL LOGIC SIGNAL 0 alternative to the transformer. the low level circuitry. motor drive or other application requiring isolation between the low level logic and high power output. and T1 is a small 1:1 driver transformer providing electrical isolation from. . they can be used in a more cost-effective way as drivers for a MOS-gate driver. duty cycle or roughly equal pulse widths positive and negative because of drive voltage limitations of the semiconductors +12V themsevles.Int) Transformer-Isolated Gate Driver Provides very large duty cycle ratios (HEXFET® is the trademark for International Rectifier Power MOSFETs) Transformer coupling of low level signals to power switches offers several advantages such as impedance matching. They also provide negative gate bias to reduce the risk of “dv/dt induced turn-on”.e. Q2 is the main power device. D 0 Figure 3. such as -12V an optical coupler to provide the +12V necessary drive isolation. Wide Duty Cycle HEXFET Power MOSFET Driver circuit For this reason transformers in semiconductor drive circuits are limited to 50%. Q1 Z1 T1 Figure 1.

and the signal source is a low impedance driver such as a PWM controller or gate driver. with a consequent turn-on time of around 75nsec. Note that because T1 need only support a 12V signal. during the negative half cycle. showing that it is indeed a mirror image of waveform A. When this voltage is applied to the primary of T1 the waveform is supported by changing core flux until saturation occurs as shown in waveform B. which. When waveform A goes 12 volts negative Ql will become fully enhanced. When T1 saturates. Waveform A is the desired logic signal to be switched by Q2. This will again be less than 10 Ohms and will yield a turn-off time less than 100nsec.1 mF capacitor. IRF840 IRFD1ZO IRF840 IRFD1ZO HEXFET AVALANCE PROTECTION IRF840 IRFD1ZO IRF840 IRFD1ZO Figure 5. its winding voltages fall to zero and Q1 turns off. it is very small—and inexpensive. In a practical circuit Z1 is frequently a 0. 8A per Section) The drain voltage of the power HEXFET Power MOSFET Q2 appears in Figure 3d. In a practical circuit this can be less than 10 Ohms total.AN-950 (v. and the main switch Q2 will now be turned off at approximately -12V at a source impedance Z1 + RDS(ON) of Q2. At this time the winding voltages fall to zero and remain so until the core flux is reversed by the negative-going portion of waveform A saturation will again occur if the negativeapplied pulse exceeds the voltseconds capability of the core. High Voltage. for 1msec or less. of course.Int) The waveforms in Figure 3 explain the circuit operation. As T1 voltage collapses. VIN VO GROUND REFERENCE LOGIC Figure 4. the intrinsic diode of Q1 isolates the collapse of voltage at the winding from the gate of the power device and the input capacitance Ciss of the power switch holds the gate bias at the fully enhanced condition for a time limited only by the gate leakage current of Q2 as indicated in Figure 3c. has the same form as the primary. the intrinsic diode of Ql is in forward conduction and Q2 receives a positive gate drive voltage with a source impedance of Z1 plus the intrinsic diode forward impedance. . When T1 again saturates. the gate of Q2 also follows this voltage and remains at zero bias. High Power HEXFET Power MOSFET Switch (500V. Single Switch Regulators During the positive portion of the secondary waveform. the desired low level logic signal.

the transformers were built from miniature tape wound or ferrite toroids. Square Permalloy 80 cores are more expensive than ferrite types. but they have much narrower hysteresis loops and hence need fewer ampere turns of excitation.AN-950 (v. Bi-directional AC Switch using HEXFET POWER MOSFET Figure 7. The second is a bi-directional ac switch. #80558-(1/2D)MA #52402-ID (2) Ferrite Toroids Ferroxcube #266CT 125-3E2A or equivalent IRF840 IRFD1Z0 ON INTRINSIC DIODES IRFD1Z0 IRFD1Z0 OFF ADDITIONAL CAPACITANCE FOR LONG SWITCH PERIODS IRF840 Figure 6.Int) It should be noted that the circuit in Figure 3(b) may not provide the necessary noise immunity when the power device is off. The size of core should be chosen so that adequate insulation thickness can be used for the isolation voltage requirements and to reduce interwinding capacitance. high-frequency switch. by adding another small N-Channel HEXFET Power MOSFET (typically another IRLML2803) as shown in Figure 7. and it is also important to space the turns to occupy 360° of the core circumference to minimize leakage inductance. The gate-source voltage of Q2 in the OFF state returns to zero when T1 saturates and the only noise immunity is provided by the threshold voltage of Q2 (2V < VTH < 4V). The circuit now provides -12V to the power MOSFET after the transformer saturates. Bifilar windings improve the magnetic coupling of primary to secondary. Typical part numbers for these cores are as follows: (1) Tape Wound Cores Magnetics Inc. a minimum of 14V noise immunity is provided which should be adequate for all applications. Unity turn ratios between primary and secondary also serve to minimize leakage inductance and hence optimize the transformer coupling coefficient. The cost and noise immunity of this solution is much less than alternatives using optoisolators and their auxiliary supplies. Figures 5 and 6 show two applications where this gate drive method is particularly advantageous. In most applications it may be desirable to provide more noise immunity. The first is a high-voltage. This can make a critical difference when the driver has limited current capability. Thus. and this reverse bias remains until the next positive half cycle of drive. Driver Circuit with additional Noise Immunity Choice of a core type is not critical provided that 10 to 20 turns bifilar of suitable wire can be hand-wound onto it. Related Topics: MOS-gate drivers Negative gate bias . Transformer T1 Considerations In the circuits illustrated.

com 1 9/14/99 .3 40 125 1. VGS @ 10V Pulsed Drain Current  Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt ƒ Operating Junction and Storage Temperature Range Soldering Temperature.9 -55 to + 150 300 (1.6mm from case ) 10 lbf•in (1. Avalanche and dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current l Effective Coss specified ( See AN 1001) l TO-220AB GDS Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG Continuous Drain Current. for 10 seconds Mounting torqe. Reset ( Both for US Line Input only ) through … are on page 8 Notes  www. 6-32 or M3 screw Max.55Ω ID 10A Benefits Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate.92004 SMPS MOSFET IRF740A HEXFET® Power MOSFET Applications Switch Mode Power Supply ( SMPS ) l Uninterruptable Power Supply l High speed power switching l VDSS 400V Rds(on) max 0.irf. 10 6.PD. Reset Single Transistor Forward Xfmr.1N•m) Units A W W/°C V V/ns °C Typical SMPS Topologies: l l Single transistor Flyback Xfmr.0 ± 30 5. VGS @ 10V Continuous Drain Current.

7 1490 52 61 Max. ID = 6. See Fig. IS = 10A.48 ––– ––– ––– ––– ––– ––– Max.50 ––– Max.0A 36 ID = 10A 9. ID = 1mA 0.0V.0 ––– ––– ––– ––– Typ.0 ––– 62 Units °C/W Diode Characteristics Min. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) Gate Threshold Voltage V(BR)DSS IDSS IGSS Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. VDS = 320V.5 Units mJ A mJ Thermal Resistance Parameter RθJC RθCS RθJA Junction-to-Case Case-to-Sink. . I D = 250µA ––– V/°C Reference to 25°C.irf. Units Conditions ––– V VGS = 0V. ––– ––– 2. ––– 0. ƒ = 1. 4.0MHz ––– VGS = 0V.5Ω. TJ = 125°C 100 VGS = 30V nA -100 VGS = -30V Dynamic @ TJ = 25°C (unless otherwise specified) gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Units Conditions ––– S VDS = 50V. VDS = 0V to 320V … Avalanche Characteristics Parameter EAS IAR EAR Single Pulse Avalanche Energy‚ Avalanche Current Repetitive Avalanche Energy Typ.0MHz. See Fig.0MHz ––– VGS = 0V. IF = 10A ––– 1. 630 10 12.0 V VDS = VGS. V DS = 1. 1. 5 ––– VGS = 0V. 400 ––– ––– 2. ––– ––– ––– Max.0 V TJ = 25°C. Units IS ISM VSD trr Qrr ton Conditions D MOSFET symbol 10 ––– ––– showing the A G integral reverse ––– ––– 40 S p-n junction diode. Flat. ––– 0. 10 „ ––– VGS = 0V ––– VDS = 25V ––– pF ƒ = 1.0A „ 4. Greased Surface Junction-to-Ambient Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)  Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Typ. VGS = 0V „ ––– 240 360 ns TJ = 25°C.9 µC di/dt = 100A/µs „ Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2 www.55 Ω VGS = 10V.See Fig. VGS = 0V µA 250 VDS = 320V. 6 and 13 „ ––– VDD = 200V ––– ID = 10A ns ––– RG = 10Ω ––– RD = 19.9 2. Max.IRF740A Static @ TJ = 25°C (unless otherwise specified) Parameter Drain-to-Source Breakdown Voltage ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. ––– ––– ––– ––– 10 35 24 22 1030 170 7. ƒ = 1.9 nC VDS = 320V 16 VGS = 10V.9 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Typ. VGS = 0V. ID = 6. ID = 250µA 25 VDS = 400V.

0V BOTTOM 4.0 9. Drain-to-Source Voltage (V) Fig 1.0 0.0V 5.5 0.1 0.0V 7.0V BOTTOM 4.0 TJ = 25 ° C V DS = 50V 20µs PULSE WIDTH 5.5V 4.1 20µs PULSE WIDTH TJ = 150 °C 1 10 100 VDS .irf. Typical Transfer Characteristics Fig 4.0 7.0V 5.0V 3 . Temperature www.IRF740A 100 VGS 15V 10V 8.0 -60 -40 -20 VGS = 10V 0 20 40 60 80 100 120 140 160 VGS .0 ID = 10A RDS(on) . Drain-to-Source Current (A) VGS 15V 10V 8.5 10 2. Drain-to-Source Current (A) 2. Normalized On-Resistance Vs.5 1 1.01 0.0V 6.0 6.0V 7.5V 5. Drain-to-Source Current (A) 10 I D . Gate-to-Source Voltage (V) TJ .5V TOP 10 1 1 0.0 10.1 0.5V 20µs PULSE WIDTH TJ = 25 °C 1 10 100 0.5V 5.0 8.1 4. Junction Temperature ( °C) Fig 3.1 4.5V TOP 100 I D . Drain-to-Source Voltage (V) VDS . Drain-to-Source On Resistance (Normalized) I D .0 0. Typical Output Characteristics 100 3. Typical Output Characteristics Fig 2.0 TJ = 150 ° C 1.

C ds SHORTED Crss = C gd Coss = C ds + C gd 16 C. f = 1 MHZ Ciss = C gs + Cgd .IRF740A 20 100000 ID = 10A VDS = 320V VDS = 200V VDS = 80V VGS .Source-to-Drain Voltage (V) VDS . Capacitance(pF) 1000 Ciss 12 100 Coss 8 10 Crss 4 1 1 10 100 1000 0 0 10 20 FOR TEST CIRCUIT SEE FIGURE 13 30 40 . Drain-to-Source Voltage (V) Fig 7.1 0. Reverse Drain Current (A) 10us 10 I D . Drain-to-Source Voltage (V) Q G . Gate-to-Source Voltage (V) 10000 VGS = 0V.2 1.4 0. Gate-to-Source Voltage 100 100 OPERATION IN THIS AREA LIMITED BY RDS(on) ISD .irf.4 1 TC = 25 ° C TJ = 150 ° C Single Pulse 10 100 10ms 1000 VSD . Drain Current (A) TJ = 150 ° C TJ = 25 ° C 1 100us 10 1ms 0. Maximum Safe Operating Area 4 www. Typical Gate Charge Vs. Total Gate Charge (nC) Fig 5.0 1.2 V GS = 0 V 0.6 0. Typical Capacitance Vs.8 1. Typical Source-Drain Diode Forward Voltage Fig 8. Drain-to-Source Voltage Fig 6.

001 0. + RG I D . Case Temperature td(on) tr t d(off) tf Fig 10b. Drain Current (A) -VDD 6.01 0.irf.001 0.50 0.IRF740A 10. Junction-to-Case www.00001 t1 . Switching Time Waveforms 10 Thermal Response (Z thJC ) 1 D = 0. Maximum Drain Current Vs.0 D.10 0. Peak T J = P DM x Z thJC + TC 0.1 % 4.20 0.05 0. Switching Time Test Circuit 2.01 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1.0 Fig 10a.1 1 10 5 .0001 0. Rectangular Pulse Duration (sec) Fig 11. Duty factor D = t 1 / t 2 2. Maximum Effective Transient Thermal Impedance.0 25 50 75 100 125 150 TC .02 0.0 VDS 90% 0.U.0 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.01 0.0 VDS VGS RD 8.1 0. Case Temperature ( °C) 10% VGS Fig 9.T.

Avalanche Voltage ( V ) 580 560 Charge 540 Fig 13a.T IA S + V . 520 50KΩ 12V .T. Unclamped Inductive Waveforms QG Fig 12c. Single Pulse Avalanche Energy (mJ) TOP BOTTOM 1200 VDS L D R IV E R ID 4. Junction Temperature ( °C) IAS Fig 12b.DS 480 1.0 IAV .DD 800 A 0 .0 10.0 3.0 9. Basic Gate Charge Waveform Current Regulator Same Type as D.3µF 500 D.U.5A 6.0 7.T.0 2.0 8. Maximum Avalanche Energy Vs.IRF740A 1 5V 1400 EAS .com .irf. Unclamped Inductive Test Circuit V (B R )D SS tp 400 200 0 25 50 75 100 125 150 Starting TJ .0 6.U.0 5. Avalanche Current ( A) IG ID Current Sampling Resistors Fig 13b. Avalanche Current 6 www. Drain Current 10 V QGS VG QGD V DSav .0 1 Ω 600 Fig 12a. Typical Drain-to-Source Voltage Vs.0 4.2µF . VGS 3mA + V . Gate Charge Test Circuit Fig 12d.U .3A 10A 1000 RG 20V tp D .

U. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 14.U. Period VGS=10V * D.irf.T.U.T.IRF740A Peak Diode Recovery dv/dt Test Circuit D. .T.T + ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ‚ - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.Device Under Test + VDD Driver Gate Drive 7 .U. ISD controlled by Duty Factor "D" D.W. For N-Channel HEXFETS www.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D. Period D= P.

7 0. 1. Na literatura. foram desenvolvidos os semicondutores totalmente controlados de potência (na entrada em condução e no bloqueio) para sua aplicação no desenvolvimento de conversores estáticos de potência.5 2 1.SC 1 . A partir de 1970. em estado de condução.Transistores IGBTs. Observando as curvas da Fig. Em condições de comutação dissipativa o IGBT pode operar até freqüências de 25kHz.9 1. • Elevada capacidade de corrente de coletor: pelo fato de apresentar uma característica de saída idêntica ao transistor bipolar de potência.5 4 primeira geração 3. Por natureza. os dispositivos tem possibilitado a diminuição das perdas de condução devido às cada vezes menores queda de tensão em estado de condução VCesat. dependerá das condições de comutação (Hard Commutation ou Soft Commutation). num único dispositivo híbrido que denomina-se transistor IGBT (Insulated Gate Bipolar Transistor). • Não apresenta problemas de segunda avalanche: o dispositivo pode suportar simultaneamente elevadas tensões e correntes de curta duração sem apresentar problemas de destruição pelo fenômeno de segunda avalanche. Até 1970.ESTRUTURA FÍSICA E PRINCÍPIO DE OPERAÇÃO DO IGBT Desde que se desenvolveu o primeiro no fim de 1957. 1 . com a evolução. a escolha da freqüência de operação do transistor. tem surgido grandes progressos no desenvolvimento de dispositivos semicondutores de potência.0 segunda geração terceira geração quarta geração Fig. implicando em baixos custos. é possível dizer que.5 3 2. o que diminui as perdas de comutação. 1 [1]. • Baixas perdas de condução: o canal do IGBT. • Operação em tensões elevadas: com o incremento da espessura das camadas do substrato N-base. aplicações e circuitos de comando René Pastor Torrico Bascopé e Arnaldo José Perin INEP – Instituto de Eletrônica de Potência Departamento de Engenharia Elétrica – Centro Tecnológico – UFSC Caixa Postal 5119 – 88040-970 – Florianópolis .5 0. é consideravelmente menos resistivo pelo fato de ter-se o substrato P junto ao coletor. O IGBT tornou-se comercialmente disponível na década de 80 com a primeira geração. foi possível alcançar tensões de operação acima de 1000V [3]. porém são menos rápidos que os transistores MOSFETs de potência. ♦ Operação em Altas freqüências : é possível operar o interruptor até 200kHz em condições de comutação não dissipativa [7]. sendo atualmente o mais avançado em tecnologia disponível e o mais utilizado comercialmente pelas características indicadas a seguir [2]: • Controle por tensão: a entrada em condução e o bloqueio do dispositivo são controlados aplicando-se tensão entre gate e emissor. A evolução das gerações de cada fabricante ocorre de uma maneira similar como é mostrado no exemplo da Fig.Curvas típicas de evolução das gerações dos IGBTs.8 0. fato este que acontece no MOSFET de potência.3 0. responsável pela injeção dos portadores minoritários (lacunas) na camada resistiva do canal (N-base).4 0.1 – CARACTERÍSTICAS GERAIS Para vencer as limitações dos transistores bipolares e MOSFET. tem possibilitado uma comutação cada vez mais rápida. 1. A característica de entrada é idêntica ao MOSFET de potência: sua elevada impedância de entrada denota simplicidade para o circuito de comando. O fluxo de corrente de coletor é dado pelos portadores minoritários. Este dispositivo pertence à família de dispositivos bi-MOS.6 0.5 1 0. os tiristores convencionais foram utilizados de maneira exclusiva para o controle da energia elétrica em aplicações industriais. os IGBTs são mais rápidos que os transistores bipolares de potência (BJT) por não apresentarem o problema do tempo de estocagem. VCEsat [V] 4. características. este dispositivo também é conhecido como Conductivity Modulated Field-Effect Transistor (COMFET)[5]. sem ocorrer o incremento da resistência do canal. Devido às perdas de comutação pela presença da corrente de cauda (que ocorre na transição do estado condução-bloqueio). realizou-se uma integração de suas vantagens: capacidade de corrente de coletor (característica do transistor bipolar) e controle por tensão aplicado entre gate-emissor (característica do MOSFET de potência).2 0. o dispositivo possui uma elevada capacidade de condução de corrente de coletor (centenas de ampères). Ao mesmo tempo.1 0. .5 0 t f [ µ s] 0 0.

3 – PRINCÍPIO DE OPERAÇÃO Como o IGBT resulta da combinação de uma estrutura MOS e de uma estrutura bipolar. pois o canal é constituído por elementos altamente resistivos (substrato tipo N) e a maior parte das suas perdas ocorre nesta região em estado de condução. como mostram a Fig. composto pelos transistores bipolares PNP e NPN. que consiste na adição. garantindo desta maneira a capacidade de bloqueio reverso do dispositivo. para tal finalidade. No IGBT. de elementos químicos em pequena proporção. A modulação de condutividade no caso de um MOSFET não é favorável.Circuito equivalente do IGBT Canal N e o seu símbolo. Para mudar suas características elétricas e torná-lo um melhor condutor. A sua construção é baseada no semicondutor de silício (Si). sua análise difere de ambos os dispositivos de potência. Para compreender sua operação. 3. N-base. o substrato tipo N é obtido dopando o silício com elementos químicos pentavalentes (cinco elétrons na camada externa de valência). é necessário o conhecimento da física do transistor MOSFET e do transistor bipolar.Estrutura física e circuito equivalente do IGBT canal N.3. reduzindo-se desta maneira de modo considerável a queda de tensão e. Nesta seção é descrito o princípio de operação do dispositivo e. O componente MOSFET canal N do circuito equivalente.6 V (o transistor parasita NPN não deve ser polarizado). depende essencialmente da espessura da camada resistiva N-base. 1. 3. pelo simples fato da junção J3 (formada entre as camadas P+ e N-base) estar polarizada reversamente. 2 e consiste basicamente de quatro camadas: substratos P+. Esta característica é mostrada através da Fig. O substrato tipo P é obtido dopando o silício com elementos químicos trivalentes (três elétrons na camada externa de valência). a sua respectiva destruição por aquecimento. Este processo também é conhecido como modulação de condutividade. é realizado o processo de dopagem. 1. A operação deste tiristor é altamente indesejável. É importante deixar claro que a tensão de ruptura reversa. A polarização reversa da junção provoca a formação de uma camada de depleção na região. 2 e a Fig. Coletor Tiristor R mod T1 iC PNP (Gate) G (Coletor) C iMOS ibasePNP T2 Gate NPN R st (Emissor) E Emissor Fig. 1) deve ser bem baixa. tipicamente 70% num dispositivo de 500V [8]. dado pelos substratos N-base.2 – ESTRUTURA FÍSICA A estrutura física de um transistor IGBT canal N é mostrada na Fig. a resistência Rst do substrato P-base (Fig. A estrutura é constituída de camadas de substratos que são chamados P e N. P-base e N+. ao semicondutor. a camada P+ é um substrato com forte dopagem de Boro (pouco resistiva) e a camada N-base é um substrato com dopagem de Fósforo (altamente resistiva). Na realidade. a potência dissipada internamente. por conseqüência. tem a função de controlar a corrente de base do transistor PNP durante sua operação. que podem ser: Boro.EMISSOR GATE EMISSOR N+ N+ R st T 2 P-BASE N+ J1 J2 N+ P-BASE N-BASE P+ T 1 R mod J3 METAL SiO (Dióxido de Silício) 2 COLETOR Fig. Por outro lado. relativas à estrutura do . 2 . P-base e N+. apesar de ter-se uma tensão positiva entre gate-emissor (VGE) acima do valor de limiar (threshold voltage). não é considerada a situação da operação do tiristor parasita que provoca perda de controle da corrente de coletor. As duas tecnologias modernas existentes atualmente.1 – Capacidade de bloqueio reverso O IGBT não entra em condução (fluxo de corrente de coletor) quando uma tensão negativa entre coletor-emissor (VCE) é aplicada. PT (Punch-Through) e NPT (Non-Punch-Through). que podem ser: Fósforo ou Antimônio [6]. A formação da junção entre estas duas camadas permite a injeção de portadores minoritários no canal quando o IGBT está no estado de condução. Gálio ou Índio. como conseqüência. neste estado [2]. A presença das quatro camadas gera um tiristor parasita. de maneira a reduzir a queda de tensão à valores inferiores a 0. 3 . 1. no IGBT a corrente de coletor é basicamente controlada através deste componente. Para evitar sua destruição. pois provoca a perda do controle da corrente de coletor e.

Por este motivo é reduzida drasticamente a resistência do canal do IGBT em relação à resistência do canal do MOSFET de potência. a corrente de coletor decresce continuamente de maneira mais lenta devido à alta densidade de portadores minoritários injetados na região N-base. que inicialmente tem um valor positivo de tensão. proporcionada pela injeção de portadores minoritários (lacunas) desde a região P+ dentro da região N-base altamente resistiva. Como resultado. Como a camada N-base do IGBT deixa de ser altamente resistiva com a injeção de portadores minoritários. o que resulta numa corrente de coletor residual indesejada que somente causa perda de energia durante a comutação de bloqueio do dispositivo. que devido à presença de indutâncias parasitas do layout e do próprio dispositivo. tem-se a súbita redução à zero da corrente do canal MOS devido aos elétrons. vence-se a depleção da junção J2 entre as camadas P-base N-base e a depleção da junção J3 entre as camadas P+ N-base (ambas as junções devem ser polarizadas diretamente). que situa-se na faixa de 0. Com esta condição. Na Fig. quando encontra-se em estado de condução. Esta característica permite operar o IGBT com elevadas densidades de corrente durante o estado de condução. Observando o circuito equivalente do IGBT mostrado na Fig. que é a mesma corrente que flui pelo canal MOS é igual a: ibasePNP = iMOS = iC/(1+βPNP). 4 . Esta queda abrupta pode ser alterada controlando-se a tensão entre gate-emissor durante o bloqueio. VGE iC vCE vCE iC aumento de R GE aumento de R GE cauda t t1 t iC ∆Ic t Fig. Tais portadores necessitam de tempo para sua recombinação. 5). Para realizar a transição do estado de condução ao estado de bloqueio.Características de bloqueio e corrente de coletor com a variação de RGE durante o bloqueio A característica de saída do IGBT é controlada através da tensão aplicada entre gate-emissor VGE. O bloqueio é realizado em condições de tensão coletor-emissor positiva. acima da tensão de limiar. o bloqueio da corrente de coletor do IGBT é realizado através do MOSFET que bloqueia a corrente de base do transistor PNP. como conseqüência. muitas vezes podendo provocar sua destruição. é alcançado reduzindo-se a tensão entre gate e emissor abaixo do valor de limiar (VGEth – Gate-Emitter Threshold Voltage). 5 . Isto implica que a corrente de base do transistor PNP.∆IC . A queda abrupta da corrente de coletor (∆Ic) causa variações de corrente de coletor (dic/dt) de elevado valor. A resistência no canal do IGBT é baixa devido à modulação de condutividade. A tensão abaixo do valor de limiar é alcançada curto-circuitando o terminal gate ao terminal emissor com um resistor de baixo valor de resistência. 5 é mostrada a . IC região ativa incremento da tensão de gate V CER característica reversa I CR característica direta VCE Fig.000V é suficiente aumentar a espessura desta camada.4 a 0. Isto é alcançado com a descarga lenta da capacitância de entrada através de uma resistência adequada ligada entre gate e emissor durante o bloqueio. a junção J2 é polarizada reversamente bloqueando o fluxo de corrente através do canal MOS do dispositivo. para aumentar a capacidade de operação com tensões acima de 1. do transistor PNP do circuito equivalente. A tensão gate-emissor positiva deve ser suficientemente elevada.Característica de saída do IGBT (genérico) 1. Após cair abruptamente. é ligado ao emissor por um circuito externo. Aplicando-se estas duas tensões. Esta corrente residual é conhecida na literatura como corrente de cauda (tail current) [7].5. é grande devido ao baixo ganho de corrente (βPNP).no instante t1 (Fig. A descida abrupta da tensão entre gate e emissor até um valor abaixo do limiar permite. um decrescimento abrupto da corrente de coletor até um certo valor.2 – Capacidade de condução direta Para que o IGBT encontre-se em estado de condução direta (forward conduction). o gate. 1. A magnitude da queda abrupta da corrente de coletor . 3.3. A densidade de portadores minoritários injetados na região N-base é tipicamente de 100 a 1.3 – Capacidade de bloqueio direto O bloqueio do IGBT. apresentam características de saída diferentes [9]. para que a resistência do canal MOS seja pequena durante o fluxo de corrente de coletor.000 vezes maior que o nível de portadores da camada N-base do MOSFET de potência.dispositivo. geram elevadas tensões sobre o interruptor durante o bloqueio.3. é necessário aplicar simultaneamente tensões positivas entre gate-emissor (VGE) e coletor-emissor (VCE). provocando-se a descarga da capacitância intrínseca de entrada dada pelo paralelo das capacitâncias entre coletor-gate e gate-emissor.

para uma mesma capacidade de corrente nominal. já que este tempo reflete-se no tempo de subida da corrente de coletor.diminuição da corrente de coletor (dic/dt) com o incremento do valor do resistor conectado entre gate e emissor durante o bloqueio. sendo portanto conveniente aplicar uma tensão gate-emissor elevada (na faixa de 12V a . o valor de diC/dt. é ínfima [5] ( Fig. o IGBT entra em condução. diminuindo-se o tempo de subida da corrente de coletor.Comutação na Entrada em Condução Para analisar as perdas e esforços e relacioná-las ao circuito de comando. O circuito de comando de gate deve permitir uma operação adequada do interruptor IGBT nos estados de condução. VG1 0 RG(on) RG(off) IGBT1 D1 Ls1 E1 tm t m= tempo morto RG(on) RG(off) VG2 0 IGBT2 D2 Carga Indutiva E2 L s2 braço Fig. desta maneira minimiza-se as perdas em estado de condução. quando o sinal de tensão gate-emissor sobe rapidamente na entrada em condução. pois ambas grandezas se relacionam. Quando a comutação finaliza. 6 . corrente indesejada. Uma vantagem do IGBT em relação ao MOSFET. Aplicando um pulso positivo de tensão entre os terminais gate-emissor VGE de valor acima do limiar (∼5V). também permite reduzir estas derivadas de tensão. provoca elevadas interferências de rádio freqüência (RFI) e eletromagnéticas (EMI). Estas derivadas de tensão podem causar oscilações de tensão de gate. A pequena resistência RG(on) indicada anteriormente em série com o gate do dispositivo. ou capacitância Miller) por meio de uma fonte de tensão de baixa impedância durante a aplicação do pulso.Circuito em meia ponte para a análise dos tempos de comutação. 5. Com um circuito bem projetado as perdas de condução e comutação são mínimas com moderados esforços de tensão e corrente. provoca-se um crescimento abrupto da mesma.dic/dt). permitindo o aumento de perdas na entrada em condução. a colocação de uma resistência RG(on) de baixo valor em série com o gate do dispositivo.1.Em Estado de Condução O valor da tensão de saturação coletor-emissor VCEsat deve ser o menor possível. é considerado o circuito de potência em meia ponte (half-bridge) com carga indutiva mostrado na Fig. o tempo de subida da tensão entre os terminais gate-emissor VGE deve ser também o menor possível. Este circuito apresenta dois interruptores no braço operando complementarmente com comutação dissipativa. evitando sua possível destruição devido aos diferentes potenciais de tensão de coletor e emissor. Para o caso de cargas resistivas. Isto pode ser conseguido carregando-se rapidamente a capacitância de entrada Cies do dispositivo (que constitui-se das capacitâncias gate-emissor CGE e gate-coletor CGC.). comutação na entrada em condução e no bloqueio. 2 . Além disso. aumentando a magnitude da corrente de recuperação reversa do diodo em antiparalelo com o IGBT complementar.2 . tensão coletor-emissor.1 – PERDAS E ESFORÇOS RELACIONADOS AO COMANDO 2. circuito grampeador. o efeito da redução da corrente de cauda.CIRCUITOS DE COMANDO Pelo fato de apresentar uma impedância de entrada elevada. Uma elevada tensão de gate ajuda a transferir rapidamente a carga necessária. portanto. É importante indicar que com o incremento do valor do resistor conectado entre gate e emissor (RGE) durante o bloqueio. ou seja. etc. a tensão coletor-emissor VCE desce rapidamente.1 . 2. como é mostrado na Fig. No caso de persistir a sobretensão. é a baixa capacitância de entrada determinando um baixo consumo de energia [10]. embora as indutâncias parasitas do circuito de comando possam ser minimizadas colocando-se o circuito de comando o mais próximo possível do dispositivo. Para minimizar a perda de comutação na entrada em condução (turn-on) o tempo de subida (rise time) da corrente de coletor (iC) deve ser o menor possível. cujos fenômenos serão explicados a seguir. apresenta importância fundamental no rendimento e custo do conversor. Observa-se que deve existir um compromisso de otimização de perdas e esforços de sobretensão. encontra-se num valor muito baixo (tensão de saturação) e este valor depende da tensão gate-emissor VGE. vencendo os efeitos das resistências e indutâncias parasitas do circuito de comando de gate. 5). Esta descida rápida provoca uma dvCE/dt que injeta correntes dentro do circuito de comando através da capacitância coletor-gate CCG. é possível controlar o tempo de subida da corrente de coletor do IGBT. Para alcançar esta característica. pode-se limitá-la em um valor dentro da área RBSOA. bem como sobretensão no interruptor complementar devido à presença de indutâncias parasitas (Ls1 e Ls2) que existem no circuito de potência e que podem ser diminuídas através de um layout apropriado (v=Ls. A resistência de gate. Deste modo. proporcionando também o isolamento entre o circuito de controle e o circuito de potência. 6. protegendo o dispositivo da destruição.1. Por outro lado. requerendo baixa potência da fonte de tensão do circuito de comando de gate. o IGBT é controlado por um sinal de tensão adequado aplicado entre gate e emissor VGE. 2. Aconselha-se portanto. Neste tipo de configuração os dispositivos suportam os maiores esforços de sobretensão e sobrecorrente. a tensão sobre o dispositivo. com a utilização de um circuito externo (circuito snubber.

Formas de onda de: tensão coletor-emissor. tempo: 200ns/div [10].) e analisando os efeitos de diC/dt e dvCE/dt. tempo: 200ns/div [10]. não podendo ser reduzida por meios externos (através do circuito de comando).entrada em condução do tiristor parasita devido ao fluxo de corrente capacitivo interno [10]. provocando picos de tensão gate-emissor acima do valor de limiar. Com relação ao tempo de subida (rise time) da tensão coletor-emissor VCE durante o bloqueio. 100A. 7. pois permite uma rápida descarga da capacitância de entrada do IGBT. etc. Porém. já que a maior perda de potência é devida à parcela de corrente de cauda. IC: 50A/div. 7. Ls = 100nH.4 . 7. Uma resistência de bloqueio RG(off). As perdas de comutação de bloqueio em um IGBT com comutação dissipativa. a presença de um pulso negativo de tensão gate-emissor VGE é importante durante o bloqueio para reduzir os efeitos de dvCE/dt que injetam correntes através do capacitor gate-coletor CGC no capacitor gate-emissor CGE. O valor da resistência em série com o gate normalmente é dimensionado conforme as correntes máximas que podem suportar os dispositivos do circuito de comando (transistores de sinal. Para operar o IGBT em alta freqüência (acima de 10kHz) num braço (halfbridge). é dimensionando adequadamente a resistência RG(off) em série com o gate. 7. testado em: 380V.b . permitindo o bloqueio do IGBT. é importante aplicar uma Fig. muitos dos fabricantes de IGBTs recomendam aplicar-se uma tensão de 15V e uma resistência RG(on) em série com o gate menor que 50Ω [11]. controlada por meio do gate e do tempo de descida da corrente de cauda (devido à parcela de corrente de coletor do mesmo transistor). O tempo de descida da corrente de coletor do IGBT compõem-se basicamente do tempo de descida da corrente de base do transistor bipolar pnp (circuito equivalente da Fig. quanto menor for este tempo. sua aplicação dependerá do tipo de topologia e dos efeitos que provoca (diC/dt. tensão gate-emissor e corrente de coletor. Um outro problema que pode provocar um elevado dvCE/dt no bloqueio é o fenômeno de latch-up . Módulo IRGTA090F06. VGE: 10V/div.1.15V). não mudam significativamente através do circuito de comando de gate variando a resistência RG(off).Em Estado Bloqueado Como já foi dito anteriormente.3 . apesar do tempo de retardo. no caso dos interruptores estarem em um braço de um conversor e atuando de modo complementar.Comutação no Bloqueio Durante a comutação de bloqueio os IGBTs. VGE: 10V/div. durante a comutação de bloqueio e estado bloqueado. IC: 50A/div. quanto maior for o valor desta resistência. VCE: 100V/div. maior será o tempo de retardo. 3.1. Na prática. . não apresentam tempos de estocagem como normalmente acontece com os transistores bipolares. Quando a tensão de saturação é bem baixa devida à aplicação de uma tensão elevada entre gate-emissor VGE. maiores serão os valores de dvCE/dt entre os terminais coletor-emissor do dispositivo. No IGBT não é necessário um sinal de tensão negativo entre os terminais gate-emissor VGE. A corrente de cauda é provocada pela recombinação de portadores minoritários no transistor pnp do circuito equivalente. Ls = 100nH. 2. Uma das maneiras de reduzir os efeitos devido às elevadas derivadas de tensão. portas lógicas. tensão gate-emissor e corrente de coletor.b para dois valores de resistências diferentes. Este picos de tensão podem provocar uma condução indevida do dispositivo complementar. 100A. VCE: 100V/div. Portanto. a magnitude da corrente de cauda é maior. A presença da resistência de bloqueio de gate RG(off) durante a comutação de bloqueio. este fenômeno é ilustrado na Fig. VCE IC 0 V GE R G(off) = 0 Ω VGE(off) = -15V Fig. testado em: 380V. é suficiente manter conectado o terminal de gate ao terminal de emissor através de uma resistência de bloqueio RG(off) de baixo valor. 2. tem uma influência direta sobre o tempo de retardo do bloqueio do IGBT.Formas de onda de: tensão coletor-emissor. dvCE/dt) sobre os dispositivos.a e Fig.a . entre gate-emissor é suficiente para proporcionar um caminho de descarga da capacitância gateemissor. VCE IC 0 V GE R G(off) = 33 Ω VGE(off) = -15V A tensão negativa de gate durante o bloqueio reduz o tempo de retardo de bloqueio. existe uma dependência entre estes dois parâmetros. de baixo valor. corrente que flui pelo canal MOS). Como pode-se observar. Módulo IRGTA090F06.

Outra vantagem de sua aplicação. técnicas convenientes de desmagnetização do núcleo devem ser utilizadas. bem como problemas devido à elevados dvCE/dt (estes problemas estão sendo superados com as últimas gerações de optoacopladores). destruindo os IGBTs. Para realizar o isolamento podem ser utilizados transformadores de pulso. • Capacidade de transferência de energia para dispensar o uso de fonte auxiliar no lado secundário. Para obter características de operação favoráveis. complexidade. sem apresentar problemas de saturação como no caso do transformador de pulso. • Dimensionamento adequado do núcleo e número de espiras do primário e secundário. onde a razão cíclica dos pulsos pode variar de ∼0 a ∼100%. porém. Quando não é utilizado isolamento existe o perigo de destruição do circuito de controle devido ao potencial de tensão de coletor do IGBT por destruição de algum dispositivo do circuito de comando conectado ao coletor do IGBT (caso de circuitos com proteção de curtocircuito por detecção de dessaturação). os mesmos limitam-se a. Para que o transformador apresente um desempenho adequado no circuito de comando. não se faz necessário utilizar uma fonte de tensão isolada no lado do secundário. 6) os sinais espúrios de tensão gate-emissor podem provocar um curto-circuito de braço.Transformadores de Pulso O transformador de pulso é um dispositivo magnético do circuito de comando de gate que opera em elevada freqüência e que proporciona isolamento galvânico entre os circuitos de potência e circuito de controle. para estes interruptores pode não ser necessário utilizar circuitos de comando de gate isolados.5. os IGBTs inferiores têm os emissores conectados a um ponto comum considerado normalmente como nó de referência. Quando é aplicado um transformador de pulso em um circuito de comando. optoacopladores e circuitos de comando de gate integrados dedicados. sem restrições quanto aos níveis da tensão e potência do conversor. apresentam pouca imunidade a interferências por ruídos. O projeto do circuito de comando de gate isolado deve levar em consideração o custo. circuitos para amplificar a corrente de saída (que é da ordem de 20mA). é a imunidade à interferências por ruído.2 . ao primário não devem ser aplicados pulsos com razão cíclica acima de 50% por motivo de saturação do núcleo. Para conseguir a transmissão de pulsos com razão cíclica acima de 50%. Alguns detalhes devem ser observados para otimizar o uso de optoacopladores: • Devem apresentar imunidade à ruídos e derivadas de tensão. normalmente costuma-se utilizar uma resistência única para ambos os estados de operação do dispositivo. Segundo [10] é recomendado aplicar-se uma tensão negativa de 5V e uma resistência RG(off) série de gate de bloqueio menor que 47Ω. é possível aplicar-se uma tensão negativa na faixa de 5V a 15V. . Convém lembrar que durante a operação do dispositivo. ainda. imunidade a ruídos. Também existem critérios de utilização de resistências com valores diferentes. • Limitação da variação da razão cíclica prevenindo a saturação do núcleo (desmagnetização do núcleo).2. No caso de um conversor em meia ponte (Fig. 2.. Possuem a vantagem de transmitir pulsos com freqüência variável e com qualquer razão cíclica. operar favoravelmente em freqüências de comutação elevadas (acima de 100kHz). recomenda-se utilizar circuitos de comando de gate isolados para todos os interruptores de potência. onde o potencial de tensão relativo é nulo.1 . Por este motivo. podendo. no máximo. ou combinação em paralelo de ambas utilizando diodos de sinal em série. O valor do pulso negativo pode ser maior que 5V. rapidez de resposta. o que torna necessário utilizar circuitos de comando de gate isolados. Em algumas aplicações. devem ser levados em consideração os seguintes tópicos: • Tensão de isolamento do transformador (> 4kV). etc. não apresentando também. têm seus emissores conectados a diferentes potenciais de tensão em relação ao potencial de referência. podem acontecer transitórios destrutivos de tensão entre os terminais gate-emissor. Em relação à freqüência de operação. Neste método. Os IGBTs superiores. • As capacitâncias entre a entrada e a saída devem ser pequenas. com o emprego de um enrolamento primário e um ou mais enrolamentos secundários. Toda escolha depende do critério do projetista do circuito de comando. Este dispositivo pode transmitir pulsos de tensão do primário para o secundário sem distorção e com atrasos quase desprezíveis. para evitar que sinais espúrios de tensão positiva provoquem a entrada em condução indevida. Para proteger o dispositivo de tais condições indesejáveis. 100 kHz. problemas por elevados valores de dvCE/dt.Optoacopladores Os optoacopladores são dispositivos do circuito de comando de gate que proporcionam isolamento elétrico entre os circuitos de controle e potência.2 – NECESSIDADE DE CIRCUITOS DE COMANDO ISOLADOS Em circuitos de potência em ponte. devem ser utilizados diodos zener diretamente conectados entre os terminais gate-emissor. • Os sensores de sinal devem ser fotodiodos (os fototransistores são lentos). portanto. • Mínima indutância de dispersão. Normalmente quando é aplicado o método comum de transmissão de pulsos. 2. em conversores com circuitos de controle complexos e com circuitos de proteção.2. sendo uma para cada estado de operação. apresentam desvantagens quando comparados a estes: necessitam uma fonte auxiliar isolada na sua saída. • Freqüência de operação. a razão cíclica dos pulsos podem variar desde valores próximos a zero até 0.tensão negativa durante todo o intervalo de tempo que se quer manter o IGBT bloqueado. Porém. 2. tanto para o pulso positivo como para o pulso negativo.

Tiristor para simular curto-circuito R3 C3 C G E IRGPH40F SCR R1 D1 100V C2 D2 R2 E2 C1 Fig. Um circuito de comando de gate (isolado ou não) é considerado adequado para acionar um IGBT. TJ = 150oC.20V.2. O IGBT do conversor da Fig. o pulso da tensão de saída não sofre distorção em relação ao pulso da tensão de entrada.Circuito em meia ponte para teste dos circuitos de comando de gate. 8 . C1 G1 E1 C2 G2 E2 D1 R1=10Ω C1 100V R2 C2 C3 MÓDULO : CM15TF . VCEsat = 2. 2. TJ = 150oC.20V. Dois circuitos não realizam proteção de curto-circuito do IGBT mas outros dois circuitos realizam proteção de curto-circuito do IGBT por detecção de dessaturação através da tensão coletor-emissor VCE. Fuji. porém.• Aplicar aproximadamente a corrente nominal na entrada para a polarização do fotodiodo.Circuitos de Comando Integrados Dedicados Atualmente muitos fabricantes de IGBTs tem desenvolvido circuitos de comando de gate integrados dedicados para seus dispositivos. ICM = 30A @ TJ = 25oC. é capaz de aplicar níveis adequados de tensão gate-emissor e corrente de gate.3 .12E Fig.Circuito a IGBT para teste dos circuitos de comando de gate. • Optar por dispositivos com elevada tensão de isolamento entre a entrada e a saída (> 4kV). O tiristor neste circuito é utilizado para simular um curto-circuito na carga. Mais adiante serão mostrados alguns deles. distância das trilhas de circuito impresso. VGE = +/. 8 foi utilizado para testar os circuitos de comando para um único transistor. o módulo IGBT em meia ponte do conversor da Fig. 9 . para manter quase inalterado o valor da razão cíclica. os circuitos sem isolamento utilizam a técnica do Bootstrap (circuitos da International Rectifier) que normalmente são utilizados em conversores de baixa potência (< 2kW ) e baixa tensão (< 600V). Semikron. 9. Existem circuitos com isolamento e sem isolamento. ICM = 58A. etc. o circuito de potência em meia ponte da Fig.7V @ IC = 15A. as magnitudes de tais atrasos devem ser aproximadamente iguais {td(on) ≅ td(off) }. 8 apresenta as seguintes especificações: VCE = 1200V. ICN = 17A @ TC = 100oC. VGE = +/. 2. VCEsat = 3V @ IC = 17A. etc. 9 apresenta as seguintes especificações: VCE = 600V. Os pulsos de tensão podem apresentar atrasos na subida e na descida como é mostrado na Fig. 10.3. quando têm as seguintes características: mantêm aproximadamente igual a razão cíclica do pulso da tensão de entrada ao circuito Vcon no pulso da tensão positiva na saída do circuito VGE. . foi utilizado para testar os circuitos de comando integrados para um braço de interruptores. Alguns circuitos ainda podem apresentar proteção contra curto-circuito. Alguns destes circuitos necessitam de uma fonte de tensão isolada na saída.) e. Por outro lado. Por outro lado. ICN = 15A @ TJ = 25oC.1 – Circuitos de comando isolados por transformador de pulso Estes circuitos são capazes de aplicar pulsos de tensão gate-emissor positivos de 15V e negativos de 5V.3 – EXEMPLOS DE CIRCUITOS DE COMANDO ISOLADOS O circuito de potência (chopper) mostrado na Fig. 2. Os circuitos com isolamento utilizam fotosensores de sinal ou transformadores de pulso para transmitir os pulsos da entrada para a saída (circuitos de comando da Mitsubishi. como por exemplo: capacitores de desacoplamento. • Levar em consideração possíveis recomendações adicionais do fabricante indicadas no catálogo.

não é mostrada a curva de carga para a tensão negativa gate-emissor. 2. VGE(off) : tensão negativa gate-emissor. ♦ CIRCUITO A1 : Vcc1 R1 vcon 15V Z1 Tr D1 R5 R6 Z5 R7 IGpk G V GE C1 t vcon R3 R2 Z2 R4 Q1 Q2 Z3 D3 C2 D2 Z4 E A seguir é dada uma metodologia para determinar algumas grandezas importantes para o dimensionamento do circuito de comando. energia necessária para garantir a polarização do IGBT. que é limitada pela resistência de gate.v con 50% 50% 50% 50% 0 50% 0 v GE t t t d(on) t d(off) Fig. Estas grandezas podem ser obtidas a partir da característica de carga de gate mostrada no catálogo do dispositivo (IGBT). A corrente de pico (Igpk) fornecida pelo circuito de comando para carregar a capacitância de entrada (Cies) do IGBT durante a entrada em condução. ∆Q ≅ [50 . pode ser determinada através da seguinte equação: (2) E IGBT ( on ) = ∆Q ⋅ ∆V Onde: ∆Q : Variação de carga da capacitância de entrada [Cies]. etc.Circuito de comando de gate isolado com transformador de pulso e sem proteção de curto-circuito para 0 < D ≤ 0. Para ter maiores detalhes ver a literatura [12]. que é dissipada no resistor de gate (R6). No circuito de comando da Fig. pode ser calculada de maneira aproximada utilizando-se a seguinte equação: I Gpk ≅ VGE (on ) − VGE ( off ) RG Fig.2 µJ A potência da fonte de tensão do circuito de comando absorvida pelo IGBT durante a entrada em condução. I Gpk ≅ 15 − ( −5) = 0. Para solucionar esta situação foi realizada uma interpolação aproximada e determinada a carga para tensão negativa. a resistência R6 é a resistência de gate (RG). tais como: corrente de pico de gate para entrada em condução do IGBT. (1) Onde: VGE(on) : tensão positiva gate-emissor. Tomando os seguintes valores de tensões de gate-emissor e a resistência de gate: VGE(on) = 15V VGE(off) = -5V RG = R6 = 27Ω e substituindo na Eq. ∆V : Variação da tensão gate-emissor [V]. 11 . [11]. 1. Da característica de carga de gate mostrada no catálogo foram obtidos os seguintes dados. tem-se o valor da corrente de pico.(-10)] = 60 ηC ∆V ≅ [15-(-5)] = 20 V É importante esclarecer que na figura de característica de carga de gate deste dispositivo. 10 . a energia é igual a: EIGBT(on) = 1. que é necessária para o cálculo da energia. No circuito da Fig. pode ser determinada com a seguinte equação: (3) PIGBT(on) = E IGBT(on ) ⋅ f S .Pulsos de tensão de entrada e de saída de um circuito de comando. 11. 8 utilizou-se o IGBT da International Rectifier ( IRGPH40F ) como dispositivo de teste. RG : resistência de gate.74A 27 A energia absorvida pelo IGBT do circuito de comando para a entrada em condução. Substituindo os valores obtidos da curva na Eq.5.

que é aproximadamente a mesma corrente que circula através do coletor do transistor Q1. • Resistor R6: é o resistor de gate (RG) que é utilizado para controlar dic/dt e dvCE/dt sobre o IGBT. O valor de sua capacitância pode ser escolhida entre 3. EIGBT(on) = EIGBT(off). o transistor é bloqueado e quando o diodo é bloqueado. podem ser determinadas com simplicidade. para evitar problemas de curto-circuito. é dissipada no resistor de gate sem considerar as perdas devido aos outros componentes do circuito de comando. • Capacitor C1: é um capacitor cerâmico que permite uma rápida entrada em condução e bloqueio do transistor Q1. Na prática pode-se utilizar a eq. O excesso de corrente de base neste transistor faz com que ele fique muito saturado aumentando o tempo de estocagem. O valor pode ser escolhido de 1kΩ a 2kΩ. quando a relação de transformação do transformador de pulso é unitária. O valor de sua resistência deve ser escolhido analisando os esforços de tensão e da corrente do IGBT. O valor desta resistência pode ser escolhida de 470Ω a 2kΩ. R3 ≅ Vcon 0.Onde: fS : Freqüência de comutação do IGBT Para as freqüências de comutação de 10kHz e 50kHz as potências são iguais a 12mW e 60mW. A operação do transistor é como segue: quando o diodo conduz. • Resistor R3: limita a corrente de base do transistor de sinal Q1. • Resistor R7: permite a descarga da capacitância gate-emissor CGE do IGBT. sua aplicação é recomendada principalmente quando o circuito de comando for utilizado em um braço. 8. Por outro lado. A energia necessária para bloquear o IGBT (energia para descarregar a capacitância de entrada) é igual à energia necessária para a entrada em condução (energia para carregar a capacitância de entrada). a tensão gate-emissor pode superar o valor de limiar permitindo a entrada em condução do IGBT. • Resistor R1: é utilizado para limitar a corrente de curto-circuito da fonte de tensão VCC1 no caso de eventual destruição do transistor Q1. quando na ausência do sinal de comando e/ou destruição do transistor Q2 é aplicada abruptamente uma tensão entre coletor-emissor VCE. que opera na região de saturação. Este capacitor comporta-se como uma fonte de tensão negativa durante todo o bloqueio do dispositivo (IGBT). 8 foi escolhido uma resistência de gate de 27Ω para o estado de condução. limita a corrente através dos dispositivos do circuito de comando de gate. • Diodos D2 e D3: são diodos de sinal colocados em série com as resistências R5 e R7 para evitar perdas e descarga da energia do capacitor C2 durante o estado bloqueado do IGBT. A seguir são explicados alguns detalhes para dimensionar os componentes do circuito da Fig.03 ⋅ I Gpk (6) • Resistor R4 : limita a corrente de base do transistor de sinal Q2. tornando lento o seu bloqueio. O valor pode ser escolhido entre 1kΩ a 2kΩ. A tensão sobre ele é grampeada no valor da tensão de operação do zener Z3. a potência fornecida ao IGBT pela fonte de tensão (VCC1) do circuito de comando. Os diodos zener conectados entre gate e emissor. Para o circuito da Fig. que é a mesma utilizada para o estado de bloqueio [RG(on) = RG(off)]. • Capacitor C2: é um capacitor eletrolítico que armazena energia durante a transmissão do pulso de tensão através do transformador de pulso. Por exemplo. • Resistor R5: o valor de sua resistência pode ser determinada com o conhecimento da corrente de polarização do zener Z3 e a energia no capacitor C2 . deve ser escolhido um capacitor com capacitância maior que 10µF / 25V. nos resistores são conhecidos os valores das resistências e as tensões sobre eles e nos diodos zener as correntes de polarização e suas tensões de operação indicadas no catálogo. 7. • Diodo D1: é um diodo de sinal utilizado simplesmente para polarizar o transistor de sinal Q2. é determinada pela seguinte equação: (4) PVcc1 = 2 ⋅ E IGBT( on ) ⋅ f S As perdas provocadas pelos outros componentes do circuito de comando. • Resistor R2 : é utilizado para desmagnetizar a indutância de dispersão do transformador de pulso e amortecer oscilações. O valor de sua resistência pode ser determinada com o conhecimento da corrente do secundário do transformador após o IGBT ter entrado em condução e que circula através do paralelo das resistências de R6 + R7 com R4.6 para o dimensionamento aproximado de R3. Portanto. O valor não deve ser elevado. Na prática recomenda-se escolher de 10Ω a 27Ω. pode provocar limitação do pulso de corrente de gate durante a entrada em condução do IGBT. como conseqüência. Este capacitor não deve provocar uma distorção do sinal de comando gerado pelo circuito de controle.3nF para uma freqüência de comutação de 10kHz a 680pF para uma freqüência de comutação de 50kHz. O valor de sua capacitância pode ser determinada utilizando-se a seguinte equação: C2 > 2 ⋅ E IGBT( on ) VZ3 2 (5) Para evitar sua descarga pela presença de outros dispositivos no circuito de comando e garantir o bloqueio do IGBT. conforme este critério deve ser escolhido o seu valor. Por este motivo. o transistor conduz. pois. O súbito crescimento da tensão provoca uma derivada que induz uma corrente na capacitância gate-emissor CGE através da capacitância coletor-gate e. Sua energia deve ser suficiente para garantir a descarga da capacitância de entrada do IGBT. portanto. Em um período de comutação. somente protegem o gate para tensões gate- . Ele deve ser dimensionado para permitir a operação do transistor na região de saturação.

12 (d) são mostradas as formas de onda da tensão coletor-emissor VCE e da corrente de coletor IC. • Transformador de pulso Tr: o transformador pode ser projetado utilizando-se as equações dadas a seguir [13]: i ef ≅ I Gpk ⋅ Ae ⋅ Aw ≅ Np ≅ Sf ≅ D max [A] 3 Vcc1 ⋅ D max ⋅ i ef ⋅ 10 4 [cm4] K p ⋅ K w ⋅ J ⋅ ∆B ⋅ f s (7) (8) (9) (10) D max ⋅ Vcc1 ⋅ 10 4 [espiras] A e ⋅ ∆B ⋅ f s i ef J [cm2] Onde: Ae : Área da seção transversal do núcleo [cm2]. Dmax : Razão cíclica máxima. foi reduzido o valor da capacitância do capacitor C1. ♦ CIRCUITO A2 : O circuito da Fig. Por outro lado. cujo interruptor IGBT foi acionado com o circuito de comando de gate da Fig. Aw : Área da janela do núcleo [cm2]. para pulsos de tensão positivos e negativos. • Zener Z4 e Z5: são utilizados para evitar a destruição do IGBT pela presença de sobretensões entre gate e emissor.1. 8.5 e 0. devido à sobrecarga ou curto-circuito. Sf : Seção do fio [cm2]. ∆B : Excursão do fluxo magnético [T]. o zener Z2 pode ser dimensionado com valor de tensão igual à tensão do secundário do transformador de pulso. mostram os detalhes da comutação do interruptor do conversor da Fig. Os transformadores dos circuitos de comando foram dimensionados para operar em uma freqüência de comutação (fs) de 10kHz. 12 foi utilizado o circuito de potência da Fig. Kp : Fator de utilização do primário. Este zener pode ser dimensionado com uma tensão de operação de 1. é recomendado desenvolver o circuito de potência com um ótimo layout.emissor acima de seu valor de operação. 13 possui uma proteção de sobrecorrente. • Transistores Q1 e Q2: devem ser dimensionados com o prévio conhecimento da corrente de pico de coletor e máxima tensão coletor-emissor. também pode ser substituído por um diodo de sinal rápido. NP : Número de espiras do primário. 12 (b) o sinal de saída (VGE) tem um atraso na subida de 100ns e um atraso na descida de 400ns. 12 (c) são mostradas as formas de onda dos pulsos da tensão gate-emissor VGE e da corrente de gate IG. baseada na . Na Fig. Como pode-se perceber. na Fig. Embora não se tenha efetuado. Para a aquisição das formas de onda mostradas na Fig. As formas de onda das Figs. 11. 12 (e) e (f). Em relação ao sinal de entrada (Vcon). Observando a última figura. deve-se também reduzir o número de espiras do primário e do secundário do transformador de pulso e o núcleo do transformador de pulso. fs : Freqüência de comutação [Hz]. Os valores de tensão de operação devem ser menores que a tensão de destruição gate-emissor indicados pelos fabricantes ( ±20V). • Zener Z1 e Z2: são utilizados para desmagnetizar o transformador de pulso. J : Densidade de corrente [A/cm2]. Os testes do circuito de comando foram realizados com estes níveis de tensão e de corrente. 11. Por outro lado. Este problema pode ser superado utilizando-se um transistor MOSFET de sinal. maior poderá ser a razão cíclica do pulso de tensão. Na Fig. 12 (a) e (b) são mostradas as formas de onda dos sinais da tensão de entrada do circuito de comando (Vcon) e da tensão de saída gate-emissor (VGE) para as razões cíclicas 0. O zener Z1 limita a tensão coletoremissor reversa do transistor Q1 em seu valor de operação (quando a relação de transformação é unitária). o IGBT entra em condução sob condições de corrente nula devido às características indutivas da carga e bloqueia sob condições de tensão e corrente não nulas. por causa da demora (tempo de estocagem) no bloqueio do transistor bipolar Q1 do circuito de comando (Fig.5 vezes a tensão no secundário do transformador de pulso. ief : Corrente eficaz no primário do transformador [A]. durante a carga e a descarga da capacitância de entrada do IGBT. Para operar o circuito em freqüências na ordem de 25kHz. 12 (a) o sinal de saída (VGE) apresenta um atraso na subida de 100ns e um atraso na descida de 200ns. Todas as aquisições foram efetuadas para uma freqüência de operação do interruptor igual a 25kHz. Por este motivo. na Fig. Os atrasos na descida são maiores em relação à subida e aumentam com a diminuição da razão cíclica. Nota: estas equações são válidas para um núcleo de ferrite do tipo EE. Quanto maior a tensão de operação de Z1. O zener Z2. Nas Figs. a derivada da corrente de coletor provoca uma sobretensão sobre o IGBT devido à presença de indutâncias parasitas no circuito de potência. Kw : Fator de utilização da janela. 11).

] (f) VCE [20V/div. observando-se VCE pode-se detectar a existência de sobrecorrente. 14 . A seguir são descritos os componentes que foram introduzidos para a proteção de sobrecorrente. 500ns/div. aumenta também a tensão VCE.. que inicialmente encontra-se com tensão coletor-emissor VCE igual ou maior que o valor da fonte de tensão do circuito de potência.10µs/div. 5µs/div.Formas de onda obtidas com os circuitos das Figs. Para este nível de corrente. 500ns/div. V GE Vcon V con V GE (a) Vcon e VGE [5V/div. O valor de C3 é determinado considerando a corrente de coletor do transistor Q2 igual à corrente de pico de gate IGpk e de valor constante durante a comutação. o capacitor C3 carrega-se com corrente aproximadamente constante. se ocorrer um aumento da corrente de coletor. . 14.8 V : Tensão de operação do zener Z6. O IGBT....] IC [2A/div.10µs/div. Portanto.] V CE IC (d) VCE [20V/div. é aproximadamente igual a: (11) v C3 (0) ≅ VZ6 + VD3 onde: VZ6 = 6. A tensão inicial sobre o capacitor C3. 500ns/div.. observando a curva de característica de saída de transistor Q2 (catálogo) é determinada a corrente de base IBQ2. com estas considerações. para uma determinada tensão de gate. I BQ2 C3 vC3 Fig.] Fig.Circuito equivalente durante a carga do capacitor C3 que ocorre na entrada em condução do IGBT.. que também é aproximadamente constante.] (b) Vcon e VGE [5V/div. 5µs/div. antes da entrada em condução do IGBT. Sabe-se que. 13 .] IC [2A/div.] iG [200mA/div. devido a sobrecargas ou curtos-circuitos.] IC [2A/div. Vcc1 R1 Tr vcon 15V R5 Z1 Q2 Z2 R4 Q1 D2 D1 R6 R8 R7 Q3 D4 Z3 C2 C3 Z6 D3 C G R9 Z5 D5 Z4 E VGE R2 C1 t vcon R3 • Capacitor C3 : permite a polarização do transistor bipolar Q2 para que o sinal de comando transmitido pelo transformador de pulso chegue ao gate do IGBT. deve alcançar a tensão coletor-emissor de saturação VCEsat antes que a tensão sobre o capacitor C3 alcance o valor de VGE(on) . 5µs/div. Deste modo.observação da tensão entre coletor e emissor.5.] V CE IC (e) VCE [20V/div... O circuito equivalente é mostrado na Fig.] VGE V CE IC IG (c) VGE [10V/div. 12 .. R6 Fig. 5µs/div. 500ns/div.Circuito de comando de gate isolado com transformador de pulso e com proteção de curto-circuito para 0 < D ≤ 0.. 8 e 12.

das curvas de característica de saída do transistor Q2 (2N2907) a corrente de base é aproximadamente igual a : IBQ2(curto) = 2. este transistor é bloqueado inibindo o sinal de comando de gate. 15 (c) são mostradas as formas de onda da tensão gate-emissor (VGE) e da corrente de coletor durante o teste de curto-circuito do IGBT. o IGBT poderá suportar correntes superiores a 6 vezes a corrente nominal até atuar a proteção. (IGpk ≅ 0). o tempo de bloqueio. Também evita a descarga do capacitor C3. os atrasos na descida são maiores em relação à subida e aumentam com a diminuição da razão cíclica e isto ocorre por causa da demora do bloqueio do transistor bipolar Q1. dentro de uma faixa de variação não muito elevada. na Fig. a corrente de base IBQ2 é aproximadamente igual a 20 mA. Substituindo valores na Eq. ♦ CIRCUITO A3 : Os circuitos das Figs. A corrente de base que carrega o capacitor C3 depende da corrente de coletor. Este diodo deve ser ultra-rápido e com tensão reversa de operação maior que a máxima tensão coletor-emissor do IGBT. Portanto. o sinal de comando é inibido e como conseqüência o IGBT é bloqueado novamente. A tensão sobre o capacitor C3 começa a crescer desde o valor inicial VC3(0) devido à corrente de base do transistor Q2. 13. 15 (d) são mostradas as formas de onda da tensão coletor-emissor VCE e da corrente de coletor durante o teste de curto-circuito do IGBT. que é de 10µs. Por outro lado. Nas Figs. 15 (b). R7 e R9. Com esta consideração. 16 e 18 permitem operar os interruptores de potência com razão cíclica e freqüência variáveis. Para obter as aquisições das formas de onda mostradas na Fig. após ocorrido o curto-circuito. e seu valor é igual a ICQ2 = 35 mA.VD3 = 0. A corrente de base é determinada a partir das curvas de característica de saída do transistor Q2 (catálogo) como uma função da corrente de coletor no instante do curto-circuito. Por outro lado.5 mA.5 e 0. No caso da ocorrência desta situação o valor da capacitância deve ser aumentado experimentalmente. Observa-se na figura que o circuito de comando garante a proteção em aproximadamente 5µs após detectada a falha. 12. cujo interruptor IGBT foi acionado com o circuito de comando de gate da Fig. o resistor R9 entre gate-emissor é ajustado para um baixo valor. 8. Do mesmo modo que no caso anterior. gate-emissor VGE. é aproximadamente igual a: t blo ≅ 5. o valor da capacitância é igual a: C 3 ≅ 1. Logo. 14. substituindo os valores na Eq. obtida a partir de Eq. menor que 100mA. O tempo que demora para atuar a proteção pode ser estimado com a seguinte equação: t blo = C 3 ⋅ VGE (on ) − v C3 (0) I BQ 2( curto ) [ ] (14) A corrente de coletor (ICQ2) durante o curto-circuito é igual à corrente que flui pelos resistores R4. Todas as aquisições foram obtidas para uma freqüência de operação do interruptor de 25kHz. a tensão coletor-emissor (VCE) deve cair do valor máximo ao valor de saturação VCEsat antes que C3 possa carregar completamente. o sinal de saída VGE tem um atraso na subida de 125ns e um atraso na descida de 430ns. O tempo de duração do curto-circuito está abaixo do valor permitido. 13. Utilizando a Eq. para diminuir o tempo de bloqueio. pode ser determinado o valor de C3: C3 ≅ I BQ2 ⋅ t com [0. . Sua corrente média é muito pequena. D1 e IGBT1 da Fig. Estes circuitos normalmente são aplicados em conversores com modulação PWM senoidal [14]. • Diodo D3 : detecta a dessaturação da tensão coletor-emissor do IGBT. para as razões cíclicas 0.8 ηF Quando ocorre o curto-circuito de carga em estado de condução do IGBT. Ressalta-se que ocorre uma sobretensão no bloqueio do IGBT devido à elevada derivada de corrente sobre indutâncias parasitas da malha formada por C2.8VGE(on) para um tempo de duração do pulso de corrente de gate (tcom) de 400ns e substituindo na Eq. • Zener Z6: Permite detectar o curto-circuito com baixos valores da tensão coletor-emissor (VCE). Uma vez conhecida a corrente de coletor. Na Fig. obtém-se o valor da capacitância C3.8 ⋅ VGE(on ) ] − v C3 (0) (13) Das curvas de característica de saída do transistor Q2 (2N2907) para a corrente de coletor ICQ2 = Igpk. Quando a tensão coletor-emissor não atinge o valor de saturação durante este tempo previsto. na Fig. 8. 12. Em relação ao sinal de entrada Vcon. na Fig. A variação linear de tensão sobre o capacitor é dada pela seguinte equação: v C 3 ( t ) = v C 3 (0 ) + ( 1 ⋅ I BQ 2 ) ⋅ t C3 (12) Considerando a tensão final sobre o capacitor C3 de 0.7 V : Queda de tensão sobre o diodo D3 durante a condução. 13. pois este tempo será inferior a 10µs. 15 (a) o sinal de saída (VGE) apresenta um atraso na subida de 125ns e um atraso na descida de 225ns.4 µs Ou seja. 15 foi utilizado o circuito de potência da Fig. Quando a tensão sobre ele atinge o valor do potencial da base do transistor Q2. a tensão coletor emissor VCE cresce e o diodo D3 é bloqueado. 15 (a) e (b) são mostradas as formas de onda dos sinais da tensão de entrada do circuito de comando Vcon e da tensão de saída.1.

Circuito de comando de gate isolado com transformador de pulso e sem proteção de Curto-circuito para 0 < D < 1. 10µs/div. Q1 e Q2 : são utilizados para polarizar os transistores de sinal Q3 e Q4. 8 e 16. 8 e 12. Para a aquisição das formas de onda mostradas na Fig. Seu valor deve ser maior ou igual a 5..] (d) VCE [50V/div. Se o nível de tensão dos pulsos do circuito de controle (vcon) for maior ou igual ao valor de VCC1. . R2.].5µs/div.5µs/div. V GE V con Nas Figs.. 16. • Capacitores C2 e C3: permitem uma corrente média nula nos enrolamentos primário e secundário para evitar a saturação do transformador de pulso.6nF..VGE VGE V con Vcon (a) Vcon e VGE [5Vdiv. 5µs/div. 10µs/div.. 17 foi utilizado o circuito de potência da Fig. Os valores das capacitâncias podem ser obtidos realizando a medição da indutância magnetizante do transformador e considerando a freqüência de ressonância (fr ) igual a 1/10 da freqüência de comutação (fs). 10µs/div.] Fig. onde o interruptor IGBT foi acionado com o circuito de comando de gate da Fig. 17 (a) e (b) são mostradas as formas de onda dos sinais da tensão de entrada do circuito de comando Vcon e (a)Vcon e VGE [5V/div.. 10µs/div.. 17 .] Fig.] (b)Vcon e VGE [5V/div. N2 : Número de espiras do secundário do transformador. C5. fs : Freqüência de comutação do IGBT. 15 . • Capacitor C5 : permite um rápido bloqueio do transistor de sinal Q2 evitando o atraso na subida do sinal de comando.5µs/div. IC [50A/div.] IC [50A/div. Vcc1 Q3 C2 Q2 Q1 C1 Q4 Tr D1 R4 Q5 C3 D2 R5 D3 C4 Z1 R6 R7 D4 Z2 Z3 VGE E G vcon 15V t R1 R3 vcon R2 C5 • Transformador de Pulso Tr : deve ser projetado de maneira similar ao do circuito da Fig.. V GE V con Fig. 16 .Formas de onda obtidas com os circuitos das Figs.] b) Vcon e VGE [5Vdiv. A seguir são dadas as equações para determinar os valores de suas capacitâncias: C2 ≥ 1 Lm  10 ⋅ 2⋅π⋅f s  2     2 (15)  N1  C3 =  (16) N   ⋅C2  2 onde: Lm : Indutância magnetizante do primário do transformador. 8. • Dispositivos R1.Formas de onda obtidas com os circuitos das Figs. estes dispositivos não são necessários.. 11.] VGE V CE IC IC (c) VGE [10V/div. N1 : Número de espiras do primário do transformador.

No caso de não ser aumentado o valor da resistência de gate. em comparação com o atraso na descida. 16. Em relação ao sinal de entrada Vcon. Neste circuito. 19 (a). Observa-se que o circuito de comando de gate garante a proteção do IGBT em aproximadamente 5. por causa do bloqueio lento do transistor bipolar Q2 do circuito da Fig. 19 foi utilizado o circuito de potência da Fig. Estes circuitos permitem aplicar pulsos de tensão gate-emissor positivos de 15V e negativos de 7.da tensão de saída gate-emissor VGE para as razões cíclicas 0. 5µs/div.] V GE VCE IC IC (c) VGE [10V/div.1 – Circuitos de comando isolados por optoacoplador Nas Figs.] (b)Vcon e VGE[5V/div. 10µs/div. 18 possui característica de proteção de sobrecorrente.3. na Fig. O tempo de duração do curto-circuito é menor que o valor permitido. 17. 19 (d) são mostradas as formas de onda da tensão coletor-emissor (VCE) e da corrente de coletor durante a ocorrência do curto-circuito do IGBT. Por outro lado. o atraso na subida diminui quando diminui a razão cíclica. as diferenças dos tempos de atrasos ocorrem pelos mesmos motivos indicados no circuito da Fig.1. 18. O sinal de saída gate-emissor tem um atraso na subida maior. Todas as aquisições foram efetuadas para uma freqüência de operação do interruptor de 25kHz. 10µs/div. Vcon VGE Fig. 19 (a) e (b) são mostradas as formas de onda dos sinais da tensão de entrada do circuito de comando Vcon e da tensão de saída gate-emissor VGE para as razões cíclicas 0. 10µs/div.] Fig. A diferença entre os dois circuitos é proteção de curto-circuito por detecção de saturação da tensão coletor-emissor do . 19 (b). 8 e 18. além das características do circuito anteriormente apresentado na Fig.5µs/div.. VGE Vcon (a)Vcon e VGE [5V/div. na Fig. onde o interruptor IGBT foi acionado com o circuito de comando de gate da Fig. Por outro lado. devido a uma maior saturação do transistor Q4. Verifica-se que a rápida descida da corrente de curto-circuito provoca uma sobretensão entre o coletor e o emissor do IGBT.. 17 (a) o sinal de saída VGE apresenta um atraso na subida de 350ns e um atraso na descida de 170ns. 18 .1. o sinal de saída VGE tem um atraso na subida de 80ns e um atraso na descida de 170ns. ♦CIRCUITO A4 O circuito da Fig.] IC [50A/div.Formas de onda obtidas com os circuitos das Figs. Estes atrasos podem ser alterados modificando as correntes de base de Q3 e Q4 ou adicionandose circuitos de anti-saturação.. o sinal de saída VGE apresenta um atraso na subida de 380ns e um atraso na descida de 180ns. 17 (b) o sinal de saída VGE tem um atraso na subida de 80ns e um atraso na descida de 150ns. 8.5µs após detectada a falha. que é normalmente de 10µs no máximo. Para a aquisição das formas de onda mostradas na Fig. 20 e 22 são apresentados os circuitos de comando isolados por optoacoplador para acionar interruptores IGBTs.. na Fig.. 8. Esta conclusão é confirmada com os resultados dos valores dos atrasos para a razão cíclica 0. D1 e IGBT1 da Fig. Esta sobretensão em alguns casos pode provocar a destruição do dispositivo.. 19 .] IC [50A/div. Na Fig. 19 (c) são mostradas as formas de onda da tensão gate-emissor VGE e da corrente de coletor IC durante o teste de curto-circuito do IGBT. 16. 2. O capacitor C5 que cumpre a função de permitir um bloqueio rápido deste transistor tem menor energia quando aumenta a razão cíclica. A sobretensão é originada pelas indutâncias parasitas na malha formada por C2.1.Circuito de comando de gate isolado com transformador de pulso e com proteção de curto-circuito para 0 < D < 1. Em relação ao sinal de entrada. Vcc1 Q3 C2 Q2 Q4 Tr D1 R4 C3 Q6 Q5 R5 D3 D2 R6 D5 Z1 C6 R7 R8 R9 D6 Z2 E Z3 Z4 D4 C G VGE C4 vcon 15V t R1 R3 vcon C1 R2 C5 Q1 Nas Figs. projetado segundo a área de operação segura de bloqueio (RBSOA). Na Fig. 10µs/div.9 e 0.5V.9 e 0. Esta derivada de corrente de coletor pode ser diminuída aumentando o valor da resistência de gate.] (d) VCE [50V/div. Portanto. na Fig. a sobretensão pode ser limitada colocando-se um grampeador de tensão entre coletor e emissor.

com este circuito.5µs após detectada a falha. 23 (c) são mostradas as formas de onda da tensão gate-emissor VGE e da corrente de coletor durante o teste de curto-circuito do IGBT. Observa-se que o circuito de comando de gate garante a proteção do IGBT em aproximadamente 5.Circuito de comando de gate isolado com optoacoplador e sem proteção de curto-circuito. onde o interruptor IGBT foi acionado com o circuito de comando de gate da Fig. 20 . por outro lado. 21 (b) o sinal de saída VGE tem um atraso na subida de 425ns e um atraso na descida de 400ns. 23 foi utilizado o circuito de potência da Fig. o sinal de saída VGE apresenta um atraso na subida de 500ns e um atraso na descida de 450ns.9 e 0. sendo que em muitos casos.. D2 R7 R9 Z4 D3 C R5 R6 Q2 Q1 Q3 Q4 Q5 D1 R8 C6 R10 Z3 G VGE 1 2 8 CI1 7 6 HCPL2200 C3 R1 3 4 C5 D4 Z2 E 5 Z1 C2 Fig. Todas as aquisições foram feitas para uma freqüência de operação do interruptor de 25kHz. Para a aquisição das formas de onda mostradas na Fig. 22 . Na Fig. Observa-se que.9 e 0.5µs/div. Neste circuito os tempos de atraso na subida e na descida e em toda a faixa de variação da razão cíclica são aproximadamente iguais.. Em relação ao sinal de entrada.1.] Fig. 23 (a) e (b) são mostradas as formas de onda dos sinais de tensão de entrada do circuito de comando Vcon e da tensão de saída gate-emissor VGE para as razões cíclicas 0. 20. 21 (a). onde o interruptor IGBT foi acionado com o circuito de comando de gate da Fig. na Fig. Neste circuito as diferenças dos tempos de atraso na subida e na descida do sinal da tensão de saída. 8. na Fig. Em relação ao sinal de entrada. VGE V con Vcon VGE Nas Figs. na Fig.1. Na Fig. ♦CIRCUITO B2: Vcc1 C4 R2 R4 R3 C1 vcon 15V t (a) Vcon e VGE[5V/div. 8. 21 foi utilizado o circuito de potência da Fig. é possível obter-se uma ampla faixa de variação de freqüências dos pulsos de comando que só é limitada nas altas freqüências por estes atrasos acima citados. ♦CIRCUITO B1: Para a aquisição das formas de onda mostradas na Fig. o sinal de saída VGE apresenta um atraso na subida de 450ns e um atraso na descida de 400ns Por outro lado. 22. 23 (d) são mostradas as formas de onda da tensão coletor-emissor VCE e da corrente de coletor durante a ocorrência de curto-circuito do IGBT. . 23 (a). na Fig.5µs/div.] (b) Vcon e VGE[5V/div. 23 (b) o sinal de saída VGE tem um atraso na subida de 450ns e um atraso na descida de 425ns.IGBT realizada pelo circuito da Fig. Todos os dispositivos destes circuitos são dimensionados de acordo com as limitações de tensão e corrente do optoacoplador da Hewlett Packard (HCPL 2200) e exigências de corrente de gate para entrada em condução e bloqueio do IGBT. são aproximadamente iguais. Vcc1 C4 R2 R4 C3 Q1 R5 R6 Q2 Q3 Q4 R7 Z3 R8 D1 C5 Z2 E G VGE R3 C1 vcon 15V t 1 2 8 CI1 7 6 HCPL2200 R1 3 4 5 Z1 C2 Fig. Estes atrasos ainda poderiam ser diminuídos melhorando-se os tempos de bloqueio dos transistores Q2 a Q4. Nas Figs. 21 (a) e (b) são mostradas a formas de ondas dos sinais da tensão de entrada do circuito de comando Vcon e da tensão de saída gate-emissor VGE para as razões cíclicas 0. 22.Circuito de comando de gate isolado com optoacoplador e com proteção de curto-circuito. Todas as aquisições foram feitas para uma freqüência de operação do interruptor de 25kHz. 8 e 20. Nesta aquisição é mostrado o detalhe do efeito da descida da corrente de curtocircuito que provoca uma sobretensão entre coletor e emissor devido às indutâncias parasitas do circuito de potência. 21 . esta sobretensão pode ser destrutiva para o dispositivo.Formas de onda obtidas com os circuitos das Figs. para toda a faixa de variação de razão cíclica.

. Na aplicação do integrado no acionamento de IGBTs com diferentes potenciais de emissor. Todas as aquisições foram feitas para uma freqüência de operação do interruptor de 25kHz.5µs/div. Agora. 10µs/div. ♦CIRCUITO C1 : O circuito integrado (CI1) da Fig. 10µs/div. capazes de acionar três IGBTs com diferentes níveis de potencial de emissor. 2.] IC [50A/div.5V.. no caso de ter-se IGBTs com seus emissores conectados a um nó comum.. Uma outra característica do circuito é a seguinte: para limitar as correntes de polarização de entrada. É importante mencionar que os circuitos não realizam proteção alguma de curto-circuito do IGBT. pois possuem internamente seus resistores.Formas de onda obtidas com os circuitos das Figs. onde os interruptores IGBTs foram acionados com os circuitos de comando de gate da Fig.Vcon Vcon VGE VGE (a) Vcon e VGE[5V/div. 24 é um circuito da Powerex/Mitsubishi que contém internamente três circuitos de comando isolados por optoacopladores. na Fig. 8 e 22. 25 (a) e (b) são mostradas as formas de onda dos sinais da tensão de entrada do circuito de comando Vcon e da tensão de saída gate-emissor VGE para as razões cíclicas 0. 25 foram utilizados os circuitos de potência da Fig. 25 (a). independentes. Para a aquisição das formas de onda mostradas na Fig. o .3. 26. Estes circuitos permitem aplicar pulsos de tensão gate-emissor positivos de 15V e negativos de 7.3 – Circuitos de comando integrados Nas Figs.] (d) VCE [50V/div. 24 empregou-se somente dois dos três circuitos de comando isolados disponíveis no circuito integrado. os circuitos requerem uma fonte de tensão na entrada com valor não maior que 5V (VCC1) como mostra a figura.Três circuitos de comando de gate isolados independentes sem proteção de curto-circuito. é necessário somente uma fonte de tensão na saída para todos os circuitos de comando que acionam estes dispositivos.] IC [50A/div. Nas Figs. 24 . Em relação ao sinal de entrada. 10µs/div. Os sinais de comando utilizados possuem pulsos complementares com tempo morto ajustado através do circuito gerador de sinais e empregados nos interruptores do circuito da Fig. Para transmitir os pulsos de tensão da entrada para a saída. cada circuito de comando deve possuir uma fonte de tensão isolada na saída.5µs/div.1. não são necessários resistores externos.] (b) Vcon e VGE[5V/div. 24 e 26 são mostrados os circuitos de comando integrados com isolamento para acionar interruptores IGBTs.9 e 0.. No circuito da Fig.] VGE VCE IC IC (c) VGE [10V/div. 9. 10µs/div.] Fig.. 24. Vcc1 6 2 vcon1 15V t R3 7 C1 1 C2 5 R2 Vcc2 Z3 R4 Z2 G1 VGE1 E1 vcon1 R1 Q1 8 CI1 16 17 11 Z1 C3 12 vcon2 15V t R3 C2 R2 Vcc2 Z2 Z1 C3 z3 R4 C1 Q1 R1 G2 VGE2 E2 15 18 vcon2 M57919L 26 27 22 R3 C2 R2 Vcc2 Z3 R4 Z4 Z1 C3 G3 25 28 C1 21 Q1 R1 E3 Fig. 23 .. drenadas da fonte de 5V.

na Fig.5µs. onde os interruptores IGBTs foram acionados com o circuito de comando para braço da Fig. 26 . Na ocorrência de curto-circuito em qualquer interruptor do braço. 25. 27 (a). os circuitos integrados CI1 e CI3 detectam a dessaturação da tensão coletor-emissor VCE por meio do diodo conectado ao coletor D1 e inibem o sinal de comando de gate em aproximadamente 6. . 26 foi desenvolvido para acionar dois IGBTs em uma configuração meia ponte.Circuito de comando para braço utilizando dois circuitos integrados (CI1 e CI3) isolados com proteção de curto-circuito. o tempo de atraso na subida é de 650ns e na descida de 1. Neste circuito as diferenças dos tempos de atrasos na subida e na descida são pequenos (esta afirmação é válida para freqüências menores que 40 kHz) e estão dentro das especificações dadas no catálogo do componente (M57919L). Estes circuitos integrados não realizam ajuste do tempo morto dos sinais de comando . No circuito de comando da figura o circuito integrado CI1 aciona o interruptor superior e o circuito integrado CI3 aciona o interruptor inferior. 25 (b) o sinal de saída VGE tem um atraso na subida de 600ns e um atraso na descida de 550ns. Em relação ao sinal de entrada. 9 e 24.9 e 0. Para a aquisição das formas de onda mostradas na Fig. O excesso de corrente no fotodiodo faz com que o fototransistor fique excessivamente saturado aumentando o seu tempo de estocagem no bloqueio Nas Figs. 9. o tempo morto deve ser ajustado no circuito de controle. Os integrados também são capazes de gerar sinais de ocorrência de curto-circuito que podem ser transmitidos ao circuito de controle através de optoacopladores. 27 (b). ambos isolados por optoacoplador. o sinal de ocorrência de curto circuito é transmitido para o circuito de controle por meio dos optoacopladores CI2 e CI4. 26.sinal de saída VGE apresenta um atraso na subida de 650ns e um atraso na descida de 550ns. para as razões cíclicas 0. No circuito da Fig.que previne curto-circuito de braço. 26). liberam novamente o sinal de comando de gate e assim sucessivamente. os circuitos integrados CI1 e CI3 inibem os sinais de comando de gate por 1. Neste circuito. Neste caso. Como os integrados CI1 e CI3 apresentam um tempo de reset. desta maneira inibindo completamente os sinais de saída do circuito integrado.Formas de onda obtidas com os circuitos das Figs. Esta figura foi adquirida para explicar o ajuste da desigualdade dos tempos de atraso do sinal de tensão gate-emissor VGE em relação ao sinal de tensão de entrada Vcon na subida e na descida. Portanto. os circuitos de comando estão dados pelos circuitos integrados CI1 e CI3 da Powerex/Mitsubishi. 27 (b) e (c) são mostradas as formas de onda dos sinais da tensão de entrada do circuito de comando Vcon e da tensão de saída gateemissor VGE com os ajustes necessários.. o sinal de ocorrência permite a entrada em condução do tiristor de sinal SCR1 e coloca o pino 10 ( pino shutdown ) do circuito integrado CI-3524 (que no exemplo é utilizado para gerar os pulsos de comando) no potencial de tensão de VCC3. No caso de não serem inibidos os sinais gerados pelo CI-3524. Este valor de tempo é menor do que o tempo permitido para não destruir o IGBT.5µs/div. 26. Vcon Vcon VGE VGE (a) Vcon e VGE[5V/div.5µs/div.. Esta desigualdade foi diminuída colocando-se um resistor de 270Ω em série com o fotodiodo na entrada do CI1 e CI2 (resistor R6 do circuito da Fig.] (b) Vcon e VGE[5V/div. Todas as aquisições foram feitas para uma freqüência de operação do interruptor igual a 25kHz. ♦CIRCUITO C2 O circuito da Fig. são mostradas as formas de onda dos sinais da tensão de entrada Vcon e da tensão gate-emissor VGE. os optoacopladores CI2 e CI4 podem ser lentos. Vcc3 8 CI2 R9 Q3 Q2 R10 C4 R7 R8 7 6 5 1 2 3 R5 D1 C1 8 1 5 R3 6N136 Vcc3 Pino Shutdown R12 SCR1 P1 R11 t vcon1 15V C5 C1 Vcc1 R6 4 CI1 14 G1 Z4 4 13 Q1 C2 C3 R2 Z1 Z2 R4 Vcc2 VGE1 Z3 vcon1 R1 Vcc3 M57962L 6 E1 8 CI4 R9 Q3 Q2 C4 R7 5 R8 7 6 1 2 3 R5 D1 R10 C2 6N136 Vcc1 vcon2 15V t C1 R6 4 8 1 5 R3 CI3 14 4 13 Q1 C2 C3 R2 Z2 Z1 G2 Z4 R4 VGE2 Z3 vcon2 R1 M57962L 6 Vcc2 E2 . Neste circuito. 27 foi utilizado o circuito de potência da Fig.1.2µs.] Fig. na Fig.2ms após detectada a falha e. Por outro lado. Na Fig. logo após este intervalo de tempo. Fig.

] IC [50A/div. 10µs/div.] V CE IC (e) VCE [50V/div.1. na Fig. 29.5µs/div. Este circuito é isolado por meio de um optoacoplador interno composto de um diodo emissor de luz e um fotodetector integrado. na Fig.] Vcon VGE VGE IC (c) Vcon e VGE [5V/div.o sinal de saída VGE apresenta um atraso na subida de 700ns e um atraso na descida de 700ns. O circuito permite aplicar pulso de tensão gate-emissor positivo de 15V e negativo de 5. O circuito integrado TLP250 é recomendado para operar até freqüências de 25kHz pelo fato das diferenças dos tempos de atraso na subida e na descida.. 27 . Com a modificação introduzida. 5µs/div. as diferenças dos tempos de atrasos na subida e na descida para toda a faixa de variação de razão cíclica estão dentro das especificações indicadas no catálogo do componente (M57962L). . por outro lado. neste circuito.. na Fig. 28 . o sinal de saída VGE apresenta um atraso na subida de 400ns e um atraso na descida de 200ns.. inibindo os pulsos de gate antes da destruição do IGBT. 10µs/div.] IC [50A/div. R9 D6 D4 R7 D1 C1 vcon 15V t D7 R8 Z6 C Z5 R4 D2 Z4 R6 Q3 C5 R5 D3 Z3 C4 Z2 D5 G VGE E 1 2 8 CI1 7 6 TLP250 5 C2 Z1 C3 R2 Vcc1 Q1 Q2 R3 R1 3 4 Nas Figs. Em relação ao sinal de entrada.] b) Vcon e VGE [5V/div. Os dispositivos externos ao circuito integrado são dimensionados de acordo com as limitações do circuito integrado TLP250. 28 é apresentado o circuito de comando utilizando o integrado TLP250 da Toshiba para acionar IGBTs e MOSFETs. 29 (a).. Vcon V GE V con VGE (a)Vcon e VGE[5V/div. O circuito também realiza proteção de curto-circuito por detecção da tensão de dessaturação coletor-emissor. 29 (a) e (b) são mostradas as formas de onda dos sinais de tensão de entrada do circuito de comando Vcon e da tensão de saída gate-emissor VGE para as razões cíclicas 0. Na Fig...1V. 27 (e) são mostradas as formas de onda da tensão coletor-emissor VCE e da corrente de coletor durante o curto-circuito. Por outro lado.9 e 0. ♦ CIRCUITO C3 Na Fig. 27 (d) são mostradas as formas de onda da tensão gate-emissor VGE e da corrente de coletor durante o teste de curto-circuito do IGBT.Circuito de comando de gate isolado com proteção e limitação da corrente de curto-circuito. 10µs/div. na Fig.] (d) VGE [10V/div. Para toda a faixa de variação de Fig. Este circuito apresenta diferenças nos tempos de atrasos da subida e da descida do sinal da tensão de saída..5µs/div.] Fig. 9 e 26. 10µs/div. Estas diferenças serão observadas nas Fig. Uma outra característica do circuito é que permite a limitação da corrente de curto-circuito por meio de redução da tensão gate-emissor após ocorrida a falha. Por outro lado. 27 (c) o sinal de saída VGE tem um atraso na subida de 650ns e um atraso na descida de 700ns.Formas de onda obtidos com os circuitos das Figs. 29 (b) o sinal de saída VGE tem um atraso na subida de 400ns e um atraso na descida de 200ns.

razão cíclica, são iguais os atrasos. Na Fig. 29 (c) são mostradas as formas de onda da tensão gate-emissor VGE e da corrente de coletor durante o teste de curto-circuito do IGBT. Nesta figura, observa-se que quando ocorre o curto-circuito a tensão gate-emissor VGE é reduzida ao valor da tensão de operação do zener Z2 e, como conseqüência, a corrente de curto-circuito de coletor é mantida em um valor de aproximadamente duas vezes o valor nominal. Desta maneira o interruptor é capaz de suportar a situação de curto-circuito por um tempo muito maior que o tempo recomendado (10µs). Como pode-se observar, o interruptor suporta 18µs sem ser destruído. Na Fig. 7.29 (d) são mostradas as formas de onda da tensão coletor-emissor VCE e da corrente de coletor durante a ocorrência de curto-circuito do IGBT. Nesta aquisição é mostrado o detalhe do efeito da descida da corrente de curtocircuito que provoca uma sobretensão entre coletor e emissor devido às indutâncias parasitas do circuito de potência. Como a magnitude da corrente de curto-circuito é pequena em relação à magnitude de corrente em operação normal (sem limitação de corrente de curto-circuito), as sobretensões entre os terminais de coletor-emissor são muito pequenas.
V con V con


(a) Vcon e VGE 5V/div.; µs/div.] (b) Vcon e VGE [5V/div.; µs/div.]





(c) VGE [5V/div.; 10µs/div.] IC [50A/div.; 10µs/div.]

(d) VCE [50V/div.; 10µs/div.] IC [50A/div.; 10µs/div.]

Fig. 29 - Formas de onda obtidas com os circuitos das Figs. 8 e 28.

♦ CIRCUITO C4 Na Fig. 30 é apresentado o circuito de comando dedicado SKHI22 da Semikron para acionar dois IGBTs em meia ponte. Este circuito é isolado por meio de transformador de pulso. O circuito não necessita fonte de tensão no lado da saída pois possui internamente um conversor cc/cc que gera as tensões complementares ±15V para os pulsos de comando do gate. Além disto, realiza ajuste de tempo morto através de sua lógica interna quando são aplicados pulsos de entrada sem tempo morto. O valor mínimo do tempo morto é de 2,7µs com possibilidade de ajuste acima do valor indicado. Os tempos de retardo dos sinais é em torno de 1µs na subida e 1µs na descida. O circuito apresenta proteção de curto-circuito por detecção da tensão de saturação coletor-emissor VCEsat. O tempo de retardo de detecção de curto circuito é 1,75µs para RCE = 24kΩ e CCE = 330pF (RCE e CCE são componentes externos ao integrado com os quais é possível ajustar este retardo, C1 e C2 , R4 e R9 da Fig. 30). Após este tempo de retardo o sinal de saída é inibido por 1µs. Em operação normal o pino de erro do circuito integrado encontra-se em nível alto (15V) e quando ocorre a falha em nível baixo (<0,7V). Quando ocorre a falha, os pulsos de entrada do circuito integrado devem ser inibidos completamente, pois se isto não ocorrer tem-se pulsos de curta duração na saída do circuito integrado que podem provocar curtos-circuitos sucessivos do IGBT até destruí-lo. Os dispositivos externos ao circuito integrado são dimensionados de acordo com as recomendações dadas no catálogo do fabricante do circuito de comando integrado. O circuito integrado SKHI22 é recomendado para operar na faixa de freqüências de 5kHz a 100kHz. Ele apresenta um tempo morto de 2,7µs; por este fato pode não ser conveniente em algumas aplicações de freqüências elevadas. Quando o circuito de comando é aplicado em módulos de IGBTs de elevada capacidade de corrente de coletor IC, sua freqüência de operação é limitada pela carga da capacitância de entrada dos módulos. Nas Figs. 31 (a) e (b) são mostradas as formas de onda dos sinais de tensão de entrada do circuito de comando VIN1 e da tensão de saída gate-emissor VGE1 para as razões cíclicas 0,9 e 0,1. Em relação ao sinal de entrada VIN1, na Fig. 31 (a), o sinal de saída VGE1 apresenta um atraso na subida de 1µs e um atraso na descida de 1µs, por outro lado, na Fig. 31 (b) o sinal de saída VGE também tem um atraso de 1µs na subida e na descida. Neste circuito de comando os valores dos atrasos são praticamente iguais na subida e na descida, tal como indica no catálogo, para qualquer variação de razão cíclica. Nas Figs. 31 (c) e 31 (d) são mostradas as duas formas de onda de saída do circuito de comando. As mesmas são complementares para acionar dois interruptores IGBTs de um mesmo braço de um conversor em ponte. O tempo morto é ajustado acima do valor de 2,7µs através dos resistores R1 e R2 da Fig. 31.

Vcc1 VCE1 CCE1 VS V IN1 R1 R TD1 CI1 GON1 R3 R4 C1 R5 R6 Z1 R11 Z2


C1 G1



E1 E2




R7 R8 C2 R9 R10


Z3 Z4

G2 C2

Fig. 30 - Circuito de comando de gate isolado com proteção de curto-circuito.



(a)VIN1 e VGE1[5V/div;5µs/div.] (b)VIN1 e VGE1 [5V/div;5µs/div]

(c)VGE1 e VGE2[5V/div;5µs/div] (d)VGE1 e VGE2[5V/div;5µs/div] Fig. 31 - Formas de onda obtidas com os circuitos das Figs. 9 e 30.

♦ CIRCUITO C4 Na Fig. 32 é apresentado um circuito de comando muito simples para inversores, com uma utilização mínima de componentes, utilizando transformadores de isolamento. Embora o circuito não tenha proteção de curto-circuito, permite aplicar uma tensão negativa durante o bloqueio e não necessita de geração de tempo morto.
+Vcc +15V Tr1 D1 T2 R2=47R Dz2 Dz3 R1=2k2 T1 D2 T3 Dz4 Dz5 D3 Lr Cs



Fig. 32 - Circuito de comando de gate isolado com transformador.

O transformador de isolamento foi projetado para utilização com uma freqüência de comutação de 35kHz, utilizando um núcleo da Thornton tipo E20, com 37 espiras de fio 28 AWG no primário e 40 espiras do mesmo fio em cada secundário. O maior número de espiras no secundário (relação de transformação ligeiramente maior do que 1) permite compensar as quedas de tensão do transistor T1 e do próprio transformador. Para a aquisição das formas de onda mostradas na Fig. 33 os interruptores IGBTs foram acionados com o circuito de comando e de potência da Fig. 32. Todas as aquisições foram feitas para uma freqüência de operação do interruptor igual a 30kHz. Na Fig. 33.a pode-se observar as tensões no enrolamento do primário e em um dos enrolamentos do secundário do transformador. Na Fig. 33.b mostra-se as tensões de gate dos transistores T2 e T3 onde pode-se observar o efeito da capacitância Miller, que varia com a variação da tensão VCE do IGBT.

a) Tensão nos enrolamentos b) detalhe da tensão de gate primário e secundário dos interruptores na comutação

c) VCE1. [100V/div.; 2,5µs/div.] e IC1 [0,5A/div.; 2,5µs/div.] Fig. 33 - Formas de onda obtidas com o circuito da Fig. 32.

Depois dos testes realizados com os diferentes circuitos de comando mostrados anteriormente, chega-se à seguintes conclusões: Os transformadores de pulso dos circuitos de comando de gate foram projetados para operar em uma freqüência de comutação de 10kHz. Embora projetados para esta freqüência, ainda assim funcionam sem problema até freqüências de aproximadamente 40kHz. Porém, quanto maior for a freqüência, mais difícil será desmagnetizar o núcleo, devido ao elevado número de espiras (maior corrente magnetizante), aumentando os atrasos entre os pulsos de entrada e de saída do circuito de comando de gate. Recomenda-se projetar os transformadores de pulso, exatamente para a freqüência de operação do conversor. Em quase todos os circuitos de comando de gate projetados, os dispositivos que provocam maior atraso são os transistores bipolares de sinal, pois o tempo de bloqueio destes transistores é elevado. Eles, para serem rápidos, necessitam da aplicação de uma corrente de base negativa (transistores npn). Por este motivo, para poder diminuir os tempos de atraso na subida e na descida dos circuitos de comando de gate, recomenda-se, se for possível, a utilização de MOSFETs de sinal. Na prática todos os circuitos de comando de gate testados podem ser utilizados, pois eles apresentam boas características de operação e confiabilidade. A escolha dependerá do critério do projetista do conversor, pois ele deve analisar o tipo de isolamento necessário, em função da freqüência e da variação da razão cíclica. Algumas vezes o critério de escolha também depende do custo dos componentes, volume e peso. As características de custo e confiabilidade não foram analisadas neste trabalho.

[1] - FUJI ELECTRIC; "IGBT data book"; Catálogo; 1994. [2] - SEMIKRON; "Semicondutores de potência"; Catálogo, 1993; pp. A-67 à A-73. [3] - REINMUTH, K.; LORENZ, L.; "A new generation of IGBTs and concepts for their protection"; PCIM'94, June 28-30, 1994, NürnbergGermany; pp. 139-147. [4] - ELASSER, Ahmed et al; “Switching losses of IGBTs under zero-voltage and zero-current switching”; IAS’96, San Diego, California, – U.S.A.; 1996; pp. 600-607. [5] - BALIGA, B. J.; "Modern power devices"; Ed: John Wiley & Sons, Inc., 1987; pp. 350-401. [6] - MARTINS FERNANDEZ, D. J.; "Conversor DC-DC quase-ressonante para altas potências utilizando IGBT"; Dissertação de Mestrado em Engenharia Elétrica; Florianópolis, UFSC-Brasil; 1991. [7] - ELASSER, Ahmed et al; “Switching losses of IGBTs under zero-voltage and zero-current switching”; IAS’96, San Diego, California, – U.S.A.; 1996; pp. 600-607. [8] - CLEMENTE, S.; DUBHASHI, A.; PELLY, B.; " IGBT characteristic and application"; Application Note, AN-983A; 1994; pp. 93-106. [9] – BASCOPÉ, René Pastor Torrico; PERIN, Arnaldo José; "O transistor IGBT aplicado em eletrônica de Potência"; Editora Sagra Luzzatto, Porto Alegre – RS, 1997. [10] - BISWAS, S. K.; BASAK, B.; RAJASHEKARA, K. S.; “Gate drive methods for IGBTs in bridge configurations”; IAS’94; 1994; pp. 13101316. [11] - LETOR, R.; MELITO, M.; "Safe behavior of IGBTs subjected to dv/dt"; SGS-Thomson, Application Note, AN476/0492, 1994; pp. 715-723. [12] - SANTOS, A.; “Driving high current IGBTs in high-power circuits”, COBEP’95, 3rd Brazilian Power Electronics Conference, December 4 to 7, São Paulo-Brazil, 1995; pp. 621-625. [13] - BARBI, I.; “Projeto de fontes chaveadas”; Publicação Interna, Florianópolis - UFSC - Brasil; pp. 31-58, 1990. [14] - BARBI, I.; ANDRADE, E. ;“Projeto e implementação de um inversor para cargas não lineares”; Relatório Interno, UFSC- Brasil, Março 1996.

In order to optimally implement all of the advantages of the IGBT device. but high voltage and high current modules are not available. The Insulated Gate Bipolar Transistor (IGBT) device is a power semiconductor device introduced to overcome the limitations of the power BJTs and power MOSFETs. However. it is essential that the designer understand the general operating characteristics of the device.MOTOROLA SEMICONDUCTOR APPLICATION NOTE Order this document by AN1540/D AN1540 Application Considerations Using Insulated Gate Bipolar Transistors (IGBTs) Prepared by: C. a brief overview of the device and its characteristics will be presented. This device eliminates the high on–state losses of the MOSFET while maintaining the simple gate drive requirements of that device. lightweight. But the minority carrier injection by the p+ substrate serves to NPN P+ JFET channel P– N+ P+ body Drain–to–Source Body Diode (Created when NPN base–emitter is properly shorted by source metal) N– EPI N+ SUBSTRATE DRAIN Figure 2. The p–type substrate is the emitter of the bipolar transistor and is the anode terminal of the device. GATE EMITTER KEY METAL SiO2 POLYSILICON GATE INTRODUCTION P– In the power electronics arena there is a constant demand for compact. In this section. The large n– area is needed in order to block high voltages. but the output current is that of a bipolar transistor. This device is controlled by the gate voltage as is the power MOSFET. When sufficient gate voltage is applied. The injected minority carrier density is typically 100 to 1000 times higher than the doping level of the n–type epitaxial drift region. and efficient power supplies. Basic Structure of VDMOSFET ©MOTOROLA Motorola. the heavily doped p+ substrate injects minority carriers into the low doped n– epitaxial layer. the demands for the power converters are not fully satisfied by power bipolar transistors (BJTs) and power MOSFETs. In turn. Power MOSFETs have high speed switching. It is quickly replacing most of the power BJTs because of its speed and ease of gate drive. reduce this resistance and thus modulates its conductivity. Basic Structure of IGBT GATE SOURCE KEY METAL SiO2 POLYSILICON GATE P– N+ DEVICE STRUCTURE A schematic structure of an N–channel IGBT device is shown in Figure 1. but their switching speeds are not satisfactory. the current that flows at the surface of the MOSFET channel enters the low doped epitaxial layer and appears as a drain current at the substrate.S. 1995 1 . DEVICE CHARACTERISTICS The recently introduced Insulated Gate Bipolar Transistor (IGBT) has been undergoing considerable improvement and maturation due to improvement in process technology. This device has become the most popular new device used by the power electronics design engineers. Mitter Motorola Inc. Inc. but it contributes to a large on–state resistance. High current and high voltage BJTs are available. N+ r′b P– N+ P+ NPN MOSFET Rmod P+ body PNP N– EPI N+ BUFFER P+ SUBSTRATE bipolar emitter COLLECTOR Figure 1. The structure is similar to that of a Vertical Double Diffused MOSFET (VDMOSFET) with the exception that a p–type heavily doped substrate replaces the n–type drain contact of the conventional VDMOSFET (see Figure 2). These devices combine the best features of both the bipolar transistors and of the MOSFET.

voltage–driven gate drive to turn on and turn off. the BJTs will latch on and behave just like an SCR. This JFET is represented by the modulated resistor Rmod. 3. and a JFET. If the gains of both transistors are significant enough. At high currents the on–resistance increases with increase in temperature. but trades off forward drop. r ′b. are collected by the body–epitaxial layer which is reverse–biased in the forward conduction operation. (This is a conceptual model and should not be confused with the actual physical structure of the IGBTs. PNP NPN GATE r ′b EMITTER Figure 3. As shown in the model.AN1540 The minority carriers. This JFET supports most of the voltage and is highly modulated giving the MOSFET its low RDS(on). The sum of electron current and whole currents make up the total collector current of the IGBT device. The n+ buffer layer is introduced for the following reasons (we will not discuss it in detail in this paper): 1.) It was shown that with increasing temperature. But this latching process is avoided by the base–emitter short resistance. It uses the low–power. in the equivalent circuit. since only a small gate–drain capacitance charging and discharging current is required (this is one of the real benefits of the IGBT). a PNP bipolar transistor. Because this process reduces the on–resistance of the device. Cres. the IGBT combines the best features of the devices mentioned. Positive Temperature Coefficient The IGBT also has a favorable temperature coefficient for on–resistance. Prevents punch–through of depletion region to p+ substrate. and possesses a gate impedance as high as that of the power MOSFET. because a smaller chip area is required for a given current rating. it can be assumed to be off. IGBT Detailed Equivalent Circuit Showing the Parasitic Components Since the current to the base of the NPN bipolar transistor is bypassed. The structure of IGBT also reduces the reverse transfer capacitance. 2. and this MOSFET provides the electrons (majority carrier) for recombination in the epitaxial layer and some are injected into the p–substrate region (bipolar emitter). This only affects speed of non–irradiated devices. Reduces PNP bipolar transistor gain which improves latching and prevents thermal runaway of leakage current at high temperature 5. The circuit consists of an N–channel MOSFET. Limit injection of holes into n– region. The disadvantage of conductivity modulation is the increase in device switching time compared to the MOSFET due to stored charge in the wide base region. the bipolar PNP and NPN form a four layer npnp structure of an SCR. This smaller capacitance results in a very low gate drive power requirement. ADVANTAGES OF IGBT Ease of Gate Drive As discussed previously. Creates low lifetime region for recombination. Low Conduction Loss The conductivity modulation of the n– layer greatly increases the current–handling capability of the IGBT for a given die size. IGBT Detailed Equivalent Circuit Showing the Parasitic Components 2 MOTOROLA . This resistance acts as a shunt to the base–emitter junction of the NPN thereby preventing the NPN bipolar transistor from turning on strongly enough to start the latching process. COLLECTOR EMITTER COLLECTOR PNP NPN GATE r ′b Figure 4. (Note that under nominal and lower collector current range. Sets breakdown voltage of back junction Much of the discussions presented have been EPI type or “punchthrough” IGBTs because the basic understanding of the device centers around the EPI type IGBTs. the devices do have negative temperature coefficient. and thus the device will not experience the thermal runaway which occurs in the power BJTs. The simplified equivalent circuit clearly shows that the drain current of the MOSFET (electron current) supplies the base current of the PNP.) The JFET is formed where the MOSFET current flows between two adjacent body diffusions [1]. This makes faster devices. an NPN bipolar transistor. This conductivity modulation has been shown to increase the forward conducting current density at given anode voltage up to 20 times that of an equivalent MOSFET and five times that of a BJT [2]. This equivalent circuit only consists of a PNP bipolar transistor and the N–channel MOSFET. IGBT Equivalent Circuit The simplified equivalent circuit representing the internal structure is shown in Figure 3. which do not recombine as they diffuse towards the body. The MOSFET channel is formed under the gate where the body meets the silicon surface. the current sharing of the devices in parallel operation is improved [3]. and this assumption results in the more simplified equivalent circuit as seen in Figure 4. the conduction loss is minimized. 4. This allows thinner epitaxial to be used which lowers VCE(on).

and results in unwanted current tail (see Figure 5). IGBT can block reverse voltage (approximately –20 V). When operating in forward conduction. the IGBT device possesses a few unwanted characteristics. One disadvantage is the current tail during turn–off.AN1540 No Internal Anti–parallel Diode This can be advantageous or disadvantageous. and the current handling is similar to that of BJTs. The turn–on time is very fast and is determined by the rate of on–voltage saturation of the integral PNP bipolar transistor. which can occur in power MOSFETs. When the device operates in forward conduction. CONCLUSION The IGBT is a new power semiconductor device which possesses the best features of the both the MOSFET and bipolar transistor. frequency of 25 kHz is obtainable without any special resonant switching technique. IGBT Turn–Off Waveform MOTOROLA 3 . The designer has the freedom of selecting the optimum rectifier if it is needed in a freewheeling application. DISADVANTAGE OF IGBT Current Tail Even with many favorable qualities. and with the use of series diode. the high resistance region n– epitaxial layer is highly modulated with injected excess minority carriers (conductivity modulation). The device is controlled by the same low–power. When the gate voltage is removed. this excess of minority carriers must be removed before the device stops conducting completely. This slow switching contributes to a large switching energy and limited operation frequencies. It has been shown that the current density is 20 times that of power MOSFETs and five times that of BJTs. At present. voltage–driven gate as for the power MOSFETs. one is the slow switching speed as compared to the power MOSFET. The absence of this anti–parallel diode protects the IGBT from reverse conduction problems in the free–wheeling diode. With the absence of antiparallel diode which is present in power MOSFETs. reverse blocking capability can be greatly increased. its conduction loss is reduced by the conductivity modulation achieved by the high level of minority carrier injection from emitter toward the wide base region of the device. The turn–off speed of the device is determined by the integral bipolar open–base charge decay. and this introduces higher switching losses and limits the operating frequency of the device. VCE IC CURRENT TAIL Figure 5.

During t1. But it is well known that MOSFETs have the simplest gate drive requirements of all the power devices mentioned. Idealized Turn–on Switching of IGBT 4 MOTOROLA . The current VGE t0 t1 t2 t3 t VCE IC t Figure 2. The device can be driven with low power. The parameters that aggravate the problems associated with high di/dt and dv/dt have been shown to be DC bus inductance. and can affect overall system efficiency. and the switching characteristics can be accurately controlled if all of the circuit parameters are well known. Some of the problems associated with rapid di/dt and dv/dt are discussed. In order to give design engineers a thorough overview of the device characteristics. SCRs become difficult to control due to loss of gate control during turn–off. and external components play a vital part in controlling the device switching under clamped inductive load. + gm dVdt (1) The time rate of change in gate–emitter voltage during t1 period is given by: dVGE dt – Vplateau) + (VGG . the designer can avoid some of the common problems. Because IGBTs are much like fast MOSFETs during the switching transitions. During the time period t0. Clamped Inductive Load TURN–ON Because the IGBT is a MOS–gated device. this section reviews some of the switching characteristics within the clamped inductive load circuit. large gate return loop area. The following expression can be used to express the current slope: dIC dt GE . RG @ Cies (2) If we substitute equation 4 into equation 1. Ideal switching waveforms describing the clamped inductive load circuit are shown in Figure 2. its switching characteristics must be understood by the design engineers in order to avoid some of the problems associated with high voltage and high current transitions. circuit layout. This paper covers some of the fundamental switching characteristics. the series collector inductance. and the antiparallel diode of the clamped inductive load. common emitter inductance (common to gate drive circuitry). and as is the case with the MOSFET. freewheeling through the diode. This simplifies the circuit design. All of these parameters contribute significantly to the durability and longevity of the devices. By understanding the device characteristics and the problems associated with rapid di/dt and dv/dt. and shows how critical the gate drive circuit is in determining the switching characteristics of the IGBTs. The inductance Ls is the series parasitic inductance due to the power trace and any wiring between the IGBT’s collector and DC bus. voltage pulses of required polarity. Figure 1 shows the clamped inductive load circuit used to analyze the switching characteristics of the IGBT. the gate current charges the constant input capacitance (Cies) with a constant slope. nothing happens until the gate–source voltage is raised to the threshold voltage Vth of the device. and these devices undergo high voltage and high current transitions. slope is dependent on gate voltage rise time and device forward transconductance. It is assumed that the inductor initially has a constant steady state current flowing through it. In addition. the collector current is redirected from the diode into the device and increases to its steady state value. The inductance Le is the common emitter inductance seen by both the power return and the gate return. and suggestions are presented in order to overcome these problems. RG @ Cies (3) DC SUPPLY IL LOAD Ls RG IGBT VGG Le DC RTN Figure 1. the turn–on switching performance is dominated by the MOS structure of the device. It is shown that the gate drive circuit.AN1540 IGBT GATE DRIVE CONSIDERATIONS INTRODUCTION Devices such as BJTs and thyristors require complicated and very inefficient methods of driving the devices due to their low gain and minority carrier device characteristics. the rate of change of collector current is expressed as: dIC dt – Vplateau) + gm (VGG .

In order to overcome this problem. will reduce much of the unwanted inductance. and the collector–emitter voltage starts to decrease. + Vth ) gm (4) the initial collector current rise because of its gate current limiting while increasing the turn–on loss [4]. Gate–Emitter Voltage Due to Temperature Variation ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 4000 VCE = 0 V 3200 C. A sample of a gate charge curve for an IGBT is shown in Figure 5. and once inductance has charged to its maximum load current. The control of turn–on di/dt can be seen by observing equation 5. see Figure 3). and a further increase in gate–emitter voltage has no effect on the dynamic characteristics. more accurate assessment of gate drive current can be determined. GATE–TO–EMITTER VOLTAGE (VOLTS) 11 0 Figure 3. the switching time must be very short. where. the gate–emitter current loop must be short. + Cres dVdt + (VGG –RV G Vplateau IC .AN1540 During the plateau region t2. Figure 4 is a sample curve indicating the capacitance values for input. However. the fast switching speed will introduce high di/dt (maximum di/dt is a function of load inductance and the gate drive: 1) where initial di/dt = V/L. Overlapping the power and return paths of the gate drive has the advantage of nullifying magnetic field induced by power trace with the magnetic field induced by the return trace and the effective loop inductance is minimized. the rate of the rise of the device current can be increased. (5) and gm is the forward transconductance of the device at the given steady state collector current IC and can be obtained using the transfer curve provided by the data sheets. 2) the di/dt will be dominated by the gate drive) which will interact with the lead inductance of the emitter. and be able to provide a large narrow pulse of current to charge the input capacitance which includes the feedback capacitance and gate–emitter capacitance. but remember that the inductance seen by the gate must be minimized. This requires that the gate drive be a low impedance type. Using these equations. Turn–On Switching Considerations In order to reduce the dynamic turn–on loss. as we will discuss later. COLLECTOR CURRENT (AMPS) 30 20 10 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁ Transfer Characteristics VCE = 100 V 5 µs PULSE WIDTH TJ = 125°C 25°C 5 6 7 8 9 10 VGE. IGBT Capacitance Curves MOTOROLA 5 . gate drive current is discharging the voltage–dependent reverse transfer capacitance at a constant gate current that can be expressed as: ig plateau) CG . the final gate–emitter voltage determines how much turn–on loss is expended by the circuit and determines the magnitude and duration of short circuit current handled by the device. All of the above expressions are presented to show the relationship between the series gate resistance and its effect on the rise time of the device current. Placing the components as near as possible to the gate–emitter terminals. along with good circuit layout. and reverse transfer capacitance Cres. the designer can control the current and voltage slope during turn–on. output. It is good practice to use twisted wire or parallel power paths. The turn–on switching time is determined by how quickly the input capacitance Cies is charged. By using the amount of charge needed to turn the device on at a certain operating point. Transconductance is determined by steady state collector current divided by the intercepting gate voltage (IC/VGE. the gate–emitter voltage has reached the value which will support the steady state collector current. A better method of obtaining the capacitance would be to use the gate charge transfer curve. This large di/dt will induce large enough transient voltage across the common emitter inductance and will reduce the available gate voltage causing linearization of 40 IC. CAPACITANCE (pF) 2400 Cies 1600 800 Coes Cres 0 Capacitance Variation ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ TJ = 25°C 0 5 10 15 20 25 GATE–TO–EMITTER OR COLLECTOR–TO–EMITTER VOLTAGE (VOLTS) Figure 4. but for qualitative results the curve given by Figure 4 is adequate. During this region. It should be noted here that the above analysis ignores the change in bipolar current gain as base charge is supplied. Also. But. In this equation it is evident that by changing the gate resistor value. The parameter for input capacitance Cies can be obtained using the capacitance curve provided by the device vendors. a small gate resistance is placed in series with the gate of the device. During region t3 the dynamic switching is completed.

where Ls is the stray inductance of the power DC bus. A snappy recovery can be controlled or eliminated by increasing the gate resistance RG. VGE tdelay 0 20 40 60 Qg. t6. Because of the high di/dt.” This current tail limits the operation frequency of the IGBTs. the collector voltage rises beyond the bus voltage due to L(di/dt) overshoot. This period is greatly influenced by the gate drive design and its drive impedance. proper choice of the freewheeling diode is absolutely critical in the performance of the device. an ultrafast diode with a soft recovery must be chosen. Nothing is observed while gate voltage is decreased. This period is defined as the time it takes for Ic to drop from 90% of its full current down to approximately the 10% level (this will include the tail). A local bypass for the DC bus should be provided as near as possible to the device with a high current. For small gate resistance. 6 MOTOROLA . a surge can occur during the recovery of the freewheeling diode. and the size and length of this current tail is determined by the device design and process technology. R G. This recombination process produces what is frequently termed as the “current tail. This current slope is due to the recombination of the minority carriers in the wide base region of the integral BJT. res @ RG (6) Equation 6 assumes that the gate resistance is large enough that the output capacitance is not the limiting factor. Figure 6 shows idealized turn–off waveforms for switched inductive load. GATE–TO–EMITTER VOLTAGE (VOLTS) 16 12 8 ÁÁ ÁÁ ÁÁ ÁÁ Q1 0 ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ QT Q2 4 ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ VGE TJ = 25°C IC = 20 A collector voltage rises. The first part of the turn–off process is the delay time (td(off)). the rapid di/dt will cause a large positive voltage to be seen by the device which can exceed the rating of the device. and the effect of RG on the collector current fall time is expressed as: dIC dt plateau + RV . Without these precautions the IGBT may encounter avalanche breakdown due to di/dt induced transient during the turn–off time. until the gate voltage reaches the value required to keep the collector steady state current to flow.AN1540 Gate–to–Emitter and Collector–to–Emitter Voltage versus Total Charge VGE. or decrease due to Ls(di/dt). Otherwise a snubber must be used to control the snappy recovery of the diode. the freewheeling diode starts to conduct. this large di/dt will cause a large dv/dt once the diode is recovered. which is the effect of the time required for the gate drive to pull VGE from its full value to the level at which the collector voltage begins to increase. The region. but this will increase the turn–on time. Idealized Turn–off Switching for IGBT At t6. Therefore. RG. low ESR capacitor. During turn–off. Therefore. This period is greatly influenced by the gate drive design and its drive impedance. For high di/dt. Therefore. the The time period t7 shows an abrupt decrease in current slope. Gate Charge Transfer Curve VCE t Rapid di/dt not only limits the available gate voltage. During t5. and the efficiency of the circuit will suffer. and its rate of rise can be controlled by the gate resistance RG: dVCE dt plateau + CV . period t6 is determined by the clamp inductance. The high di/dt caused by the snappy recovery of the diode can cause large unwanted voltage transients. G @ Cies (7) TURN–OFF The turn–off of the IGBT is initiated by removing the voltage across the gate–emitter just as for MOSFETs. Effect of the Freewheeling Diode Just as during turn–off. it is important to reduce di/dt during turn–on and turn–off duration. IC CURRENT TAIL t4 t5 t6 t7 t Figure 6. is the initial fall time. the collector voltage has reached the bus voltage VDD. Because of the stray inductance within the circuit and the device leads. TOTAL GATE CHARGE (nC) 80 Vth Figure 5. and this is the time required for the gate drive circuit to remove the charge that flows into the gate from the gate–to–drain capacitance as VDS increases during turn–off. and collector current starts to decay. the reverse recovery of the diode can become very snappy. but causes the bus voltage to dip.

Make the gate drive connection as short as possible to the device being used so as to reduce any parasitics 4. Use a negative bias if possible to reduce any dv/dt problems MOTOROLA 7 . The ground loop of the gate drive must be separated from the power return so that the common emitter inductance does not interrupt the turn–on process. This current tail contributes to limit operational frequency and introduces large switching energy to be dissipated by the device. Also a series resistor should be used when negative gate bias is applied during the turn–off process. Reduce the gate–emitter current loop by separating the power return and gate return 2. In order to reduce any unwanted supply bus inductance. we cannot discharge the excess minority carriers by reverse biasing the gate. or just as in gate drive. The rapid turn–off will cause a high dv/dt. and as a result. Effect of the Current Tail The t7 interval. This will protect the device from the false turn–on due to the dv/dt problem. RG to limit di/dt and dv/dt 5. it was suggested that a bypass capacitor with low inductance and low ESR be connected right at the device level. di/dt and dv/dt can be controlled. but it helps to speed up the turn–off of the MOSFET portion. A small gate–emitter resistance can be added to the terminals to bypass the dv/dt problem. the following have arisen as the important factors that need to be considered when designing the gate drive: 1. Layout of the circuit was vital in overcoming some of the switching problems. and as such the highly resistive region (n– epitaxial layer) is highly injected with minority carriers. IGBT is a minority carrier device during the forward conduction. This tailing effect is the direct result of the internal base of the PNP structure which cannot be accessed by the external means. is a result of minority carrier recombination in the bipolar PNP structure. The problem associated with high dv/dt is that it can introduce current through the capacitance to the base of the internal parasitic NPN bipolar transistor (only in a bad device). Through the correct use of gate drive the designer can overcome some of the common problems associated with high voltage high current switching: 1) accurately control di/dt and dVCE/dt problems. care must be taken in the beginning stage of the design to ensure that circuit layout will support the high di/dt and dv/dt. CONCLUSION IGBTs are excellent candidates for high power applications. However. many of the common problems associated with high current and high voltage switching can be dramatically reduced. and thus turns off the base of the integral PNP bipolar transistor quicker. the gate–control is lost and the device cannot be turned off without removing the power to the collector terminal of the device (see Figure 2). By following some of these recommendations. The negative bias should be left on while the device is turned off. How fast the minority carriers recombine determines how long the current tail is and the turn–off speed of the device. thereby causing the device to latch on. Using a negative bias at the gate reduces the chance of false turn–on and latching of the device. Use a series gate resistor. the supply bus tracks can be paralleled. Not only was the gate drive vital in determining the switching loss. The turn–off speed of the device is therefore determined by the integral bipolar open base turn–off. as discussed earlier.AN1540 Turn–Off Considerations Just as with the MOSFETs a negative bias can be applied to the gate in order to speed up the turn–off. GATE DRIVE REQUIREMENTS From the previous discussion of switching characteristics of the IGBT. Some equations have been provided so that by using appropriate gate resistors. The controlled rate at which the minority carriers recombine is a function of device design and process technology. This minority carriers must be removed before the device stops conducting completely. Optimum values of the resistors can be found by trying different values of the resistor in the circuit to be used or by simulation. but the freewheeling diode in a clamped inductive load introduces turn–on switching losses. This does not mean that the recombination of minority carriers in the wide base region will be increased. The twisted wires or parallel power tracts should be used for the gate drive. Once the device is latched on. when switching high voltage and high current. It was observed that the gate drive is a vital element in obtaining the maximum performance of the device. and 2) avoid latching of the parasitic thyristor. It is of utmost importance that an ultrafast diode with soft recovery type be chosen. Use a twisted wire if possible and overlap the power traces of gate drive if PCB is used 3.

and if the energy is beyond the capability of the device it will be destroyed due to thermal breakdown. increase in gate–emitter voltage reduces turn–on loss. it is clear that the smaller gate voltage limits the current at lower value and increases the short circuit time duration. once the gate–source voltage has reached the value to support the steady–state drain current. In understanding this. the turn–on characteristics of IGBTs are similar to those of a MOSFET. Turn–on Loss with Different Gate–Emitter Voltage Figure 2. During the short circuit fault. During this time the device will have a large amount of energy across the device. For given collector currents. 20 ohms. IGBTs produced by Motorola are capable of short circuit survivability of 10 µs minimum. Figure 3 data shows the relationship between the gate voltage. device. TURN–ON LOSS As mentioned before. In this section some of the impacts of the gate–emitter voltage on the device performance will be examined. the magnitude of the gate–emitter supply voltage of an IGBT has a significant impact on the performance of the device. The magnitude of the gate voltage impacts the turn–on loss and short circuit survival capability of the devices. the gate current available increases with the increase in the gate voltage. As shown in Figure 3. the large current can cause parasitic NPN bipolar transistor to turn on and cause the device to latch. Equivalent Short Circuit Condition SHORT CIRCUIT FAULT OPERATION A major concern in inverter applications is the ability to survive a short circuit fault condition. This can be explained by the fact that for a given gate resistor. Another method of increasing the short circuit survivability is to decrease the gate voltage when the short circuit across the device is observed. Figure 1 depicts measured data that shows the relationship between gate–emitter voltage and turn–on loss with a constant RG. but rather limits the amount of the energy dissipated by the device by limiting the collector current. The most effective way to provide the short circuit survivability would be to inherently build current sensing capability into the device. the collector current will rise to some undetermined value limited by the gate–emitter voltage. Because of the high gain characteristic of the IGBTs. There are many different ways to protect the device from the short circuit condition for some duration. but as of now. it is clear that the device should be able to survive a short circuit condition if the energy delivered to the device is maintained below some value that is tolerable to the device. 50 45 40 Eon . and the short circuit survival time period. larger gate–emitter voltage reduces the turn–on loss of the device. short circuit current. As shown by the curves. The magnitude of the gate–emitter voltage significantly affects the magnitude of the turn–on loss during the transition. Therefore. One point to note here is that the IGBTs are less sensitive to second breakdown due to hot spot formulation unlike the BJTs. the more energy is dissipated by the device. Therefore it is of utmost importance that the device be able to survive a short circuit fault condition. This provides enough time for the external protection circuits to be activated. For the bad devices. wherein the gate control will be lost. the input capacitance of the device is charged at a faster rate which can account for less loss. Remember that the device does not turn off when a short circuit occurs. a further increase in VGS has no significant role in the circuit. In MOSFETs. but it does greatly affect the switching speed of the device. no manufacturer has any device which has built–in current sense for short circuit detection. The longer it takes the device to turn on. while the gate potential is at full operating value (see Figure 2). (NORMALIZED) 35 30 25 20 15 10 5 0 0 2 4 6 8 10 12 IC IN AMPS 14 16 18 20 20 V 15 V 17 V RG = 20 OHMS 12 V SHORT CIRCUIT FAULT VDD VGG Figure 1.AN1540 EFFECT OF GATE–EMITTER VOLTAGE ON TURN–ON LOSS AND SHORT CIRCUIT CAPABILITY INTRODUCTION Unlike the MOSFETs and BJTs. the device is exposed to the supply voltage across the 8 MOTOROLA .

Because of their use in high power applications. Short Circuit Response of IGBT MOTOROLA 9 . Using these two relationships. But as we have discussed. the designer needs to understand that the high gate–emitter voltage reduces the short circuit survivability of the device. Figure 3.AN1540 SUMMARY Short Circuit Time & Current versus Gate Voltage 80 ISC 40 60 I SC IN AMPS 30 t SC IN µ s 40 20 20 tSC 0 10 11 12 13 14 15 16 VG IN VOLTS 17 18 19 10 0 20 IGBTs are high current and high voltage devices. and is a function of the diode’s reverse recovery time. the designer can choose the best voltage value which will meet their design requirements. In most cases. But on the other hand. the turn–on loss of the device in a clamped inductive load is dependent on the performance of the free–wheeling diode. the magnitude of the gate–emitter voltage can be optimized in order to reduce the turn–on loss of the device. it is important that some of the key behavior of the device is understood by the user in order minimize switching losses and to prolong their lifetime.

At high temperature. For low current levels. it can be misunderstood that the device always possesses a positive temperature coefficient (that is. This may be true if other factors such as conduction current. In this section the on–state voltage characteristics and dynamic turn–off will be discussed. It is shown that the unique characteristics of the IGBTs allow the designer to operate the device to obtain low conduction loss. All of these add to the turn–off energy loss and can damage the device if care is not taken. in other cases switching losses may be the major concern. the device possesses a positive temperature coefficient characteristic and its saturation voltage increases with increase in temperature. These effects all contribute to higher turn–off energy loss. Figure 1 shows the temperature dependence of collector current versus collector–emitter voltage. But for higher current levels. the design engineer can better assess the best operating parameters for a given application. At higher current levels. Figure 2 shows the dramatic increase in turn–off loss at high temperature. But because IGBTs possess dual device characteristics. and initial anode current tail height is also increased. 10 MOTOROLA . By understanding how the device behaves with the temperature at turn–off. introduce the positive temperature coefficient which is a MOSFET effect of the device. the two curves cross each other and at this crossover point VCE becomes temperature independent. It was discussed by Hefner [5] that: 1) the base resistance increases with temperature due to decrease in the mobility of the carriers. the turn–off energy loss is increased with temperature. there are a few important things that are happening which contribute to the device on–voltage. During the turn–off at high temperatures close attention must be given to: 1) current tail variation. If the operating current is within the negative temperature coefficient region. thermal environment. 2) emitter–base junction diffusion voltage decreases due to increase in base intrinsic carrier concentration. The BJT characteristics of the device are dominating at this point. coefficient. the on–voltage increases at higher temperature). 60 IC. their behavior is not easily understood. and as a result the saturation voltage is decreased with increase in temperature. and as a result. The current tail is a function of the base minority carrier lifetime and is increased with rise in temperature. Not only is current tail length increased. 3) the drain–source voltage increases slightly with temperature because the decrease in MOSFET transconductance dominates the decreasing threshold voltage for the high gate voltage bias condition. and. dVC/dt. At some current level. The on–voltage of the device decreases with temperature at lower current levels because the base resistance and channel resistance is small compared to the change in emitter–base junction diffusion voltage. one can be mistaken in thinking that operating the device at a higher temperature will be much more efficient. and attention should be given by the designers using the IGBTs. This increase in energy loss is contributed largely by the increase in the current tail. 2) initial current height of the anode current.AN1540 FORWARD CONDUCTION AND TURN–OFF BEHAVIOR OF IGBTS AT HIGH TEMPERATURE AND ITS CONTRIBUTIONS TO STATIC AND DYNAMIC TURN–OFF LOSS INTRODUCTION IGBTs have been introduced to overcome the high on–state voltage of MOSFETs and slow switching frequency of BJTs. the base resistance and channel resistance start to become significant enough and dominate the on–voltage of the device. the device possesses a negative temperature Unlike the relatively temperature insensitive forward voltage drop of the device. dynamic turn–off must be considered at high temperature operation FORWARD CONDUCTION Because IGBTs behave like MOSFETs in switching transitions. 4) and increased carrier lifetime. COLLECTOR CURRENT (AMPS) VGE = 20 V TJ = 25°C 40 TJ = 125°C TURN–OFF 20 0 0 2 4 6 VCE. In high current applications. But also shown are that dynamic turn–off losses must be taken into consideration with variation in temperature. and other operating parameters have been considered. But as we will later see. COLLECTOR–TO–EMITTER VOLTAGE (VOLTS) 8 Figure 1. circuit layout. but the storage time. This perception is partially correct. As we shall see the device actually possesses negative temperature coefficient at low current levels. 3) reduced rate of rise of anode voltage. IGBT Output Characteristics IGBTs possess aspects of both MOSFET and BJT characteristics. the on–state voltage becomes a major issue.

the rate of rise of the anode voltage is also affected by the temperature due to increase in the lifetime. MOTOROLA 11 .40 35 30 Eoff (NORMALIZED) 25 20 15 10 5 0 0 2 4 Turn–off Losses versus IC ÁÁ ÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 125°C 25°C 16 18 20 AN1540 For nonbuffered devices. and diffusivity of the device [6]: IT (0+) ∝ Q ⋅ D (1) VCE IC VCE: VGE: IC: TIME: 50 V/div 5 V/div 2 A/div 250 ns/div VGE CURRENT TAIL Figure 4a. Turn–off Waveforms at 120°C TIME Figure 3. Turn–off Waveforms at 25°C VCE IC VCE: VGE: IC: TIME: 50 V/div 5 V/div 2 A/div 250 ns/div VGE IT (0–) IT (0+) Initial Current Tail Increased Due to Increased Temperature ANODE CURRENT IF Figure 4b. Figure 3 depicts the anode current during the turn–off. and adds to total turn–off loss. and as a result. But in the buffered devices. Not only is more energy dissipated by the device. But for devices with the buffer layer. It was discussed that the IT(0+) is proportional to the base charge Q. This increase in the current tail length and initial current height contributes to a larger turn–off energy loss. and the lifetime is increased which prolongs the current tail during the turn–off of the transistor. Both the increased height and length of tail with temperature means that the device will turn off slower. the increased charge due to the temperature is greater than the decrease in the diffusivity of the device. the increase in the base charge with temperature is negated by the corresponding decrease in the diffusivity. Figures 4 and 4b show turn–off waveforms at two different temperatures. The data shows that the initial current height and current tail is increased significantly at higher temperatures. this initial tail height increases with the temperature. Anode Current During Turn–off Collector Voltage Transitions In the previous paragraphs it has been discussed how the increase in device temperature decreases the mobility and increases the lifetime of a device. the initial height of current tail remains relatively constant and with temperature only current tail length is increased. This increase in lifetime also increases the current tail length and its associated initial current height. The initial current height is denoted by IT(0+) and is the time at which the current tail starts to decay exponentially. the initial current magnitude varies with temperature. The increase in the current tail can account for almost 60% of the turn–off loss. Turn–off Energy Loss at Different Temperatures Current Tail With an increase in temperature. For devices which do not have the buffer layer. The variation in initial current height and in current tail length is the major contributor to the turn–off energy loss. But as we shall see. 6 8 10 12 IC in AMPS 14 Figure 2. this will reduce the operating frequency of the device. the mobility of the minority carriers in the wide base is reduced.

Larger capacitance then decreases the rate–of–rise of the anode voltage because it takes longer to charge the bigger capacitance. This capacitance is orders of magnitude larger than the depletion capacitance and dominates the effective output capacitance of the IGBT during turn–off. charge Q is charge present in the base. FURTHER DISCUSSION ON TEMPERATURE EFFECT Figure 6 shows all of the phenomenon that has been discussed previously. and hence increases the turn–off loss. The decrease in dVCE/dt causes the collector current to remain at its full steady–state value much longer. THL (2) Current Ibase is a steady state current level. IGBT Equivalent Circuit Superimposed on One–half of Symmetric IGBT Cell (Reprinted with permission from NIST) 12 MOTOROLA .) So special care should be given to the turn–off transition if the device is to operate efficiently under temperature variations. the effective output capacitance and rate–of–rise of the anode voltage must be able to supply the steady–state collector current. The following equation can be expressed as: Ibase Storage Time Other side effects of the decrease in the rate–of–rise of the voltage is that it prolongs the storage time. At high temperature. the turn–off loss encountered can increase much more which will then increase the junction temperature of the device. The first thing to note is that the initial current tail magnitude has increased dramatically. All of the phenomenon discussed are apparent during the turn–off transition. With increase in temperature. the whole lifetime is increased due to reduction of mobility of carriers within the base region. In a clamped inductive load. During the turn–off. and is independent of gate voltage after t6 region (it is assumed that there is no significant variation in gate drive performance with variation in temperature). (See Figure 9. Since the capacitance is proportional to the amount of charge present. Because this capacitance is charge dependent. the collector voltage must reach its full supply voltage value before the collector current starts to decay (see Figure 5). the increase in charge increases the effective output capacitance and thus decreases the rate–of–rise of the collector–emitter voltage. Ccer. The rate–of–rise of the collector voltage is an inverse function of the capacitance. During the voltage transition. If the collector voltage is increased. its value is increased accordingly. Turn–off Behavior of IGBT with Temperature Variations Figure 5. One important factor to remember is that the device was operated only at 50% of its rated voltage. The increase in the base lifetime means that the charge must increase in order to provide the unchanged collector current. and tHL is the excess carrier lifetime.AN1540 Figure 5 shows an equivalent schematic of IGBT showing all of the internal circuits associated with the device. and the following expression can be used to describe its dependency on charge and capacitance: dVC dt 1 1 T Ccer TQ (3) VGE CATHODE GATE STORAGE TIME 25°C Cm n+ c Cdsj b n– BJT Rb Cebj + Cebd p+ e ANODE Ads Agd d Coxs s MOSFET Coxd Cgdj 125°C Vth t 25°C IC VCE 125°C CURRENT TAIL t7 t4 t5 t6 t p+ Depletion Ccer Region Figure 6. its value is varied with change in temperature (charge is varied with temperature). Figures 7 and 8 are measured data showing the effect of temperature variation during the turn–off. dVCE/dt is decreased by a factor of two. the output capacitance is dominated by the collector emitter redistribution capacitance. But also note that the storage time has been increased due to the decrease in dVCE/dt. As shown in Figure 6. Notice the lack of voltage overshoot due to decrease in the slopes. + Q .

Temperature environment of the circuit Device characteristics with temperature variations Increase of storage time Decrease of dVC/dt Increase in initial current tail height Increase in total current tail length Operating current of the device Operating frequency VCE IC VCE: VGE: IC: TIME: 50 V/div 5 V/div 2 A/div 25 ns/div VGE Considering these factors will help the design engineers to better utilize all of the benefits of IGBTs. The design should be done by derating the part for the worst case condition which the device will confront. Turn–off at 120°C (VDD = 300 Vdc) IC VCE VGE: IC: TIME: 100 V/div 5 V/div 2 A/div 25 ns/div VGE VCE Figure 9. 6. Turn–off at 120°C (VDD = 500 Vdc) MOTOROLA 13 . Turn–off at 25°C (VDD = 300 Vdc) IGBTs have very unique characteristics which can be utilized to best meet many of the high power switching applications. 3. If the environment is such that temperature variation is minimal (and can be guaranteed). The following are some of the considerations that should be taken when using IGBTs: 1. it is not straightforward when it comes to designing for temperature variations. one can be assured of device failure or degraded performance. Figure 8. One must not only look at the on–state voltage. the design can be optimized for the on–state voltage because the turn–off energy loss variations will be small. 2.AN1540 CONCLUSION VCE IC VCE: VGE: IC: TIME: 50 V/div 5 V/div 2 A/div 25 ns/div Figure 7. 8. 4. 7. but one also needs to consider the dynamic behavior of the device with temperature. If care is not taken. How well the device temperature is stabilized determines how rugged the device will be. But if the temperature stability is not guaranteed. But unlike BJTs and MOSFETs. the designer needs to consider all of the parameters discussed and great care should be given to device junction temperature. 5.

However. LS2. but as expected the device with higher lifetime had a larger current tail because more charge had to be removed. The inductors LS1. thermal considerations. The circuit used to simulate and test the parallel operation of IGBTs is shown in Figure 1. Design engineers must make sure that the temperature variations do not significantly vary the significant device parameters. In order to understand how the lifetime variation behaved in parallel operation of IGBTs. it is necessary to understand how the temperature changes the characteristics of each device type. it draws more of the load current. were varied between two different devices. Paralleled IGBTs Used in Inductive Load turn–on transitions. These parameters were chosen because the normal process variation of these parameters has the most impact on current sharing for parallel operation [7]. With its lower VCE(sat). Aside from the temperature and device parameter variations. and caution must be observed. But it is unclear as to what or how the temperature is changing the device characteristics. It is true that temperature is the key role player in the destruction of IGBT devices. threshold voltage Vth. and transconductance Kp. the destruction MOTOROLA 14 . but the current imbalance during the steady–state region. This increase in current tail will increase the turn–off loss of that device but should not have significant effect on the static current sharing if the parameter variation is minimal. it is well known and much has been written about how the circuit layout and its contribution can greatly influence the performance of devices in parallel operation. paralleling an ultrafast IGBT with a slow IGBT). During the turn–off sequence. many of the problems associated with the paralleling power IGBT devices can be avoided. With increase in temperature the lifetime increases. The difference in lifetime has no effect on Figure 2. there is no problem associated due to lifetime variations. But if the devices have wide variation in the lifetime. Variations in Lifetime The effect of lifetime on the IGBT is through the bipolar characteristics of the device. Then some suggestions are presented on how to overcome the common problems associated with paralleling IGBT devices. The effect of device parameter variations under static and dynamic current sharing are studied. In this section the characteristics of IGBTs under parallel operation are shown. Figure 2 shows that if the static current sharing is within the tolerable region. The load resistor RL is used to limit the collector current to a safe level. and the effect of temperature and circuit layout are discussed. the length of the current tail of the device with higher lifetime is increased. and pays careful attention to process variations within the given lots. thermal improvements. two devices with dissimilar lifetimes were observed. The thermal effect of the device is overcome by using the same heatsink for both devices and the temperature feedback between the devices will keep the current sharing very constant because the lifetime of both devices will vary together and one will track the other constantly. and thus decreases the saturation voltage.AN1540 IGBT PARALLELING CONSIDERATIONS INTRODUCTION Paralleled IGBTs are used extensively in power modules to obtain higher current ratings [3]. more charge is stored in the wide base region. the typical process variation of device parameters within a given device type is significant enough to result in uneven static and dynamic current sharing if the paralleled devices are chosen randomly from a given lot of IGBTs of the same type. The IGBTs have the dual device (MOSFET and BJT) characteristics. the parameters lifetime tHL. Because the current tail is the same in a paralleled configuration as for a single device. and Le2 are the inductances due to lead and power traces. the device with the higher lifetime can encounter thermal breakdown (for example. HIGH LIFETIME IC1 IC2 LOW LIFETIME VCE PARAMETER VARIATIONS In order to observe how the dissimilar parameters affect current sharing of the paralleled IGBTs. LOAD RL DC SUPPLY Ls1 RG1 Q1 Q2 Ls2 RG2 VGG Le1 Le2 DC RTN Figure 1. It is shown that if the designer considers careful circuit layout. No significant current spike is observed during the turn–off transition. and turn–off variations are observed. Le1. Because of this higher lifetime. The device with the higher lifetime conducted more current than the device with lower lifetime. It is shown that these parasitic components have a significant role in the operation of the IGBTs. Figure 2 shows a waveform of collector voltage and collector current of both device types. In this way the designer is better informed and will be able to better design for “key” parameters. and in order to truly understand the temperature effect on paralleling. Many of the papers written about parallel operations of IGBTs concern the effect of temperature variations. and for redundancy. Paralleled Operation of IGBTs with Lifetime Variation Temperature Effect on the Lifetime Variations.

using a separate heatsink will actually improve the dynamic current sharing for the IGBTs. During turn–off. and as a result. The turn–on delay occurs for the higher threshold voltage device because it takes longer for the gate voltage to charge up the gate–emitter capacitance to its threshold voltage. the threshold voltage of the IGBT will decrease with the increase in temperature. The turn–off current spike in the higher transconductance device occurs because the resistance of the lower transconductance device becomes larger sooner than for the high transconductance device. the BJT emitter–base voltage decreases with temperature due to the increase in intrinsic carrier concentration. the EFFECT OF GATE RESISTANCE If separate gate resistors are used for each device. VCE(on). USING COMMON HEATSINK With common heatsink. and as a result. Static current sharing is greatly improved in IGBTs because the lifetimes of the devices tend to increase proportionally to other devices with temperature. however. During the static operation. and the resultant waveform is shown in Figure 3. it will introduce a variation in delay time (or storage time). But if the current level is high enough. it will oscillate with large common–emitter inductance. With the interaction of parasitic capacitors and nonlinear voltage–dependent junction capacitance of the devices. Using a common heatsink will improve the static current sharing. Paralleled Operation of IGBTs with Kp and Vth Varied Temperature Dependency of Vth and Kp. a large current spike is observed by the lower inductance device because it turns on much faster than the other. Just as variation in transconductance will introduce turn–off current spike. the MOSFET effect will dominate and the device VCE(sat) will increase with temperature. However. but large dynamic instability can still be introduced if Kp and Vth variation is not minimized. the circuit layout is very important in the parallel operation of the devices. large variation in threshold voltage can cause dynamic current imbalance because one device will turn off faster than the other device. both of the parameters will be decreased. and the lower storage time device will transfer its current to the other MOTOROLA 15 . the device may fail due to excessive energy dissipated by the device at high temperature. However. one of the devices can be destroyed due to excessive current spike. and the current spike is independent of the temperature. At turn–off. The turn–off current spike introduced by variation in transconductance and threshold voltage can be detrimental to the device if its SOA has been exceeded. If the designer did not consider the temperature effect of the current tail. With an increase in temperature. the failure of the device in paralleled operation would be the same as in a single device operation. the device with higher transconductance will conduct most of the current because the MOSFET channel resistance dominates during switching. but because the IGBT has dual device characteristics. If one of the device’s emitter–ground inductance is large while the other device sees low inductance. Just as for the transconductance. the decrease in transconductance counterbalances the effect of the decrease in threshold voltage. and the device with the higher transconductance conducts more current because its on–resistance is lower than the other device. EFFECT OF CIRCUIT LAYOUT Just as in normal operation of the single device. Threshold Voltage and Transconductance Variation Threshold voltage and transconductance are MOSFET characteristics. The device with longer turn–off time will stay on longer. Not only does the threshold voltage cause the delay. Unless the parameters are significantly different. and the inductor current is transferred to the lower resistance device. This will be sensed by the other device. The static portion of the waveform shows a current imbalance. In fact. and thereby always keep the current–sharing well balanced. If the variation in transconductance is wide enough. Two devices with different MOSFET threshold voltages and transconductance were chosen. The decrease in BJT emitter–base voltage will negate the decrease in transconductance. the parameter variation in both devices will approximately be equal. and the energy loss. It was discussed earlier that the large emitter inductance introduces large voltage drop and results in clamping of the gate current during the turn–on. the threshold voltage will have no effect. This increase in on–resistance of the device will cause the other device to take more of the current. the dynamic turn–off current imbalance will not be improved significantly if the designer did not pay attention to the Vth and Kp. a current spike exists for the device with the larger transconductance and smaller threshold voltage. amount of current seen by the device will be changed very little or not at all.AN1540 of the device due to life time variation is the same as for single devices used in a scaled down circuit. the on–state voltage will tend to increase with temperature. but the lower transconductance will cause delay during the turn–on because the device resistance is higher than the other device until its gate voltage becomes large enough so that the on–state resistance of both devices are primarily determined by the bipolar emitter–base voltages. So more of the gate current is diverted to the device with lower common–emitter inductance. For a high–gate voltage. in a parallel operation. Large variation in common–emitter inductance has been shown to be the biggest contributor to the cause of dynamic current imbalance of the devices. unless a large quantity of the devices are paralleled for very high current levels. HIGH Kp/LOW Vth IC1 IC2 LOW Kp/HIGH Vth VCE Figure 3. and they will together oscillate out of phase with each other. static current sharing is well balanced from device to device.

or other applications intended to support or sustain life. Buyer shall indemnify and hold Motorola and its officers. pp. or authorized for use as components in systems intended for surgical implant into the body. 28. employees.. “Static and Dynamic Behavior of Paralleled IGBT’s.. Industry Applications. Minimize the spread of lifetime. “Temperature Behavior of Insulated Gate Transistor Characteristics. even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. careful circuit layout (minimizing parasitic inductance). 303. Rahul Chokhawala. Literature Distribution Centers: USA: Motorola Literature Distribution. 28 (1992). Should Buyer purchase or use Motorola products for any such unintended or unauthorized application. R. “Application Advantages Using IGBT Technology. including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. directly or indirectly. 30 (1993). Phoenix.T. Calculate the junction temperature using worst case numbers ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ REFERENCES [1] Hefner. 16 ◊ *AN1540/D* MOTOROLA AN1540/D . including without limitation consequential or incidental damages. Y. Use single gate resistors to drive the gates to reduce the storage time variations 5. EUROPE: Motorola Ltd. 2 Dai King Street. If careful attention has been given to the circuit layout. Motorola products are not designed. A. Hefner. JAPAN: Nippon Motorola Ltd. A. Take all the precautions just as if the devices were operating as single devices 4. England. Scott Deuty. Hong Kong.K. Its dual device characteristics can be utilized to give design engineers very satisfactory performance under static and dynamic current sharing of the devices. Vol. Motorola reserves the right to make changes without further notice to any products herein. In summary. Kp. pp. and reasonable attorney fees arising out of. Blakelands. J. pp. intended. Industry Applications. Dissertation (July 23. ASIA PACIFIC: Motorola Semiconductors H.. Japan. Motorola. Milton Keynes. the following criteria should be met for paralleling IGBTs: 1.” IEEE Trans. Vol. “Characterization and Modeling of the Power Insulated Gate Bipolar Transistor. A. [2] [3] Letor. representation or guarantee regarding the suitability of its products for any particular purpose. D. affiliates. SUMMARY Many of the problems associated with paralleling of power devices can be greatly reduced by using IGBTs..” IEEE Trans. Vol. ACKNOWLEDGMENTS The author wishes to thank the following people for their inputs and many interesting discussions: Steve Robb. or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. costs. IXYS Corporation Hefner. and using common heatsinks.. (1989). “A Dynamic Electro–Thermal Model for the IGBT. Remember that using a common heatsink does not improve the dynamic current imbalance if parameter variations of Kp and Vth are large. and expenses.. Motorola makes no warranty. 395–402. Chuck. C. N. Chen. C. and distributors harmless against all claims. F. Tokyo 141. S. MK14 5BP. using a single–gate resistor for both devices will reduce the turn–off storage time variation because the device with higher storage time will keep the other device conducting to a value which is dependent on the device transconductance. [4] Rinehart. any claim of personal injury or death associated with such unintended or unauthorized use.” IEEE Trans. Inc. R. 17–18. R. It has been shown that the device characteristics of the IGBT device favors parallel operation as opposed to BJTs. (1985). Tai Po Industrial Estate.” App Note. Shinagawa-ku.. Romeo.AN1540 device. Hefner for many long and interesting telephone conversations which have been so valuable to the materials in this paper. [5] [6] Hefner. Problems associated with paralleling IGBTs can be minimized and deterred if careful attention is given to parameter variations. 30 (1994). A. Vol. damages. 1987). Ltd. and specifically disclaims any and all liability. and Vth between the devices to be paralleled 2. Silicon Harbour Center.” PhD. “Insulated Gate Bipolar Transistor (IGBT) Modeling Using IG–Spice. and Lee. is an Equal Opportunity/Affirmative Action Employer. Kim Gauen. pp. Inc.” Solid State Electronics. pp. Baliga. Most of the failure of the devices in paralleled operation can be contributed to neglect of device temperature effect and not derating the parts as they should have. Arizona 85036. All operating parameters. and special thanks to A. “Typical” parameters can and do vary in different applications.. Use a common heatsink for all of the devices 6. nor does Motorola assume any liability arising out of the application or use of any product or circuit. P. B. R. Static current sharing is increased with the use of common heatsink. Minimize the common–emitter inductance difference 3. 24–33. This will introduce more power dissipation in one device and introduce thermal instability if separate heat sinks are used. Bill Fragale. Larry and Heron. Nishi-Gotanda. Box 20912. 4-32-1.O. “An Improved Understanding for the Transient Operation of the Power Insulated Gate Bipolar Transistor (IGBT). and common–emitter inductance has been minimized. European Literature Centre. Rodrigo Borras. [7] Mitter. Understand which characteristics will dominate the parallel operation (BJT or MOSFET) 7. No. 3. R. Tai Po. 289–297. 88 Tanners Drive. 394–405.” IEEE Power Electronics Specialists Conf. subsidiaries. pp. Motorola and are registered trademarks of Motorola. no.

and approach the desired ideal switch. drive circuitry. semiconductor manufacturers need to create products that approach the ideal switch. the conduction loss of the device is decreased. the IGBT is faster. therefore. The IGBT is. IGBTs are replacing MOSFETs in high voltage applications where conduction losses must be kept low. © MOTOROLA Motorola. INTRODUCTION As power conversion relies more on switched applications. IGBTs. in fact. turn–off of the IGBT is slower than a MOSFET. RDS(on). no significant reduction in the RDS(on) is foreseen. the reduced silicon area makes the IGBT the lower cost solution. the change to IGBTs can be made without having to redesign the gate drive circuit. Figure 1c shows the resulting package area reduction realized by using the IGBT. Since the cell density. The IGBT curve has an offset due to an internal forward biased p–n junction and a fast rising slope typical of a minority carrier device. In high voltage applications. Device cost is related to silicon area. has better gate turn–off capability. As shown in Figure 1a. The gradual rising slope of the MOSFET in Figure 1a can be attributed to the relationship of VDS to RDS(on). In a power MOSFET. 1995 1 . 3) switch with infinite speed. As shown in Figure 1b. Compared to thyristors.” The tailing restricts the devices to operating at moderate frequencies (less than 50 kHz) in traditional “square waveform” PWM. whereas turning off an IGBT only requires that the gate capacitance be discharged. By reducing the forward drop. IGBTs exhibit an on–voltage and current density comparable to a bipolar transistor while switching much faster. Inc. 2) infinite resistance in the off–state. above all. like MOSFETs. all have strong and weak points. the designer must deviate from the ideal switch and choose a device that best suits the application with a minimal loss of efficiency. IGBTs offer an attractive solution over the traditional bipolar transistors. simple drive requirements and low conduction loss. the on–resistance is proportional to the breakdown voltage raised to approximately the 2. MOSFETs and thyristors. The ideal switch would have: 1) zero resistance or forward voltage drop in the on–state.7 power (1). MOSFETs are often used because of their simple gate drive requirements. MOSFETs exhibit increased RDS(on) resulting in lower efficiency due to increased conduction losses. switching applications. and 4) would not require any input power to make it switch. the IGBT can be operated in the hundreds of kilohertz range [1]. has better dv/dt immunity and. For low voltage applications. using an IGBT in place of a power MOSFET dramatically reduces the forward voltage drop at current levels above 12 amps. When using existing solid–state switch technologies. It is possible to replace the MOSFET with an IGBT and improve the efficiency and/or reduce the cost. With zero current switching or resonant switching techniques. Since the structure of both devices are so similar. The IGBT exhibits a current fall time or “tailing. MOSFET technology has advanced to a point where cell densities are limited by manufacturing equipment capabilities and geometries have been optimized to a point where the RDS(on) is near the predicted theoretical limit. a spin–off from power MOSFET technology and the structure of an IGBT closely resembles that of a power MOSFET. The choice involves considerations such as voltage. At operating frequencies between 1 and 50 kHz. an IGBT has considerably less silicon area than a similarly rated MOSFET. power MOSFETs offer extremely low on–resistance. While some thyristors such as GTOs are capable of being turned off at the gate. The IGBT has high input impedance and fast turn–on speed like a MOSFET. There are a variety of solid state switch technologies available to perform switching functions. current. switching speed. substantial reverse gate current is required. geometry and the resistivity of the device structure play a major role. HIGH VOLTAGE POWER MOSFETs The primary characteristics that are most desirable in a solid–state switch are fast switching speed. R DS(on) 2. A thyristor has a slightly lower forward–on voltage and higher surge capability than an IGBT. load.MOTOROLA SEMICONDUCTOR APPLICATION NOTE Order this document by AN1541/D AN1541 Introduction to Insulated Gate Bipolar Transistors Prepared by: Jack Takesuye and Scott Deuty Motorola Inc. The IGBT is more space efficient than an equivalently rated MOSFET which makes it perfect for space conscious designs. and temperature effects. are transconductance devices and can remain fully on by keeping the gate voltage above a certain threshold.7 T VDSS (1) ENTER THE IGBT By combining the low conduction loss of a BJT with the switching speed of a power MOSFET an optimal solid state switch would exist. Although turn–on speeds are very fast. however. New technologies are needed to circumvent the problem of increased on–resistance without sacrificing switching speed. The Insulated–Gate Bipolar Transistor (IGBT) technology offers a combination of these attributes.

just the opposite would be true and the device would be made faster and have greater conduction losses.05 0 Figure 1b.17 X 0.9 1. IGBTs have similar ratings in terms of voltage and current. some trade–offs in conduction loss versus switching speed exist. Since the initial introduction of IGBTs in the early 1980s. Thus far. INCHES) Figure 1a.8 0. tf of newer generation devices.6 0.26) 1 AREA (SQ.10 0. semiconductor manufacturers have learned how to make the devices faster.40 0.5 1. Reduced Die Size of IGBT Realized When Compared to a MOSFET with Similar Ratings 0.60 Ç ÉÉÉÉÉÉ Ç ÉÉÉÉÉÉ É ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÇÇÇÇÇÇ ÉÉÉÉÉÉ ÇÇÇÇÇÇ ÉÉÉÉÉÉ ÇÇÇÇÇÇ ÉÉÉÉÉÉ ÇÇÇÇÇÇ ÉÉÉÉÉÉ IGBT DIE SIZE (0. INCHES) 0. In a higher frequency application.0 1. Ç ÉÉÉÉÉÉ Ç ÉÉÉÉÉÉ É ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÇÇÇÇÇÇ ÉÉÉÉÉÉ ÇÇÇÇÇÇ ÉÉÉÉÉÉ ÇÇÇÇÇÇ ÉÉÉÉÉÉ ÇÇÇÇÇÇ ÉÉÉÉÉÉ IGBT PACKAGE SIZE (TO–220) MOSFET PACKAGE SIZE (T0–247) 1 1ST GENERATION COMPETITOR 1985 2ND GENERATION COMPETITOR 1989 1ST GENERATION MOTOROLA 1993 3RD GENERATION COMPETITOR 1993 2ND GENERATION MOTOROLA DEMONSTRATED LOW SATURATION SERIES 0.5 3.3 0.7 0. 3.2 0. As illustrated in Figure 2. BJTs require that base current be continuously supplied in a quantity sufficient enough to maintain saturation.5 tf (µs) 0. BJT drive circuits must be sensitive to variable load conditions. the IGBT has demonstrated certain advantages over power MOSFETs with the exception of switching speed. the presence of an isolated gate in an IGBT makes it simpler to drive than a BJT.1 0. Advanced Features Offered by the Latest Motorola IGBT Technologies for Forward Voltage Drop (VCE(sat)) and Fall Time (tf) 2 MOTOROLA . However.AN1541 PEAK CURRENT THROUGH DEVICE (AMPS) 40 35 30 25 20 15 10 5 0 0 2 4 6 FORWARD DROP (VOLTS) 8 10 VDS MTW20N50E MOSFET VCE(sat) MGW20N60D IGBT AREA (SQ. power supplies and inverters that require devices rated for 600 to 1200 volts.20 0 Figure 1c.35 X 0.0 VCE(sat) (VOLTS) 2. BJTs are minority carrier devices and charge storage effects including recombination slow the performance when compared to majority carrier devices such as MOSFETs.5 2.0 Figure 2.4 0.0 0. Base currents of one–tenth of the collector current are typical to keep a BJT in saturation. Notice that the curves in Figure 2 show reductions in both the forward drop (VCE(sat)) and the fall time. Reduced Package Size of IGBT Realized When Compared to a MOSFET with Similar Ratings Because the loss period is a small percentage of the total on time.5 0 0 HIGH SPEED SERIES 0. slower switching is traded for lower conduction loss. IGBTs also experience recombination that accounts for the current “tailing” yet IGBTs have been observed to switch faster than BJTs. The base current of a BJT must be kept proportional to the collector current to prevent desaturation under high–current loads and excessive base drive under low–load conditions. Reduced Forward Voltage Drop of IGBT Realized When Compared to a MOSFET with Similar Ratings When compared to BJTs.227) MOSFET DIE SIZE (0. Lower frequency applications can tolerate slower switching devices. This additional base current increases the power dissipation of the drive circuit. These capabilities make the IGBT the device of choice for applications such as motor drives.

The substrate for an IGBT is P+ as shown in Figure 3a. these carriers do not have a current path to exit the device.7 T VDSS (1) To increase the breakdown voltage of the MOSFET. The solution to this came in the form of conductivity modulation. The n– epi region to this was placed on the P+ substrate forming a p–n junction where conductivity modulation takes place. One difference between a MOSFET and an IGBT is the substrate of the starting material. Because of conductivity modulation. reducing the RDS(on) of a high voltage device requires greater silicon area A to make up for the increased n– epi region. Now the P+ substrate. Additional benefits of the N+ buffer layer include preventing thermal runaway and punch–through of the depletion region. R DS(on) 2. Cross Section and Equivalent Schematic of an Metal–Oxide–Semiconductor Field–Effect Transistor (MOSFET) Cell Figure 4b. While the N+ buffer layer may speed up the recombination. the n– epi region thickness (vertical direction in figure) is increased. The subject of current tailing has been mentioned several times. Minority carriers build up to form the basis for conductivity modulation. n– epi layer and P+ “emitter” form a BJT transistor and the n– epi acts as a wide base region. Thus far. Cross Section and Equivalent Schematic of an Insulated Gate Bipolar Transistor (IGBT) Cell GATE SOURCE KEY METAL SiO2 POLYSILICON GATE N+ P– Device designers were challenged to overcome the effects of the high resistive n– epi region. IGBT Schematic Symbol N+ SUBSTRATE DRAIN DRAIN GATE SOURCE Figure 3b. By varying the starting material and altering certain process steps. however. at Motorola mask sets are designed specifically for IGBTs. This allows a thinner n– epi to be used which somewhat decreases forward voltage drop. As depicted in the classical resistance relationship (2). an IGBT may be produced from a power MOSFET mask. When the device turns off. the device structure as shown in Figure 3 provides insight as to what causes the tailing. The n– epi resistivity determines the breakdown voltage of a MOSFET as mentioned earlier using relationship (1). Recombination is the only way to eliminate the stored charge resulting from the build–up of excess carriers. it also increases the forward drop of the device.AN1541 CHARACTERISTICS OF IGBTs: DEVICE STRUCTURE The structure of an IGBT is similar to that of a double diffused (DMOS) power MOSFET. Hence the tradeoff between switching speed and conduction loss becomes a factor in optimizing device performance. In a MOSFET the substrate is N+ as shown in Figure 3b. the IGBT has a much greater current density than a power MOSFET and the forward voltage drop is reduced. COLLECTOR JFET channel N+ P+ NPN P+ GATE Drain–to–Source Body Diode (Created when NPN base–emitter is properly shorted by source metal) N– EPI EMITTER Figure 4a. R 1 TA (2) GATE EMITTER KEY METAL SiO2 POLYSILICON GATE N+ P– N+ P+ P– P+ Rshorting NPN MOSFET Rmod PNP N– EPI N+ BUFFER P+ SUBSTRATE COLLECTOR Figure 3a. MOSFET Schematic Symbol MOTOROLA 3 . Additional recombination centers are formed by placing an N+ buffer layer between the n– epi and P+ substrate.

When the gate is initially brought below the threshold voltage. Device processing directs currents within the device and keeps the voltage across Rshorting low to avoid latching. choose an optimal device based on switching speed or use a slower device with lower forward drop and employ external circuitry to enhance turn off. Therefore. the forward drop of an IGBT stays relatively unchanged at increased temperatures. The IGBT can be gated off unlike the SCR which has to wait for the current to cease allowing recombination to take place in order to turn off. an IGBT is designed so that it does not latch on. Current flowing through Rshorting can result in a voltage across the base–emitter junction of the NPN. switching speed and achieve other key parametric variations. 2 IGBT #2 in 1. If the base–emitter voltage is above a certain threshold level. Switching Speed Until recently. This drop is similar to that seen in a forward biased p–n junction diode and results in an offset voltage in the output characteristic. This is a disadvantage to motor control designers who use the anti–parallel diode to recover energy from the motor. it does not have the inverse parallel diode inherent to power MOSFETs. This structure resembles that of a thyristor device known as a Silicon Controlled Rectifier (SCR). 4 MOTOROLA . Efforts to minimize gate drive impedance for IGBTs are also recommended. The IGBT has a high input impedance due to the isolated gate and it exhibits the accompanying advantages of modest gate drive requirements and excellent gate drive efficiency. TAIL TIME of MOTOROLA GEN. IGBTs offer an advantage over the SCR by controlling the current with the device. the n– epi contains a very large concentration of electrons and there will be significant injection into the P+ substrate and a corresponding hole injection into the n– epi. the N+ buffer layer is highly doped for recombination and speedy turn off. Rshorting is the parasitic resistance of the P+ emitter region. and a recombination phase in which the collector current decrease more slowly. the stored charges can only be dissipated through recombination. process steps are optimized to control the geometry. Current flowing from collector to emitter must pass through a p–n junction formed by the P+ substrate and n– epi layer. Notice that the IGBT has a gate like a MOSFET yet it has an emitter and a collector like a BJT. Also. the NPN will begin to conduct causing the NPN and PNP to enhance each other’s current flow and both devices can become saturated.0 hp MOTOR DRIVE at 1750 RPM 6 5 I C (AMPS) 4 3 2 1 0 –1 0 200 TAIL TIME ÇÇ ÉÉÉÉ ÇÇ ÉÉÉÉ ÇÇ ÉÉÉÉ ÇÇ ÉÉÉÉ ÇÇ ÉÉÉÉ ÇÇ 400 600 MOSFET TURN–OFF PORTION PNP TURN–OFF PORTION 800 1000 Figure 5. The turn–off time of an IGBT is slow because many minority carriers are stored in the n– epi region. The additional doping keeps the gain of the PNP low and allows two–thirds of the current to flow through the base of the PNP (electron current) while one–third passes through the collector (hole current). While turn–on is fairly rapid. the electron injection decreases. For a fast device. the gate of the IGBT is electrically isolated from the rest of the chip by a thin layer of silicon dioxide. Current flow contributions are shown in Figure 3a using varying line thickness with the thicker lines indicating a high current path. A turn–off mechanism is suggested in a paper by Baliga et al [2]. leaving the rest of the electrons to recombine. Unlike the SCR where the device latches and gate control is lost. the turn–off of an IGBT has two phases: an injection phase where the collector current falls very quickly. The operation of the IGBT is best understood by again referring to the cross section of the device and its equivalent circuit as shown in Figure 3a. initial IGBTs had current fall times of around three microseconds. This results in the device latching in a fashion similar to an SCR. SiO2. As the electron concentration in the n–region decreases. Unlike the MOSFET where increased temperature results in increased RDS(on) and increased forward voltage drop. Like a power MOSFET. The possibility of latching is also reduced by strategic processing of the device. The internal MOSFET of the IGBT when gated off will stop current flow and at that point. To maximize the performance of the IGBT. IGBT Current Turn–off Waveform In power MOSFETs. Figure 5 shows the switching waveform and the tail time contributing factors of a “fast” IGBT designed for PWM motor control service. Equivalent Circuit of IGBT Figure 4b shows the terminals of the IGBT as determined by JEDEC. The IGBT’s on–voltage is represented by sum of the offset voltage of the collector to base junction of the PNP transistor. not the device with the current. Geometry and doping levels are optimized to minimize the on–voltage. Full control of the device can be maintained through the gate drive. the voltage drop across the modulated resistance Rmod and the channel resistance of the internal MOSFET. doping and lifetime.AN1541 The IGBT has a four layer (P–N–P–N) structure. the feature that limited the IGBT from serving a wide variety of applications was its relatively slow turn–off speed when compared to a power MOSFET. the switching speed can be greatly affected by the impedance in the gate drive circuit. Because the IGBT is a four–layer structure.

The conduction losses of BJTs and IGBTs is related to the forward voltage drop of the device while MOSFETs determine conduction loss based on RDS(on). To get a relative comparison of turn–off time and conduction associated losses, data is presented in Table 1 where the on–resistances of a power MOSFET, an IGBT and a BJT at junction temperatures of 25°C and 150°C are shown. Note that the devices in Table 1 have approximately the same ratings. However, to achieve these ratings the chip size of the devices vary significantly. The bipolar transistor requires 1.2 times more silicon area than the IGBT and the MOSFET requires 2.2 times the area of the IGBT to achieve the same ratings. This differences in die area directly impacts the cost of the product. At higher currents and at elevated temperatures, the IGBT offers low forward drop and a switching time similar to the BJT without the drive difficulties. Table 1 confirms the findings offered earlier in Figure 1a and elaborates further to include a BJT comparison and temperature effects. The reduced power conduction losses offered by the IGBT lower power dissipation and heat sink size. Thermal Resistance An IGBT and power MOSFET produced from the same size die have similar junction–to–case thermal resistance because of their similar structures. The thermal resistance of a power MOSFET can be determined by testing for variations in temperature sensitive parameters (TSPs). These parameters are the source–to–drain diode on–voltage, the gate–to–source threshold voltage, and the drain–to–source on–resistance. All previous measurements of thermal resistance of power MOSFETs at Motorola were performed using the source–to–drain diode as the TSP. Since an IGBT does not have an inverse parallel diode, another TSP had to be used to determine the thermal resistance. The gate–to–emitter threshold voltage was used as the TSP to measure the junction temperature of an IGBT to determine its thermal resistance. However before testing IGBTs, a correlation between the two test methods was established by comparing the test results of MOSFETs using both TSPs. By testing for variations in threshold voltage, it was determined that the thermal resistance of MOSFETs and IGBTs are essentially the same for devices with equivalent die size . Short Circuit Rated Devices Using IGBTs in motor control environments requires the device to withstand short circuit current for a given period. Although this period varies with the application, a typical value of ten microseconds is used for designing these specialized IGBT’s. Notice that this is only a typical value and it is suggested that the reader confirm the value given on the data sheet. IGBTs can be made to withstand short circuit conditions by altering the device structure to include an additional resistance (Re, in Figure 6) in the main current path. The benefits associated with the additional series resistance are twofold.




N+ P+

R P+ shorting







Figure 6. Cross Section and Equivalent Schematic of a Short Circuit Rated Insulated Gate Bipolar Transistor Cell First, the voltage created across Re, by the large current passing through Re, increases the percentage of the gate voltage across Re, by the classic voltage divider equation. Assuming the drive voltage applied to the gate–to–emitter remains the same, the voltage actually applied across the gate–to–source portion of the device is now lower, and the device is operating in an area of the transconductance curve that reduces the gain and it will pass less current.

Characteristic TMOS 20 A IGBT 20 A Bipolar 20 A Current Rating Voltage Rating 500 V 0.2 Ω 0.6 Ω 600 V 500 V* 0.18 Ω R(on) @ TJ = 25°C 0.24 Ω 0.23 Ω R(on) @ TJ = 150°C Fall Time (Typical) 0.24 Ω** 200 ns 40 ns 200 ns * Indicates VCEO Rating ** BJT TJ = 100°C

Table 1. Advantages Offered by the IGBT When Comparing the MOSFET, IGBT and Bipolar Transistor On–Resistances (Over Junction Temperature) and Fall Times (Resistance Values at 10 Amps of Current)



Second, the voltage developed across Re results in a similar division of voltage across Rshorting and VBE of the NPN transistor. The NPN will be less likely to attain a VBE high enough to turn the device on and cause a latch–up situation. The two situations described work together to protect the device from catastrophic failure. The protection period is specified with the device ratings, allowing circuit designers the time needed to detect a fault and shut off the device. The introduction of the series resistance Re also results in additional power loss in the device by slightly elevating the forward drop of the device. However, the magnitude of short circuit current is large enough to require a very low Re value. The additional conduction loss of the device due to the presence of Re is not excessive when comparing a short circuit rated IGBT to a non–short circuit rated device. Anti–Parallel Diode When using IGBT’s for motor control, designers have to place a diode in anti–parallel across the device in order to handle the regenerative or inductive currents of the motor. As discussed earlier, due to structural differences the IGBT does not have a parasitic diode like that found in a MOSFET. Designers found that the diode within the MOSFET was, in fact, a parasitic, i.e., not optimized in the design process, and its performance was poor for use as a current recovery device due to slow switching speed. To overcome the lack of performance, an optimized anti–parallel diode was used across the MOSFET source–to–drain. Placing a packaged diode external to the MOSFET itself created performance problems due to the switching delays resulting from the parasitics introduced by the packages. The optimal setup is to have the diode copackaged with the device. A specific line of IGBTs has been created by Motorola to address this issue. These devices work very well in applications where energy is recovered to the source and are favored by motor control designers. Like the switching device itself, the anti–parallel diode should exhibit low leakage current, low forward voltage drop and fast switching speed. As shown in Figure 7, the diode forward drop multiplied by the average current it passes is the total conduction loss produced. In addition, large reverse recovery currents can escalate switching losses. A detailed explanation of reverse recovery can be found in the Appendix. A secondary effect caused by large reverse recovery currents is generated EMI at both the switching frequency and the frequency of the resulting ringing waveform. This EMI requires additional filtering to be designed into the circuit. By copackaging parts, the parasitic inductances that contribute to the ringing are greatly reduced. Also, copackaged products can be used in designs to reduce power dissipation and increase design efficiency.




Figure 7. Waveforms Associated with Anti–Parallel Diode Turn–off

Line–operated, pulse–width modulated, variable–speed motor drives are an application well suited for IGBTs. In this application, as shown in Figure 8, IGBTs are used as the power switch to PWM the voltage supplied to a motor to control its speed. Depending on the application, the IGBT may be required to operate from a full–wave rectified line. This can require devices to have six hundred volt ratings for 230 VAC line voltage inputs, and twelve hundred volt ratings for 575 VAC volt line inputs. IGBTs that block high voltage offer fast switching and low conduction losses, and allow for the design of efficient, high frequency drives of this type. Devices used in motor drive applications must be robust and capable of withstanding faults long enough for a protection scheme to be activated. Short circuit rated devices offer safe, reliable motor drive operation.

The IGBT is a one of several options for designers to choose from for power control in switching applications. The features of the IGBT such as high voltage capability, low on–resistance, ease of drive and relatively fast switching speeds makes it a technology of choice for moderate speed, high voltage applications. New generations of devices will reduce the on–resistance, increase speed and include levels of integration that simplify protection schemes and device drive requirements. The reliability and performance advantages of IGBTs are value added traits that offer circuit designers energy efficient options at reduced costs.













Figure 8. Typical Pulse–Width, Modulated, Variable–Speed Induction Motor Drives Are Where IGBT’s Offer Performance Advantages

The writing of this document was assisted by a number of internal device designers. Their assistance was greatly appreciated by the authors. Bill Fragale, Steve Robb and Vasudev Venkatesan provided device operation insight and reference materials. Graphic material was provided by Basam Almesfer and Steve Robb. Finally, C. S. Mitter assisted with editing and accuracy of the material.

[1] D. Y. Chen, J. Yang, and J. Lee “Application of the IGT/COMFET to Zero–Current Switching Resonant Converters,” PESC, 1987. [2] B. J. Baliga, “Analysis of Insulated Gate Transistor Turn–off Characteristics,” IEEE Electron Device Lett. EDL–6, (1985), pp. 74–77 . [3] B. J. Baliga, “Switching Speed Enhancement in Insulated Gate Transistors by Electron Irradiation,” IEEE Transactions on Electron Devices, ED–31, (1984), pp. 1790–1795.



is an Equal Opportunity/Affirmative Action Employer. even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. 1–800–441–2447 MFAX: RMFAX0@email. costs. and reasonable attorney fees arising out of. intended. 3–14–2 Tatsumi Koto–Ku. Toshikatsu Otsuki. or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Reverse Recovery Waveform Motorola reserves the right to make changes without further notice to any products herein. (Phoenix: Motorola. any claim of personal injury or death associated with such unintended or unauthorized use. The ta time is a function of the forward current and the applied di/dt. Inc. DL135. This does not give enough information to fully characterize the waveform shape. as shown in Figure A–1. Box 20912. load inductance and the applied reverse voltage.5) and ultrafast rectifiers are very abrupt (softness factor of about 0. A relative softness can be defined as the ratio of tb to ta. including without limitation consequential or incidental damages. subsidiaries. Measured tb times vary greatly with the switch characteristic. pp.. How to reach us: USA / EUROPE: Motorola Literature Distribution. Inc. 2–9–22 to 2–9–23. 8B Tai Ping Industrial Park. damages. or authorized for use as components in systems intended for surgical implant into the body. Motorola does not convey any license under its patent rights nor the rights of others. [4] Source: “Motor Controls. P. Q4/92. 852–26629298 8 ◊ *AN1541/D* MOTOROLA AN1541/D . Phoenix. The tb portion of the reverse recovery current is not very well understood.K.sps. Ltd. Motorola makes no warranty. and specifically disclaims any and all liability. N. 03–3521–8315 HONG KONG: Motorola Semiconductors H.T. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application. 6F Seibu–Butsuryu–Center. A better way to characterize the rectifier reverse recovery is to partition the reverse recovery time into two different regions. 51 Ting Kok Road. or other applications intended to support or sustain life. Arizona 85036. Inc. including “Typicals” must be validated for each customer application by customer’s technical – TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET. and expenses.. Motorola. nor does Motorola assume any liability arising out of the application or use of any product or circuit. trr = ta = tb = IRM(rec) = total reverse recovery time fall time due to stored minority charge application and device dependent peak reverse recovery current Figure A–1. Hong Kong.AN1541 APPENDIX Diode Reverse Recovery Analysis [4] di/dt IF IRM(rec) ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ Qa Qb ta tb trr A typical reverse recovery waveform is shown in Figure A–1. fast recovery diodes are fairly soft (softness factor of about 0. and distributors harmless against all claims.mot. Tai Po. General purpose rectifiers are very soft (softness factor of about 1.” TMOS Power MOSFET Transistor Data.O. Rev 4.2). All operating parameters. Motorola and are registered trademarks of Motorola. circuit parasitics. representation or guarantee regarding the suitability of its products for any particular purpose. Japan. The reverse recovery time trr has been traditionally defined as the time from diode current zero–crossing to where the current returns to within 10% of the peak recovery current IRM(rec). Buyer shall indemnify and hold Motorola and its officers. Motorola products are not designed. the area under the curve.. “Typical” parameters can and do vary in different applications. directly or indirectly. 1992). employees.0). Tokyo 135. ta and tb. A charge can be assigned to this region denoted Qa. Tatsumi–SPD– JAPAN: Nippon Motorola Ltd. affiliates..

wide SOA. IGBTs on the other hand. as detailed in INT-990 Sec VIII. as the voltage rating goes up. Generally speaking. In spite of its similarity to the cross-section of a power MOSFET. ease of drive. being minority carrier devices. GATE POLYSILICON OXIDE EMITTER N+ PP+ rb N. current requirement. while sharing many of the appealing features of power MOSFETs such as ease of drive. operation of the two transistors is fundamentally different. HOW THE IGBT COMPLEMENTS THE POWER MOSFET Switching speed. are partly mitigated by their conduction characteristics which are strongly dependent on temperature and voltage rating. The lack of an integral diode can be an advantage or a disadvantage. etc. cost of diodes.EPI N+ BUFFER LAYER G P+ SUBSTRATE COLLECTOR (a) DEVICE STRUCTURE E EMITTER rb N+ C COLLECTOR rb (b) Device Symbol (c) EQUIVALENT CIRCUIT Figure 1. depending on the frequency of operation. the IGBT being a minority carrier device. enhancement mode). However. . These advantages. without sacrificing the much superior conduction characteristics. The terminal called collector is. actually. avalanche and dv/dt capability have made power MOSFETs the logical choice in new power electronic designs. have superior conduction characteristics.Int) (HEXFET® is a trademark of International Rectifier) IGBT Characteristics Topics covered: How the IGBT complements the MOSFET Silicon structure and equivalent circuit Conduction characteristics and “switchback” Switching characteristics Latching Safe Operating Area Transconductance How to read the data sheet Families of IGBTs 1. The absence of the integral reverse diode gives the user the flexibility of choosing an external fast recovery diode to match a specific requirement or to purchase a “co-pak”. the emitter of the PNP. the switching speed of an IGBT is inferior to that of power MOSFETs. peak current capability. a new line of IGBTs from International Rectifier has switching characteristics that are very close to those of power MOSFETs. the inherent reverse diode displays increasing Qrr and Trr which leads to increasing switching losses. Furthermore.AN-983 (v. wide SOA. an IGBT and a diode in the same package. i. a natural consequence of being majority carrier devices. Silicon cross-section of an IGBT with its equivalent circuit and symbol (N-Channel. peak current capability and ruggedness.e.

very significant in a power MOSFET. 2. is positive. As the final stage of a pseudo-Darlington. that the emitter of an IGBT covers the entire area of the die. SILICON STRUCTURE AND EQUIVALENT CIRCUIT Except for the P+ substrate. As explained later. hence its injection efficiency and conduction drop are much superior to that of a bipolar transistor of the same size. the on-state voltage drop across an IGBT never goes below a diode threshold. this option is limited by latch-up considerations and voltage withstanding capability. the IGBT consists of a PNP driven by an N-Channel MOSFET in a pseudoDarlington configuration. This is due to the fact that. This is due to the P+ substrate which is responsible for the minority carrier injection into the N-region and the resulting conductivity modulation. the gain of the PNP increases with current and an increase in gate voltage causes an increase in channel current. This can be done by increasing the die size and/or the cell density. Thus. CONDUCTION CHARACTERISTICS As it is apparent from the equivalent circuit. The MOSFET component. The cell density of the MOSFET structure is higher than that of a high-voltage. Two options are available to the device designer to decrease the conduction drop: 1. the PNP is never in heavy saturation and its voltage drop is higher than what could be obtained from the same PNP in heavy saturation. low voltage drop and efficient silicon utilization. on the other hand. on the other hand. within its operating range. It should be noted. a significant share of the conduction losses occur in the N-region. The breakdown voltage of this junction is about 20V and is shown in the IGBT symbol as an unconnected terminal (Figure 1). have concentrated on the optimization of the bipolar part and the resulting product should be more correctly referred to as a "MOSFET-driven transistor" with a different set of characteristics. The problem is made more complex by the fact that these two components are weighted differently at different current and temperatures. the silicon cross-section of an IGBT (Figure 1) is virtually identical to that of a power MOSFET. In a power MOSFET. International Rectifier has been pursuing the optimization of the MOSFET component of the IGBT to the point where its devices can be correctly referred to as a "conductivity modulated MOSFET" with its characteristic features of high speed. is minimal in an IGBT. 3. the voltage drop across the IGBT is the sum of two components: a diode drop across the P-N junction and the voltage drop across the driving MOSFET. for currents that are close to their rated value. typically 70% in a 500V device. unlike the power MOSFET. however. This same figure shows that the temperature dependence of the voltage drops is different at different current levels. Temperature dependence. . consequently. The voltage drop across the driving MOSFET. has one characteristic that is typical of all low voltage MOSFETs: it is sensitive to gate drive voltage. an increase in gate voltage causes a reduction in collector-to-emitter voltage. as shown in Figure 14 for the IRGBC20U. The base region of the PNP is not brought out and the emitter-base PN junction. However. This is apparent from Figures 12 and 13 where. has better Resistance-Area product.AN-983 (v. which does not benefit from conductivity modulation.type material under the P wells is sized in thickness and resistivity to sustain the full voltage rating of the device. As shown in the equivalent circuit of Figure 1. on the other hand. The JFET has been included in the equivalent circuit to represent the contriction in the flow of curr ent between adjacent P-wells. spanning the entire extension of the wafer cannot be terminated nor passivated. in spite of the many similarities. the physical operation of the IGBT is closer to that of a bipolar transistor than to that of a power MOSFET. This is because the diode component of this drop has a temperature coefficient that is initially negative becoming positive at higher current levels. Other semiconductor companies. comparable technology MOSFET and.Int) 2. In both devices the N. just enough to ensure current sharing of paralleled devices at high current levels under steady state conditions. Increase the gain of the PNP. Both devices share a similar polysilicon gate structure and P wells with N+ source contacts. Reduce the on-resistance of the MOSFET. This is quite different from the behavior of a high voltage power MOSFET that is largely insensitive to gate voltage. as will be explained later. hence a reduction in voltage drop across the PNP. The dramatic impact of conductivity modulation on voltage drop can be seen from Figure 2 which compares a HEXFET® power MOSFET and an IGBT of the same die size. This influences the turn-off and reverse blocking behavior of the IGBT.

after conductivity modulation is established. it has no storage time and its turn-off time is much faster than the same PNP in heavy saturation.. On-state voltage drop as temperature of drop at low current and low temperature is higher than two IGBTs of different switching characteristics expected. levels below conductivity modulation is higher than for a somewhat higher collector current. on account of their resistive 1 20 30 50 70 90 110 130 150 voltage drop. The voltage drop of a conductivity modulated device with minority lifetime killing may exhibit a peculiar JUNCTION TEMPERATURE (0C) behavior frequently referred to as ‘switchback’: the voltage Figure 2. though. The term comes from the fact that.7 1200 1000 3.6. i. the correct value would be ≈ 1.1 100 Typical Voltage Drop 2 @ 1.5 2. the on-resistance increases with the voltage rating at a 5 higher rate than a square law. assuming that a power law is a true representation of the underlying physical phenomena. the voltage drop for current IGBTs. α 50 40 10A 30 40 IRF8 20 ON-STATE VOLTAGE DROP (VOLTS) 10 7 i. because of higher levels of lifetime killing. Rated Voltage IGBT HEXFET® IGBT HEXFET® 100 100 1. A trace of this phenomenon can be seen in the “bump” in the VCE(Sat) portion of Figure 12. Notice that the bump disappears in Figure 13 because temperature increases the lifetime of the charges and speeds up the onset of conductivity modulation.4 26. Notice. where the conduction drops of four IGBTs of different voltage ratings are compared with those of HEXFET®s at the same current density. a 500V device is compared with 600V conductivity modulation. In actual fact they achieve their highest power handling IRGBC40S capability per unit area between 400V and 600V. These data sheets will also contradict the common misconception that IRGBC40U 2 power MOSFETs have better silicon utilization at low voltage. even if they are unbeatable at low voltages. when measuring voltage drop with a curve tracer. also. A common misconception is that power MOSFETs exhibit a voltage dependence of the RDS(on) of the following type: R = RO V with α = 2.7A/mm .epi. conductivity modulation virtually eliminates its dependence on the voltage rating. that since the PNP is in a pseudo-Darlington connection. Hence. it may still be inadequate for many high frequency applications. This behavior is ascribed to lifetime killing which. the avalanche capability of the HEXFET into in so far as it facilitates recombination. external drive circuitry cannot be used to improve the switching time. This is shown in Table I.Int) In addition to reducing the voltage drop and its temperature coefficient. . Even so.e.AN-983 (v. SWITCHING CHARACTERISTICS The biggest limitation to the turn-off speed of an IGBT is the lifetime of the minority carriers in the N. suddenly dropping to its expected value if current or compared to those of a HEXFET of the same die temperature are increased. the trace Conductivity modulation causes a dramatic suddenly ‘switches’ to the left of the screen as the current improvement in the on-state voltage drop. delays the onset of account. Since this base is not accessible.e. To take increases. size (IRGBC40S and IRGBC40U vs IRF840).1 11.. It should be remembered.5. as can be easily 3 verified from the data sheets of any manufacturer. In reality.2 600 500 2. This phenomenon is one of the causes of the “forward recovery” of fast (reverse recovery) diodes and of higher values of latching current in minority lifetime killed thyristors. that only the Ultrafast IGBTs exhibit this phenomenon.0 300 250 2. the base of the PNP. 4. 1000C Table 1: Dependence of Voltage Drop From Voltage Rating The voltage rating of the HEXFET® power MOSFETs used in this comparison are lower than the IGBTs to take into account their avalanche capability.

. as explained in the next section. This tail increases turn-off losses and requires an increase in the deadtime between the conduction of two devices in a halfbridge. Notice the clean break at the inception of the "tail". Figure 4. "dynamic latching" could occur at turn-off when a high density of hole current flows in r’ b. these techniques increase the voltage drop. E: 5 mJ/div. There is. 1 µs/div. 5.5ms for the voltage to drop the last 50V. the IGBT may experience a short burst of current if the complementary device is turned on soon after the current has ceased in the one that was conducting. where the turn-on losses have become larger than the turn-off losses. Thus. IGBTs operated in zero current switching may exhibit quasisaturation losses at turn-on that are somewhat higher than in switchmode circuits. As the MOSFET channel stops conducting. and by latching considerations on the other. Switching waveforms of a commercially available IGBT with heavy lifetime killing. the gain of the PNP is constrained by conduction and turn-on losses on one hand. IC VCE VCE : 100V/div. IC: 10A/div. which is the parasitic bipolar of the MOSFET. the IGBT is made of four alternate P-N-P-N layers. The energy plot shows that the losses at turn-on are twice as high as those at turn-off. can be reduced with the same techniques [1] that are commonly employed to give HEXFET®s their avalanche and dv/dt capability. Like all minority carrier devices. however. 6. This is due to the fact that the turn-on of the complementary device causes the supply voltage to appear across the first IGBT. The three main conditions that would subject an IGBT to this combined stress are the following: .Int) The charges stored in the base cause the characteristic “tail” in the current waveform of an IGBT at turn-off (Figure 3). If this r’b is not adequately reduced. It takes approximately 0. thereby depleting its base region and causing a final sweep-out of the minority carriers that were still left there. LATCHING As shown in the cross-section of Figure 1. The N+ buffer layer and the wide epi base reduce the gain of the PNP. minority lifetime killing causes a quasi-saturation condition at turn-on. Pushed to the extreme. Turn-off waveform of a commercial IGBT at 250C. with zero-voltage turn-off. a component of current that is due to the charging of the device capacitances and is totally unrelated to minority carriers. The low di/dt that is characteristic of this mode of operation emphasizes the "switchback" phenomenon described in the previous section. taking the gain of the parasitic NPN to much higher values. 0. Given the necessary conditions (αNPN + αPNP > 1) the IGBT could latch-up like a thyristor.AN-983 (v. electron current ceases and the IGBT current drops rapidly to the level of the hole recombination current at the inception of the tail. the switching performance of an IGBT degrades with temperature. Traditional lifetime killing techniques and/or an N+ buffer layer to collect the minority charges at turn-off are commonly used to speed-up recombination time. while the gain of the NPN. Similarly.2 µs/div. Insofar as they reduce the gain of the PNP. VCE IC ENERGY VCE : 100V/div. mainly a drastic reduction of the r’b. Figure 3. Switching circuit as in Figure 16. as shown in Figure 4. Switching circuit as in Figure 16. SAFE OPERATING AREA The safe operating area (SOA) describes the capability of a transistor to withstand significant levels of voltage and current at the same time. IC : 5A/div. rated current..

as indicated in Section 9. IGBTs from International Rectifier can be operated at their maximum switching speed without any problem.. This. Reasons to limit the switching speed should be external to the device (e. the transconductance of an IGBT tops out at current levels that are well beyond its thermal capability. These conditions are different from those described in the previous section in so far as the load current is totally made up of holes flowing through r’b. thereby avoiding a potential "dynamic latching" condition. Linear operation exercises the SOA of the IGBT in a combination of the two modes described above. As shown in Figure 5. large enough to turn on the NPN parasitic bipolar with possible latching. Operation in short circuit. The IGBT. combine with the flattening of the gain of the PNP. sometimes referred to as "clamped IL. 8. Since this second technique increases conduction losses and reduces switching speed. like all technical documents it requires a good understanding by the user of the different terms and conditions. No detailed characterization of IGBTs as linear amplifiers has been carried out by IR. 3. because its gain has fallen to very low values. 100 70 40 20 gfe hfe 10 7 4 2 1 1A 10A 100A COLLECTOR/DRAIN CURRENT 1000A BUX98 C50U IRGP 1000C 0 45 IRF Figure 5. the saturation in transconductance occurs at lower current as the temperature increases. as mentioned in the previous section or by a reduction of the total device transconductance. with all the information required to operate the IGBT reliably. .g. is not "gain limited. is a second order effect because the gain of the PNP is determined mainly by the N+ buffer layer. two families of IGBTs have been made available by IR. This high transconductance is partly responsible for their superior switching and conduction characteristics. it is entirely possible. HOW TO READ THE DATA SHEET International Rectifier prides itself on having one of the most comprehensive IGBT data sheets in the industry. The current in the IGBT is limited by its gate voltage and transconductance and can reach values well in excess of 10 times its continuous rating. While the "headline current rating" of power semiconductors is based solely on thermal considerations. 7. TRANSCONDUCTANCE The current handling capability of a semiconductor can be limited by thermal constraints or by gain / transconductance constraints. The level of hole current that flows underneath the N+ source contact can cause a drop across r’b. given the limited use of IGBTs in this type of application. However. the transconductance of fast IGBTs peaks at a lower level than those without lifetime killing. For this reason some manufacturers suggest the use of gate drive resistors to slow down the turn-off dv/dt and maintain some level of electron current." Since lifetime killing reduces the gain of the PNP. Current dependence of the transconductance of an IGBT compared to that of a HEXFET and to the gain of a bipolar of approximately the same die size. Operation as a linear amplifier. that the device cannot operate at the current level it is thermally capable of. as is frequently the case with bipolar transistors. This is normally prevented by a reduction in r’b. The flattening out of transconductance occurs when the saturation effects in the MOSFET channel. Inductive turn-off. however. overshoots due to stray inductance). rather than internal. the current density of a standard IGBT from International Rectifier reaches values of 10-20A/mm2 in short circuit.Int) 1. the other for short circuit operation. one optimized for low conduction losses. 2.AN-983 (v. while the gain of a bipolar of similar die size is on a steep downslope within its current operating range. like te power MOSFET. These are briefly explained in the following sections." In an inductive turn-off the voltage swings from a few volts to the supply voltage with constant current and with no channel current. With a gate voltage of 15V. Since temperature reduces the MOSFET channel current more than it increases the gain of the PNP. The decrease in transconductance at very high current and its additional decrease with temperature helps protect the IGBT under short circuit conditions. that reduce the base current of the PNP.

SHORT CIRCUIT U ULTRAFAST K ULTRAFAST. 8.2. the associated rating is of no practical value and is only reported because transistors have been traditionally rated in this way.Int) IR G P C 4 0 U D2 CO-PAK INTERNATIONAL RECTIFIER D2 DIODE IS ONE DIE SIZE SMALLER D1 DIODE IS TWO DIE SIZES SMALLER IGBT SPEED DESIGNATOR S STANDARD F FAST M FAST. with a junction temperature of 150°C. . Pulsed Collector Current (ICM). Continuous Collector Current @ TC = 25°C and 100°C (IC). the IGBT can be used to a peak current well above the rated continuous DC current. to prevent breakdown of the collector-emitter junction. Simplified nomenclature code for commercial IGBTs from International Rectifier 8.AN-983 (v. Within its thermal limits. as explained in Figure 6. This represents the dc current level that will take the junction to its rated temperature from the stipulated case temperature. It is calculated with the following formula: IC = ∆T θ j− c • VCE ( on ) @ I C where ∆Τ is the temperature rise from the stipulated case temperature to the maximum junction temperature (150°C) . The Headline Information In addition to the mechanical layout. Since in normal applications the case temperature is much higher than 25°C. The temperature rise during a high current transient can be calculated as indicated in Section Y. The Absolute Maximum Ratings This table sets up a number of constraints on device operation that apply under any circumstance. Figure 7 shows how this rating changes with case temperature. Notice that VCE(On) @ IC is not known because IC is not known. It is clear. 1t can be found with few iterations . SHORT CIRCUIT PACKAGE DESIGNATOR B P TO-220 TO-247 VOLTAGE DESIGNATOR C E F G H 600V 800V 900V 1000V 1200V MODIFIER DIE SIZE Figure 6. The test circuit is shown in Figure 8.1. that a current rating has no meaning without a corresponding junction and case temperature. The part number itself contains in coded form the key features of the IGBT. from this formula. Voltage across the IGBT should never exceed this rating. Collector-to-Emitter Voltage (VCE). for a specific device. The breakdown itself is guaranteed in the Table of Electrical Characteristics . the front page gives the voltage drop at the 100ºC current ratings.

that the device can sustain high voltage and high current simultaneously. It is calculated with the following formula: PD = ∆T θ j−c 15 12 9 6 3 0 25 50 75 100 125 150 Tc. Clamped Inductive Load Current (ILM).. Clamped Inductive Load Test Circuit 8.63V/°C. which adds a significant component to the turn-on losses (Figure 10). The ILM rating is specified at 150°C. This rating guarantees a square switching SOA. i. Thermal Resistance Rthjc. The gate voltage is limited by the thickness and characteristics of the gate oxide layer. the user is limited to 20V to limit current under fault conditions and to ensure long term reliability. This parameter guarantees the lower limit of the distribution in breakdown voltage. This rating guarantees that the device is able to repetitively turn off the specified current with a clamped inductive load. Rthja are needed for the thermal design. This complements the information supplied by the RBSOA. Though the gate dielectric rupture is typically around 80 volts. This implies that a device with 600V breakdown at 25°C would have a breakdown voltage of 550V at -55°C. Maximum Power Dissipation @ 25°C and 100°C (PD). Junction Temperature (Tj): the device can be operated in the industry standard range of -55°C to 150°C.4. Electrical Characteristics The purpose of this section is to provide a detailed characterization of the device so that the designer can predict with accuracy its behavior in a specific application.3. the test circuit (Figure 9) exposes the IGBT to the peak recovery current of the free-wheeling diode. Collector-to-Emitter Breakdown Voltage (BVCES). CASE TEMPERATURE (0C) Figure 7. as encountered in most applications. Case Temperature The same comments that were made on the Continuous Collector Current apply to Power Dissipation. as explained in INT-949 8. Pulsed Collector Current Test Circuit Figure 9. Breakdown is defined in terms of a specific leakage current and has a positive temperature coefficient (listed in the table as BVCES/∆T) of about 0. Reverse Avalanche Energy (EARV). In fact. Maximum Collector Current vs.e.AN-983 (v. 480V 32µF 600V 480 RL = 4 X IC @ 250C 480V 10µH 32µF 600V 40HFL60 10Ω DUT 10Ω DUT Figure 8.Int) MAXIMUM COLLECTOR CURRENT (AMPS DC) Maximum Gate-to-Emitter Voltage (VGE). . Rthcs. This subject is covered in detail in the BVECS section of the electrical characteristics . 80% of the rated voltage.

. To discriminate between the losses that are intrinsic to the IGBT and those due to the diode reverse recovery. Test circuit as in Figure 16./div. the test circuit shown in Figure 16 has been used to generate the data sheet values. Emitter-to-Collector Breakdown Voltage (BVECS). This parameter is measured by superimposing a small variation on a gate bias that takes the IGBT to its 100°C rated current in "linear" mode. The variation in gate threshold with temperature is also specified (∆VGE(th) / ∆Τj). Turn-on with an ideal diode (zener clamp). T1 D1 LS LS T2 D2 Figure 11.e. 0. 0.. Being the key rating to calculate conduction losses. current and gate voltage (Figures 14./div. IR's IGBTs have a specified reverse blocking capability (BVC E S) and an avalanche rating (ERV) .1 µs/div IC VCE : 100V/div. This is the range of voltage on the gate at which collector current starts to flow. IC : 5A. though higher voltages can result from very high di/dt or poor layout. As mentioned in Section 7. that is more useful to the designer than a traditional diode characterization. the turn-off di/dt in the stray inductance that is in series with the diode generates a reverse voltage spike across the IGBT (i. and 16 for the IRGBC20U). but by thermal considerations. the collector voltage goes negative with respect to the emitter). Turn-on with a clamped inductive load and a fast recovery diode. International Rectifier IGBTs have an energy rating. 15. given in the Absolute Maximum Ratings table.. Gate Threshold Voltage (VGE(th)). IC : 5A. The reverse turnoff di/dt of T2 developes a voltage across the stray inductance in series with D1 which reverse biases T1. This reverse voltage is typically less than 10V. Typically the coefficient is -11 mV/°C. The reverse recovery is a significant contributor to turn-on losses.Int) VCE VCE IC VCE : 100V/div.AN-983 (v.4V in the threshold voltage at high temperature. Test circuit as in Figure 9. Figure 10b . Collector-to-Emitter Saturation Voltage (VCE(on)). When an IGBT turns off and current is transferred to the diode across the complementary device. When T2 goes off. This rating characterizes the reverse breakdown of the unterminated collector-base junction of the PNP.1 µs/div Figure 10a . leading to a reduction of about 1. this value is supported by three figures that provide a detailed characterization in temperature. These replace the older format shown in Figure 12 and 13. Forward Transconductance (gFE). as a bipolar. transconductance increases significantly with current so that the "current throughput" of an IGBT is not limited by gain. The relevance of this specification and its associated reverse avalanche energy can be better understood with reference to Figure 11. Since this reverse voltage can cause avalanche in the junction. load current flows into the diode in parallel with T1. This rating is typically an order of magnitude more than what would be required by the user.

Typical Output Characteristics. The voltage fall time. Figure 17 gives the typical value of the total gate charge as a function of the voltage applied to the gate.0V 100 5. Tc = 250C Figure 13. Qgc). as for a power MOSFET.AN-983 (v. This parameter guarantees the upper limit of the leakage distribution at the rated voltage and two temperatures. Those for co-paks are defined with reference to the Clamped Inductive Load of Figure 19. They provide a very unreliable indication of switching losses. two significant contributors to losses are not properly accounted for by the switching times. Gate charge values of an IGBT are useful to size the gate drive circuit and estimating gate drive losses. a significant part of the turn-off energy may be dissipated as the current is below 10%.5. they are defined as follows: • • • • Turn-on delay time: 10% of gate voltage to 10% of collector current Rise time: 10 to 90% of collector current Turn-off delay time: 90% of gate voltage to 90% of collector current Fall time: 90 to 10% of collector current. they are defined as follows: • • • • Turn-on delay time: 10% of gate voltage to 10% of collector current Rise time: 10 to 90% of collector current Turn-off delay time: 90% of gate voltage to 10% of collector voltage Fall time: 90 to 10% of collector current. For a copak.0V 5. VGE 50V 15V 10V 7. Switching losses are fully characterized as such in the data sheet. as explained in the next paragraph.0V BOTTOM 5. 8. Tc = 1500C . COLLECTOR-TO-EMITTER VOLTAGE (VOLTS) 0 2 4 6 8 10 Vce. The test method and the characteristics described in the application note INT-944. tf). because of the minority carrier nature of this device. The shape of the curve is explained in detail in INT-944. It complements the BVCES rating seen above. Thus. Unfortunately they cannot be used to predict switching times.2. is not characterized in any way. Switching Times (td.0V TOP Ic. Typical Output Characteristics. COLLECTOR-TO-EMITTER CURRENT (AMPS) 101 BOTTOM Ic. COLLECTOR-TO-EMITTER CURRENT (AMPS) TOP 101 100 5. Switching Characteristics GateChargeParameters(Qg. on the other hand.0V VGE 50V 15V 10V 7. Qge. tr. Because of the current tail mentioned in Section 8. Switching times provide a useful guideline to establish the appropriate deadtime between the turn-off and subsequent turn-on of complementary devices in a half bridge configuration and the minimum and maximum pulse widths. For a simple device. COLLECTOR-TO-EMITTER VOLTAGE (VOLTS) Figure 12. The switching times for a simple IGBT are defined with reference to the Switching Loss Test Circuit of Figure 18.Int) Zero-Gate-Voltage Collector Current (ICES).0V 10-1 10-2 20µs pulse width Tj = 250C 20µs PULSE WIDTH Tj = 250C 10-1 0 2 4 6 8 10 Vce.

It must reflect the losses that are attributable to the IGBT.0 Ic = 6. Tc. the energy figures reported in the data sheet are defined as follows: . i. Gate-to-emitter Voltage (V) 20 Figure 14. including the quasisaturation at turn-on and the tail at turn-off. The DUT will see the test current that was flowing into the inductor and the voltage across the zener. Case Temperature The test circuit that meets these requirements for a simple IGBT is shown in Figure 18. IGBTs from International Rectifier have a guaranteed switching energy providing a full characterization in terms of temperature. by turning on and off the device under test (DUT). This test can exercise the IGBT to its full voltage and current without any spurious effect due to diode reverse recovery. When it is turned off. collector current and gate resistance (Figures 20. The test method.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 2. must account for all losses that occur because of the switching operation. The turn-off delay is due to the Miller effect.0 Ic = 3. on the other hand. Figure 15.AN-983 (v.A of INT-990. Collector-to-Emitter Saturation Voltage vs. current flows in the zener. It must simulate the switching conditions as they are encountered in a practical application. like the reverse recovery of the freewheeling diode. the tail and the quasisaturation. as explained in Section I.3A 1. It should be remembered that IGBTs.0 Vce. Eoff. At this point the switching time and switching energy test begins. 21 and 22 for the IRGBC20U). Collector-to-emitter Current (A) IC. COLLECTOR-TO-EMITTER VOLTAGE (VOLTS) Ic = 13A Vge = 15V 80ms pulse width Switching Energy (Eon. Ets). 3.e. like power MOSFETs.5A 2. CASE TEMPERATURE (0C) Figure 16. This allows the designer to calculate the switching losses. Gate-to-emitter Current (A) Tj = 250C Tj = 1500C 10 Tj = 1500C 10 Tj = 1500C 1 VGE = 15V 20µs PULSE WIDTH 1 VCE. without worrying about the actual current and voltage waveshapes.. To fulfill this requirement. without any reverse recovery component from a freewheeling diode. 4. and must be independent from those due to other circuit components. Any test circuit for measuring switching losses has to satisfy two fundamental requirements: 1. do not have a storage time. Collector-to-emitter Voltage (V) 10 0. Its operation is as follows: The driver IGBT builds the test current in the inductor.Int) 100 100 IC. a clamped inductive load with continuous current flow.1 5 VCC = 100V 5ms PULSE WIDTH 10 15 VGE.

The definitions are as follows: Eon: From 10% of test current to 5% of test voltage. This is not necessarily true for IGBTs from other manufacturers. Cree). While the current tail of most IGBTs would be finished well before that time. TOTAL GATE CHARGE (nC) 20 Figure 17. As shown in Figure 22. Typical Gate Charge vs. should include the losses due to the diode. The output capacitance has the typical voltage dependence of a P-N Emitter Voltage LC DRIVER * DUT 1 2 3 * DRIVER SAME TYPE AS DUT VC = 80% OF BVCES Figure 18a 1 2 90% 3 VC 90% 5% 10% tr Eon Ets = (Eon + Eoff) tf Eoff t = 5 µs 10% td(off) IC Figure 18b. on the other hand. Eoff: This energy is measured over a period of time that starts with 10% of test voltage and goes on for 5 µsec. Ets: This is the sum of the turn-on and turn-off losses. Figure 18. Device Capacitances (Ciee. The test circuit for a co-pack. Eoff: This energy is measured over a period of time that starts with 5% of test voltage and goes on for 5 µsec. The input capacitance.Int) Vge. Internal Emitter Inductance (LE) This is the package inductance between the bonding pad on the die and the electrical connection at the lead. The test circuit and a brief explanation of the test method can be found in Figure 20.AN-983 (v. assuming a clamped inductive load with an identical device in a complementary position (Figure 19).5A 16 12 8 4 0 0 4 8 12 16 Qg. 20 Vce = 480V Ic = 6. the voltage developed across this inductance is in excess of 7V. The reverse transfer (Miller) capacitance is also strongly dependent on voltage (inversely proportional). shows the same voltage dependence of the Miller capacitance but in a very attenuated form since the gate-toemitter capacitance is much larger and voltage independent. just like the Miller effect slows it down by an amount that is proportional to the collector dv/dt. With a di/dt of 1000 A/µsec. but in a more complex way than the output capacitance. We feel that 5% is a reasonable compromise between the resolution of the instrumentation and the need to account for the quasi-saturation that could occur in some devices. Gate . Switching Loss Test Circuit and Waveforms . GATE-TO-EMITTER VOLTAGE (VOLTS) Eon: From 5% of test current to 5% of test voltage. Coee. it was felt that the contribution of the leakage losses to the total energy is minimal. This inductance slows down the turn-on of the IGBT by an amount that is proportional to the di/dt of the collector current. switching energy for International Rectifier IGBTs is closely proportional to current. which is the sum of the gate-to-emitter and of the Miller capacitance.

Vg GATE SIGNAL DEVICE UNDER TEST CURRENT D. trr Qrr= ∫ trr Id dt tx 10% Irr Vcc Vce 10% Ic 90% Ic 5% Vce DUT VOLTAGE AND CURRENT Vcc Ipk Ic td (on) tr t2 Eon = Vce Ic dt t1 t2 ∫ DIODE REVERSE WAVEFORMS t4 Erec= Vd Id dt t3 t4 t1 DIODE REVERSE RECOVERY ENERGY t3 ∫ Figure 19c.T. Vce 10% Vce Ic tf 90% Ic 5% Ic t1+5µs Eoff = Vce Ic dt t1 Ic 80% of Vce 430µF D.T.U.AN-983 (v. td (off) ∫ t1 t2 Figure 19a.Int) + Vge 90% Vge Same type device as D.U.U. CURRENT IN D1 Figure 19e.T.U. Figure 19d. GATE VOLTAGE DUT 10% +Vg +Vg tx 10% Vcc Vpk Ic Figure 19b.T. VOLTAGE IN D. .

AN-983 (v.Int)

Vce = 480V Vge = 15V Tc = 250C Ic = 6.5A



Vge = 15V Vcc = 480V Rg = 50Ω

Ic = 13A 100 Ic = 6.5A


0.335 0.330

Ic = 3.3A


0.320 20


30 35 40 45 50 Rg, GATE RESISTANCE (OHMS)


10-1 -60 -40 -20

0 20 40 60 80 100 120 140 160 Tc, CASE TEMPERATURE (0C)

Figure 20. Typical Switching Losses vs. Gate Resistance

Figure 21. Typical Switching Losses vs. Case Temperature

The Transfer Characteristic (Figure 15 for the IRGBC20U). This curve deviates from the traditional definition of transfer characteristic in one detail: the drain is not connected to the gate but to a fixed (100V) supply. When gate and drain are tied together, the curve is the boundary separating operation in full enhancement from operation in linear mode (sometimes referred to as "sat mode"). Figure 15 provides an indication of current when operated in short circuit. In the normal range of operation this curve shows a slight negative dependence on temperature and is largely independent from applied voltage. The Short-Circuit Withstand Time (for short-circuit rated IGBTs) defines the guaranteed minimum time the IGBT can be in short circuit in the specified conditions. Notice that the gate resistor cannot be any lower than specified and the overvoltage at turn-off has to be maintained to the indicated value by an appropriate clamp.
If a diode is copackaged with the IGBT, its characteristics are included in this table, together with their associated graphs. The parameters included in the table are defined in application note AN-989.
1.00 TOTAL SWITCHING ENERGY LOSSES (mJ) Tc = 1500C Rg = 250Ω Vcc = 480V Vge = 15V

9: The IGBT Families from IR
Table II may be useful in placing different power transistors in the proper perspective. In general, the IGBT offers clear advantages in high voltage (>300V), high current (1-3 A/mm2 of active area), and medium speed (to 5-50 kHz). International Rectifier’s technology is characterized by very low voltage drop per unit of current density. This allows higher levels of minority lifetime killing and, consequently, much lower switching losses. To maximize the value to the user of its technological breakthrough, International Rectifier has introduced three different families of devices with different crossover frequency: Standard, Fast and UltraFast. IR's Standard IGBTs have been optimized for voltage drop and conduction losses and have the lowest voltage drop per unit of current density that is presently available in the market.

0.90 0.80 0.70

0.60 0.50


0.30 3


Figure 22. Typical Switching Losses vs. Collector Current

AN-983 (v.Int) IR's UltraFast IGBTs have been optimized for switching losses and have the lowest switching losses per unit of current density presently available in the market. As it is apparent from Figure 24, these devices have switching speeds that are comparable to those of power MOSFETs in practical applications. They can operate comfortably at 50 kHz in PWM and well over 100 kHz in resonant or ZVS/ZCS circuits.

620K DUT Ciee = Ccg + Cge =





1 1 Cmeasured 1 C2

10M 620K



Figure 23a.
HIGH C2 620K Coee = Ccg + Cce = CAPACITANCE METER DUT BIAS VOLTAGE LOW 620K = 1 1 Cmeasured 1 C2

Figure 23b.

Figure 23c. Figure 23. Capacitance test circuits

The IGBT is biased with 25V between collector and emitter. Two of its terminals are ac shorted with a large value capacitor. Capacitance is measured between these two terminals and the third.
IR's Fast devices offer a combination of low switching and low conduction losses that closely matches the switching characteristics of many popular bipolar transistors. Table III shows the key features of the three families. The Fast and Ultrafast IGBTs are also available in short-circuit rated versions for those applications, like motor drives, that require it. The short circuit capability comes at the expenses of a slight increase in conduction losses.

AN-983 (v.Int)



IC ENERGY VCE : 100V/div. IC : 10a/div. E : 0.5µJ/div., 0.1ms/div.

IC ENERGY VCE : 100V/div. IC : 10A/div. E : 0.5 mJ/div., 0.1 µs/div

Figure 24a.

Figure 24b.

Figure 24. IRGPC50U switching 50A at 480V, 1250C. Test circuit is as shown in Figure 16.

Type of Drive Drive Power Drive Complexity

POWER MOSFETs Voltage Minimal Simple

IGBTs Voltage Minimal Simple

Current Density For Give Voltage Drop Switching Losses

High at low voltages Low at high voltages Very Low

Very High Small trade-off with switching speed Low to Medium depending on trade-off with conduction losses

Bipolars Current Large High Large positive and negative currents are required Medium Severe trade-off with switching speed Medium to High depending on trade-off with conduction losses

Darlingtons Current Medium Medium



Table II: Comparative Table of Power Transistor Characteristics

References: 1. U.S. Patents No. 4,376,286 and 4,642,666

Characteristic VCE Switching Energy Conduction Losses (50% dc)

Standard 1.3V 0.54 mJ/A mm

Fast 1.5V 0.16 mJ/A mm

Ultrafast 1.9V 0.055mJ/A mm




Table III. International Rectifier IGBT Families
1A/mm , 1000C, Typical Values

Mounting Torque.063 in.Diode Case-to-Sink. typical socket mount Weight 1 4/17/00 . ----------0.5 -----80 ------ Units °C/W g (oz) www. Max. (1. IC = 12A n-cha nn el Benefits • Generation -4 IGBT's offer highest efficiencies available • IGBTs optimized for specific application conditions • HEXFRED diodes optimized for performance with IGBTs .PD 91453B IRG4BC30UD INSULATED GATE BIPOLAR TRANSISTOR WITH ULTRAFAST SOFT RECOVERY DIODE Features • UltraFast: Optimized for high operating frequencies 8-40 kHz in hard switching.07) Max.95V @VGE = 15V. ultra-soft-recovery anti-parallel diodes for use in bridge configurations • Industry standard TO-220AB package C UltraFast CoPack IGBT VCES = 600V G E VCE(on) typ.6mm) from case) 10 lbf•in (1. for 10 sec.2 2.50 ----2 (0. ------------------------- Typ. = 1. 1. Minimized recovery characteristics require less/no snubbing • Designed to be a "drop-in" replacement for equivalent industry-standard Generation 3 IR IGBTs TO-220AB Absolute Maximum Ratings Parameter VCES IC @ TC = 25°C IC @ TC = 100°C ICM ILM IF @ TC = 100°C IFM VGE PD @ TC = 25°C PD @ TC = 100°C TJ TSTG Collector-to-Emitter Voltage Continuous Collector Current Continuous Collector Current Pulsed Collector Current Q Clamped Inductive Load Current R Diode Continuous Forward Current Diode Maximum Forward Current Gate-to-Emitter Voltage Maximum Power Dissipation Maximum Power Dissipation Operating Junction and Storage Temperature Range Soldering Temperature.IGBT Junction-to-Case .1 N•m) Units V A V W °C Thermal Resistance Parameter RθJC RθJC RθCS RθJA Wt Junction-to-Case . 6-32 or M3 Screw. greased surface Junction-to-Ambient. flat.irf. >200 kHz in resonant mode • Generation 4 IGBT design provides tighter parameter distribution and higher efficiency than Generation 3 • IGBT co-packaged with HEXFREDTM ultrafast. 600 23 12 92 92 12 92 ± 20 100 42 -55 to +150 300 (0.

18 ---ns IC = 12A. RG = 23 Ω 130 Energy losses include "tail" and ---diode reverse . Collector-to-Emitter Breakdown VoltageS 600 ∆V(BR)CES/∆ TJ Temperature Coeff.6.5 5. 10. 2.250 µA ---.52 ---V 2.6 80 220 180 120 Max. VCE = 600V VGE = 0V.1 2.Emitter Charge (turn-on) Gate . 7 ---ƒ = 1. IC = 12A VGE = 0V.38 0. 10. ---nH Measured 5mm from package ---VGE = 0V ---pF VCC = 30V See Fig.0MHz 60 ns TJ = 25°C See Fig. of Threshold Voltage ---gfe Forward Transconductance T 3. 11.IRG4BC30UD Electrical Characteristics @ TJ = 25°C (unless otherwise specified) Parameter Min. VCE = 600V. of Breakdown Voltage ---VCE(on) Collector-to-Emitter Saturation Voltage ---------VGE(th) Gate Threshold Voltage 3.±100 nA Conditions VGE = 0V. IC = 250µA VCE = VGE.0mA IC = 12A VGE = 15V IC = 23A See Fig. 120 TJ = 125°C 14 IF = 12A 6.irf. 13 IC = 12A. 8 27 VGE = 15V ---TJ = 25°C ---ns IC = 12A.1 ICES Zero Gate Voltage Collector Current ------V FM Diode Forward Voltage Drop ------IGES Gate-to-Emitter Leakage Current ---V(BR)CES Typ. TJ = 150°C VGE = ±20V Switching Characteristics @ TJ = 25°C (unless otherwise specified) Qg Qge Qgc td(on) tr td(off) tf Eon Eoff Ets td(on) tr td(off) tf Ets LE Cies Coes Cres t rr Irr Qrr di (rec)M/dt Parameter Total Gate Charge (turn-on) Gate .3 1. 5 IC = 12A.9 ---TJ = 150°C. 18 0. TJ = 150°C VCE = VGE. 600 TJ = 125°C 16 di/dt 200A/µs ---. VCC = 480V ---VGE = 15V. 10 TJ = 125°C 15 VR = 200V 180 nC TJ = 25°C See Fig.0 -11 ---.mV/°C 8.54 40 22 120 180 0.Collector Charge (turn-on) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Switching Loss Turn-Off Switching Loss Total Switching Loss Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Switching Loss Internal Emitter Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Diode Reverse Recovery Time Diode Peak Reverse Recovery Current Diode Reverse Recovery Charge Diode Peak Rate of Fall of Recovery During tb Min. VCC = 480V 140 VGE = 15V. IC = 250µA VGE = 0V. Max.0 ∆VGE(th)/∆TJ Temperature Coeff.7 V 1.95 2.0 A TJ = 25°C See Fig. See Fig. IC = 250µA VCE = 100V. Units ------V 0.V/°C 1.89 7. ---------------------------------------------------------------------------------Typ. IC = 1. 50 8.5 1100 73 14 42 80 3. 9. ---TJ = 125°C 17 2 www.6 ---S ---.09 ------.6 ---.63 ---. RG = 23 Ω ---Energy losses include "tail" and ---mJ diode reverse recovery.16 0.A/µs TJ = 25°C See Fig.1 18 40 21 91 80 0. Units Conditions 75 IC = 12A 12 nC VCC = 400V See Fig. ---mJ See Fig.4 1. 11. 9. TJ = 150°C IC = 12A See Fig.2500 1.

C olle cto r-to -E m itte r C u rre n t (A ) TJ = 2 5 ° C TJ = 1 5 0 °C 10 I C . C o lle cto r-to -E m itte r C u rre n t (A ) TJ = 1 5 0 °C 10 TJ = 2 5 ° C 1 1 0.Typical Load Current vs.Typical Transfer Characteristics www. 1 .1 5 6 7 8 V CC = 10V 5 µ s P U L S E W ID T H 9 10 11 A 12 V C E .irf. C o lle cto r-to -E m itte r V o lta g e (V ) VG E . 3 . 2 . Frequency (Load Current = IRMS of fundamental) 100 100 I C . Frequency (kHz) Fig.1 1 10 A 100 f.1 0. G a te -to -E m itte r V o lta g e (V ) Fig.IRG4BC30UD 16 12 Load Current ( A ) D uty c yc le : 5 0% T J = 12 5 ° C T s in k = 90 ° C G a te d rive a s s pe c ified T urn -o n losse s in clud e effects of re verse re co very Pow e r D is sipatio n = 21 W 6 0 % o f ra te d vo l ta g e 8 I 4 0 3 .1 1 VG E = 1 5 V 2 0 µ s P U L S E W ID T H A 10 0.Typical Output Characteristics Fig.

0 10 5 I C = 6 . Ju n c tio n T e m p e ra tu re ( ° C ) Fig.Maximum Collector Current vs. D u ty f ac t or D = t 1 / t 2 0 .0 0 0 1 0 .0 A A -60 -40 -20 0 20 40 60 80 100 120 140 160 0 25 50 75 100 125 A 150 1. 4 .0 VGE = 15V 8 0 µ s P U L S E W ID T H IC = 2 4 A 20 2. Junction-to-Case 4 www. Junction Temperature 10 Therm al Response (Z thJ C ) 1 D = 0. R ectangular Pulse Duration (sec) Fig.0 1 0 .Typical Collector-to-Emitter Voltage vs. P e a k TJ = P D M x Z th J C + T C 0 .1 1 10 t 1 .0 0 0 0 1 2 .05 0 .20 .10 PD M 0 .IRG4BC30UD M a xim u m D C C o lle c to r C u rre n t (A 25 V C E .Maximum IGBT Effective Transient Thermal Impedance.0 0 1 0 . C a s e Te m p e ra tu re ( ° C ) T J . 6 .0 1 0 .5 0 0. 5 .irf.1 0 .0 1 S IN G L E PU LS E (T H E R M AL RE S PO N SE ) t 1 t2 N o te s : 1 .5 15 IC = 1 2 A 2. Case Temperature Fig. C ollector-to-Em itter Volta ge (V) V GE = 15V 3.5 TC .0 2 0 .

Gate Resistance ( Ω) TJ .Typical Switching Losses vs. f = 1MHz C g e + C g c . 7 .irf. Junction Temperature ( ° C) Fig.Typical Gate Charge vs.58 Total Switchig Losses (mJ) V C C = 480V V G E = 15V T J = 25 ° C I C = 12A R G = 23 Ω V G E = 15V V C C = 480V I C = 24A 0.Typical Switching Losses vs. Collector-to-Emitter Voltage Fig.0A 0.54 I C = 6.Typical Capacitance vs. 8 .52 0.50 0 10 20 30 40 50 A 60 0.1 -60 -40 -20 0 20 40 60 80 100 120 140 A 160 R G . C o lle c to r-to -E m itte r V o lta g e (V ) Q g . C apa cita nc e (pF ) 1600 V GE = C ie s = C re s = C oes = 0V . G a te -to -E m itte r V o lta g e (V ) A C.60 10 Total Switchig Losses (mJ) 0.IRG4BC30UD 2000 V G E . C ce S H O R TE D C gc C ce + C g c 20 VCE = 400V IC = 12A 16 C ie s 1200 12 800 C oes 8 400 C re s 4 0 1 10 0 0 10 20 30 40 A 50 100 V C E . T o ta l G a te C h a rg e (n C ) Fig. Junction Temperature www. 10 . 9 .56 1 I C = 12A 0. Gate-to-Emitter Voltage 5 . Gate Resistance Fig.

1 1 10 100 1000 I C . C ollector-to-E m itter C urrent (A ) RG TJ V CC V GE = 23 Ω = 150 ° C = 480V = 15V 1000 VG = 2 0V EE G T J = 12 5 ° C 100 1.V FM (V ) Fig.4 0.Typical Switching Losses vs.irf. Collector-to-Emitter Current (A ) V C E . Collecto r-to-E m itter V oltage (V ) Fig. 13 . 12 .6 2.I F (A ) TJ = 15 0 ° C 10 TJ = 12 5 ° C TJ = 2 5 ° C 1 .8 1 0.6 I C . Instantaneous Forward Current 6 www.2 1.0 0 10 20 30 A 0 .Turn-Off SOA Instan tan eou s Fo rwa rd C urre nt .0 Total Switchig Losses (mJ) 1.8 1. 11 .4 Fo rwa rd V oltage D rop .0 2. Collector-to-Emitter Current 100 Fig.4 0.Maximum Forward Voltage Drop vs.IRG4BC30UD 2.2 S A FE O P E R A TIN G A R E A 10 0.

(ns) I F = 1 2A I F = 6 .0A I F = 6 .Typical Stored Charge vs.(A ) I F = 2 4A 10 t rr .0 A I F = 2 4A I F = 1 2A I F = 12 A 100 200 I F = 6.(n C ) IF = 6. dif/dt 10000 VR = 2 0 0 V TJ = 1 2 5 °C TJ = 2 5 ° C VR = 2 0 0 V TJ = 1 2 5 °C TJ = 2 5 ° C 400 d i(re c )M /d t .com 7 . 16 . 17 . dif/dt 600 Fig.Typical Reverse Recovery vs.Typical Recovery Current vs.(A /µ s) 1000 1 100 1000 di f /dt . 14 .(A /µ s) Fig.Typical di(rec)M/dt vs.(A /µs) Fig. dif/dt Fig.(A /µ s) 1000 Q R R . 15 .0 A I F = 2 4A 0 100 d i f /d t .0 A 40 0 100 d i f /d t .(A /µ s) 1000 10 100 1000 d i f /d t . dif/dt www.IRG4BC30UD 160 100 VR = 2 0 0 V TJ = 1 2 5 °C TJ = 2 5 ° C 120 VR = 2 0 0 V TJ = 1 2 5 °C TJ = 2 5 ° C I F = 24 A I F = 1 2A 80 I IR R M .irf. . 18d .U . tf G A T E V O L T A G E D .Test Waveforms for Circuit of Fig. trr.Test Waveforms for Circuit of Fig. td(on).irf. 10% Vce Ic 9 0 % Ic 5 % Ic td (o ff) tf Eoff = ∫ t1 + 5 µ S V c e ic d t t1 Fig. Qrr.IRG4BC30UD 90% Vge +Vge Same ty pe device as D . Defining Erec. tr. td(on). Vce Ic 80% of Vce 430µF D . Irr. 18a .T. Defining Eon. Eon. Irr 8 www. tr Fig. Defining Eoff. 1 0 % +V g +Vg trr Ic Q rr = ∫ trr id d t tx tx 10% Vcc Vce Vcc 1 0 % Ic 9 0 % Ic D UT VO LTAG E AN D CU RRE NT Ip k Ic 1 0 % Irr V cc V pk Irr D IO D E R E C O V E R Y W A V E FO R M S td (o n ) tr 5% Vce t2 E o n = V ce ie d t t1 t2 D IO D E R E V E R S E REC OVERY ENER GY t3 t4 ∫ E re c = t1 ∫ t4 V d id d t t3 Fig.T .T. td(off). Eoff(diode). 18a. 18b . Qrr. td(off).Test Waveforms for Circuit of Fig. tf t1 t2 Fig. 18a. 18c .U.U . trr.Test Circuit for Measurement of ILM.

C U R R E N T IN D 1 t0 t1 t2 Figure 18e.480V 480V 4 X IC @25°C Figure 19.U.U .IRG4BC30UD V g G A T E S IG N A L D E V IC E U N D E R T E S T C U R R E N T D .T . Pulsed Collector Current Test Circuit www. Macro Waveforms for Figure 18a's Test Circuit L 1000V 50V 6000µ F 100 V Vc* D.T. Clamped Inductive Load Test Circuit Figure 20.U .com 9 .T . V O L T A G E IN D .irf. RL= 0 .


MOS CONTROLLED THYRISTOR ÍNDICE Assunto Introdução Princípio de Funcionamento Características Parâmetros Operação Forma de Onda da Tensão de Gatilho Amplitude Negativa Transição Negativa Amplitude Positiva Transição Positiva Área de Operação Segura de Bloqueio Circuitos de Comando Coeficiente de Temperatura da Tensão Comparação: IGBT versus MCT Queda de Tensão em Condução Comutação Tensão de Operação Segura de Bloqueio Onde Usar o MCT? Referências Bibliográficas Página 3 4 5 6 8 8 9 9 9 9 10 10 12 13 13 13 14 14 15 INEP .INSTITUTO DE ELETRÔNICA DE POTÊNCIA 2 .MCT .

o que torna-se possível consultando as referências bibliográficas apresentadas. INEP .MCT . porém concisa. Objetivando a familiarização com o componente. o seu funcionamento e suas principais características.emerge como uma alternativa ímpar para a implementação e projeto das estruturas envolvidas em eletrônica de potência. como SCRs ou GTOs.já disponível comercialmente . embora carregue consigo semelhanças com interruptores mais antigos. Um novo dispositivo semicondutor de potência. na dependência do aperfeiçoamento ou do desenvolvimento de novos interruptores à base de dispositivos semicondutores. descreve-se de maneira genérica.INSTITUTO DE ELETRÔNICA DE POTÊNCIA 3 . o “MOS Controlled Thyristor”. não havendo compromisso com o aprofundamento do assunto. Possui seu próprio conjunto de características.MOS CONTROLLED THYRISTOR INTRODUÇÃO A eletrônica de potência invariavelmente soluciona problemas relacionados à utilização de energia elétrica. ou simplesmente MCT . Progressos nesta área traduzem-se. freqüentemente.

Circuito Equivalente O bloqueio é proporcionado. VGA . o P-MCT. pela aplicação de tensão VGA positiva. O mosfet canal N entra em condução. via gatilho. Aplicando-se tensão VGA negativa. No P-MCT. o mosfet canal P realiza o disparo.o arranjo permite o comando do MCT através da tensão gate-anodo. polarizando a base do transistor inferior (NPN). desviando a corrente de emissor do transistor PNP bloqueando-o.MOS CONTROLLED THYRISTOR PRINCÍPIO DE FUNCIONAMENTO A figura 1 mostra o circuito equivalente do MCT tipo P. baseado no modelo de tiristor a dois transistores. responsáveis pelo disparo e bloqueio via gatilho . 1 . Isto provoca o corte da corrente de polarização da base do transistor NPN. INEP . o “PFET” é acionado. ANODO PFET-DISPARO GATILHO NFET-BLOQUEIO CATODO Fig. Nota-se também a presença de dois FETs.MCT .INSTITUTO DE ELETRÔNICA DE POTÊNCIA 4 . o que coloca o MCT em condução.

000 grupos de células em paralelo. O MCT também é bloqueado por corrente reversa. é constituída de cerca de 11. uma das quais destina-se ao disparo. O MCT apresenta diversas vantagens quando comparado com os interruptores tradicionais utilizados em eletrônica de potência: • A alta impedância do gatilho MOS exige uma quantidade mínima de energia para a comutação. permitindo o controle de disparo/bloqueio por tensão. como ocorre com tiristores comuns. 600 V. sendo rodeada pelas 8 restantes responsáveis pelo bloqueio. A figura 2 apresenta sua simbologia. Cada grupo constitue-se de 9 células de 0.MCT .MOS CONTROLLED THYRISTOR interrompendo a corrente de catodo do MCT e efetuando o seu bloqueio. A ANODO RETORNO GATILHO GATILHO G CATODO K Fig. • Possui baixa queda de tensão em condução. o MCT combina a capacidade de corrente dos tiristores com a alta impedância de entrada das portas MOS. CARACTERÍSTICAS Pela sua constituição.Simbologia A primeira geração de P-MCT. INEP .INSTITUTO DE ELETRÔNICA DE POTÊNCIA 5 . 2 .4 cm2 . simplificando os circuitos de comando.

máxima tensão permissível entre catodo e anodo. GTOs e MCTs podem apresentar queda de tensão em condução reduzida. possui capacidade de bloqueio suficiente para permitir o uso de um diodo em antiparalelo. • Tiristores. • Baixa capacitância de entrada. • Para uma mesma quantidade de silício.o MCT não é projetado como um componente de bloqueio de tensão reversa mas. pode apresentar densidades de corrente centenas de vezes maior que seu contemporâneo IGBT (figura 3).MOS CONTROLLED THYRISTOR • Grande capacidade de di/dt e dv/dt. tipicamente 10 nF. VDRM .MCT . alguns parâmetros são diferentes dos convencionais: • Tensão de Bloqueio de Pico (MCT Bloqueado). PARÂMETROS O MCT assemelha-se em certos aspectos aos tiristores. ITSM . • Tensão de Pico Reversa.INSTITUTO DE ELETRÔNICA DE POTÊNCIA 6 . • Excelente capacidade de corrente: para quedas de tensão similares. o MCT apresenta queda de tensão bem inferior quando comparado a outros interruptores como GTOs ou tiristores comuns. • São fabricados sobre uma ampla faixa de valores. podendo alcançar os 10KV. A temperatura da junção limita sua amplitude e largura. • Corrente de Catodo de Pico Não Repetitiva. Muitos parâmetros encontrados em seus manuais são idênticos aos presentes nos manuais dos FETs de potência. não apresentando “corrente Miller” na comutação. porém este último possuirá dimensões menores (economia de silício).é a máxima corrente permissível através do componente sob o formato de um pulso. VRRM . O bloqueio pode ser simétrico ou assimétrico (suporta apenas tensões positivas ou também negativas). de 100V a 8KV. como o IGBT. INEP . Entretanto.

Bloquear correntes que ultrapassem este valor pode significar a destruição do componente.MOS CONTROLLED THYRISTOR • Corrente Controlável de Pico. VGA .representa o máximo valor de corrente de catodo bloqueável através do sinal de gatilho. 3 . INEP .5 1.5 2 o 25 C 2.Comparação entre alguns Interruptores de Potência • Tensão Gate-Anodo (pico). ITC . DENSIDADE DE CORRENTE (A/cm2) 1 10 4 N-MCT P-MCT 1000 N-IGBT 100 DARLINGTON 10 N-MOSFET TEMPERATURA: 1 0 0.MCT .o componente permite sobretensões (“overshoot”) durante as transições de bloqueio e disparo.é função da máxima resistência térmica junçãoencapsulamento (0. • Máxima Potência Dissipada. PT .0 1.INSTITUTO DE ELETRÔNICA DE POTÊNCIA 7 .5 QUEDA DE TENSÃO (VOLTS) Fig.6oC/W) e da máxima diferença de temperatura junção-encapsulamento (+125oC).

Com a junção a uma temperatura de 235oC. ele suportou cerca de 100 horas ao teste de vida de bloqueio. suportando dV/dt’s de 10KV/µs a 250oC. Recomenda-se para tanto.MCT . o sinal de gatilho deve enquadrar-se nas áreas sombreadas. INEP .Limites da Forma de Onda da Tensão de Gatilho Durante a ocorrência dos pulsos de comando (amplitude constante) deve-se caracterizar a forma de onda pelas regiões seguras. manter-se continuamente a polarização do gatilho. VGA POSITIVA (VOLTS) (BLOQUEIO) 25 20 15 10 5 0 -5 -10 -15 -20 -25 TEMPO EM us REGIÃO SEGURA MCT EM CONDUÇÃO REGIÃO SEGURA MCT EM CONDUÇÃO REGIÃO SEGURA MCT BLOQUEADO TRANSIÇÃO NEGATIVA (DISPARO) TRANSIÇÃO 0 1 (BLOQUEIO) 2 0 1 (DISPARO) 2 Fig. o MCT operou bloqueando 80A a 300oC. 4 . Segundo testes realizados pelo fabricante (HARRIS) . Nos períodos de transição. O seu funcionamento é mapeado na figura 4.MOS CONTROLLED THYRISTOR OPERAÇÃO Certos cuidados devem ser tomados para a operação com sucesso. Forma de Onda da Tensão de Gatilho O desempenho do MCT está ligado diretamente à forma de onda da tensão de gatilho. que serve como base para a definição de valores de tensão para o circuito de comando.INSTITUTO DE ELETRÔNICA DE POTÊNCIA 8 .

Transição Positiva Para maximizar a capacidade de bloqueio. a corrente será redistribuida nas células internas alcançando valores que impossibilitarão o bloqueio. Permite-se que a tensão alcance os 25V nas transições.MOS CONTROLLED THYRISTOR Amplitude Negativa A tensão limite de -7V na região segura (figura 4) coloca o componente em condução com certo atraso. INEP . Quando o período da transição é reduzido. o que pode ser conseguido variando-se a inclinação da transição negativa da tensão. Isto estabelece 200 ns como limite de tempo para a transição positiva. Transição Negativa Distintamente no MCT. Amplitude Positiva Com a aplicação de tensão gate-anodo positiva. O bloqueio da corrente é conseguido com uma tensão da ordem de 18V com uma duração mínima de 1. Caso o crescimento da tensão ocorra de maneira lenta. ainda na região segura. o MCT é bloqueado e assim permanece. deve-se acionar o gatilho rapidamente. Limita-se em 20V a tensão na região segura a fim de se evitar a destruição por excesso da mesma. o gatilho (valor de tensão) não pode ser usado no controle do tempo de disparo.INSTITUTO DE ELETRÔNICA DE POTÊNCIA 9 . a corrente de deslocamento provocará o disparo com a tensão de gatilho ainda positiva.5 µs. limita o funcionamento normal do MCT sem danificá-lo por tensão excessiva.MCT . A tensão de -20V.

∗ Corrente de pico: superior a 2A. Basicamente três fatores são incisivos na capacidade de comutação: ∗ Tempo de subida da Tensão de Gatilho: para valores superiores ao recomendado anteriormente. Circuitos de Comando Os circuitos de comando destinados ao MCT devem apresentar as seguintes características: ∗ Tensão de Comando de Gatilho: superior a ± 20V.MOS CONTROLLED THYRISTOR Área de Operação Segura de Bloqueio Similarmente a outros interruptores a semicondutor tipo P. ∗ Isolação de Potência: o circuito de comando deve ser fisicamente conectado ao anodo do MCT. ∗ Interface de sinal: isolação ótica ou magnética. INEP . Aconselha-se a aplicação de sobretensão (25 V) durante a comutação para o auxílio do bloqueio. Requer-se isolamento da tensão de barramento e capacidade de suportar dv/dt resultante das comutações. ∗ Tempo de Subida/Descida: < 200ns. a área de operação segura será delimitada abaixo da curva mostrada na figura 5. o P-MCT apresenta limitações na área de operação segura de bloqueio (SOA). ∗ Tensão de Gatilho durante o Bloqueio: a tensão de gatilho deve alcançar e manter os valores anteriormente indicados sob pena da redução da região superior plana da curva.MCT .INSTITUTO DE ELETRÔNICA DE POTÊNCIA 10 . ∗ Tensão VKA de Pico: na região de alta tensão da curva a capacidade de comutação é influenciada por este valor.

5 . Uma opção de circuito de comando implementada e testada por Franklin Miguel [4]. Os circuitos de comando são tipicamente energizados por um transformador e um retificador para prover a isolação CC.Curva de Capacidade de Bloqueio Típica A tensão de gatilho pico a pico requerida limita as escolhas de CI’s que possam comandar diretamente o MCT. O sinal de comando geralmente será acoplado por fibra ótica ou por meio de um optoacoplador.INSTITUTO DE ELETRÔNICA DE POTÊNCIA 11 . é apresentada na figura 6. INEP .MCT .MOS CONTROLLED THYRISTOR o Ik (A) Tj=+150 C. Vg=18V.L=200u 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 -50 -150 -250 -350 -450 -550 VKA (V Fig.

a tensão decresce com a temperatura. Abaixo deste valor o coeficiente é negativo. o circuito deve ser ressonante ou a mesma deve ser conduzida a um nível de comutação segura. 6 . Dependendo da configuração do circuito. Acima do mesmo a queda de tensão em condução aumenta conjuntamente com a corrente.MCT . é vantajoso fixar-se na região de coeficiente positivo. ou seja. denotando um coeficiente de temperatura positivo.3 nF D2 1N4148 RA 470W A RB 330 W CA 22 uF Vin Q3 2N3819 R3 330W D3 1N4148 Q2 BD140 CB 10 uF C2 1 nF D4 1N4148 Fig.INSTITUTO DE ELETRÔNICA DE POTÊNCIA 12 .Sugestão para circuito de Comando Coeficiente de Temperatura da Tensão Um importante aspecto da queda de tensão em condução é o valor de corrente para o qual o coeficiente de temperatura é zero.MOS CONTROLLED THYRISTOR +20V R2 470 W D1 +20V 1N4148 Q1 BD139 RG 1W G +20V R1 540 W C1 3. Do ponto de vista do paralelismo. Para a operação acima da corrente de coeficiente de temperatura zero. pode-se operar acima da capacidade de comutação de pico de um único componente. INEP .

Os melhores IGBTs fabricados atualmente podem superar o “então” P-MCT na velocidade de bloqueio apresentando menores perdas por ciclo de comutação (grosseiramente por um fator 2). a remoção de calor tem impacto significativo no tamanho e na natureza do encapsulamento. diferindo do seu concorrente. No IGBT o disparo é. Comutação O disparo no MCT é iniciado pelo gatilho e completado regenerativamente como um SCR. grande capacidade de di/dt e de picos de corrente. com valores da temperatura da junção em torno de 150oC. aumentando modestamente mesmo em grandes picos de corrente. Apresenta rapidez. as duas estruturas são aplicáveis em circuitos de comutação de potência onde requer-se 600V ou mais. com freqüência. os requisitos de cada circuito específico pode influenciar bastante na comparação. usados também em freqüências de comutação mais altas do que geralmente é praticado com transistores Darlington de potência. INEP .INSTITUTO DE ELETRÔNICA DE POTÊNCIA 13 . Sendo uma “mescla” bipolar/MOS.MOS CONTROLLED THYRISTOR COMPARAÇÃO: MCT VERSUS IGBT Em muitas aplicações. Portanto. com baixas perdas em condução. Em circuitos de alta potência. perdas de comutação e em condução perfazem o primeiro confronto dos citados a seguir: Queda de Tensão em Condução A mais importante característica do MCT é a queda de tensão em condução. Ambos possuem o gatilho isolado. com valores situados de 1/3 a 1/2 dos valores do IGBT.MCT . porém com sacrifício das perdas em condução. são interruptores controlados por campo. intencionalmente lento para controlar a recuperação reversa do diodo de circulação.

Na substituição de um IGBT com perdas de condução de 50W e de comutação de 30W por exemplo. Tensão de Operação Segura de Bloqueio (SOA) A área de operação segura de bloqueio descreve o lugar geométrico das combinações permissíveis de tensão e corrente através do interruptor que não provoque a sua operação indevida. a primeira geração de PMCT pode reduzir pela metade as perdas e a área ativa de silício: um componente menor e mais eficiente. o P-MCT pode ser uma boa escolha. apesar da provável necessidade de um circuito limitador de tensão (geralmente um simples capacitor: “snubber”) para mantê-lo na área de operação segura. ou seja. em freqüências de muitos KHz e abaixo. Na substituição a GTOs e transistores bipolaress. INEP . apresentaria perdas por condução < 25W. dependerá do circuito em questão. contra os 80% do IGBT. Também em circuitos de comutação dissipativa.INSTITUTO DE ELETRÔNICA DE POTÊNCIA 14 .MCT . o lucro seria pequeno: a primeira geração de MCTs tipo P.MOS CONTROLLED THYRISTOR A decisão final a ser tomada para a escolha do componente depende da proporção entre as perdas no chaveamento e em conducão. Para o P-MCT. a corrente nominal de bloqueio é sustentável de 50% a 60% do valor da tensão de ruptura. mas suas perdas de comutação seriam aproximadamente 60W. ele oferece a considerável vantagem do gatilho MOS. O seu uso pode tornar-se desinteressante em circuitos onde as perdas de comutação são equivalentes às perdas de condução. que apresenta uma melhor área de operação segura. ONDE USAR O MCT? Em qualquer circuito dominado por perdas de condução.

Em freqüências de comutação acima de 50Khz na comutação dissipativa e acima de 100Khz na comutação suave. REFERÊNCIAS BIBLIOGRÁFICAS [1]V. pp 1018-1025 (Toledo. particularmente em freqüências acima de 10 Khz. os MOSFETs de potência ainda afirmam-se como a única solução prática no momento (1995). Em circuitos PWM. PET-EEL. PESC 92 Proceedings. Circuitos de descarga de pulso geralmente favorecem o MCT.K. [4] Franklin Miguel.1987 pp 23-29. Com MCTs tipo P o uso de capacitores limitadores ou componentes com valores mais elevados torna-se necessário para a operação nesta mesma faixa. D. “MCT”. 1994.MCT . 1995. INEP . podem torná-lo a solução preferida para tensões contínuas entre 300V e 400V. Spain. [2] V. as baixas perdas de comutação do IGBT sobrepujam as baixas perdas de condução do MCT.“Harris Semiconductor”. a maior tensão na área de operação segura de bloqueio do IGBT de 600V.MOS CONTROLLED THYRISTOR Em circuitos de comutação dissipativa ou PWM.July 3. Arthur et al. cerca de 480V. Nov. 1992) [3] Manual do Fabricante . o MCT ainda não preenche todos as lacunas em eletrônica de potência.. June 29 .INSTITUTO DE ELETRÔNICA DE POTÊNCIA 15 . Apesar de suas características. PCIM. “Power Device Evolution and the MOS-Controlled Thyristor”. Relatório de Estágio. devido à velocidade de disparo e grande capacidade de picos de corrente sob baixa queda de tensão. Temple.A. Temple. “Megawatt MOS Controlled Thyristor for High Voltage Power Circuits”. S.

. . . . . . Absolute Maximum Ratings TC = +25oC. . . . . . . . -600V • VTM = -1. . . . The SCR like forward drop greatly reduces conduction power loss. . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . .063" (1. . They feature the high peak current capability common to SCR type thyristors. . . . . . . . . . . . . . . . . . . . . . . . . .N L BSO SS O MCTV75P60E1. . . . . . . . . . . . . . . . . . . . The MCT is especially suited for resonant (zero voltage or zero current switching) applications. . . . . . . . . . It is designed for use in motor controls. . . . . . . . . . and operate at junction temperatures up to +150oC with active switching. . . . . . . . line switches and other power switching applications. MCTA75P60E1 JEDEC STYLE TO-247 5-LEAD ANODE ANODE CATHODE GATE RETURN GATE 75A. . . . . . . . . . . (0. . . . . . . . . . . . . . . . inverters. . . . . . . . . . . . . . . . . . . . . . VDRM Peak Reverse Voltage . Continuous Cathode Current (See Figure 2) TC = +25oC (Package Limited) . . . use the entire part number.3V(Maximum) at I = 75A and +150oC • 2000A Surge Current Capability • 2000A/µs di/dt Capability • MOS Insulated Gate Control • 120A Gate Turn-Off Capability at +150oC Description The MCT is an MOS Controlled Thyristor designed for switching currents on and off by negative and positive pulsed control of an insulated MOS gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . .Semiconductor April 1999 PRO CE IGNS WN DRA EW DES H T I TW ON PAR ETE . . . . . . . . Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unless Otherwise Specified MCTV75P60E1 MCTA75P60E1 UNITS V V A A A A V V A/µs W W/oC oC oC Peak Off-State Voltage (See Figure 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCTs allow the control of high power circuits with very small amounts of input energy. . . Peak Controllable Current (See Figure 10) . . . . . . . . . . . Users should follow proper ESD Handling Procedures. . . . . . . . Gate-Anode Voltage (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 600V P-Type MOS Controlled Thyristor (MCT) Package Features • 75A. . . . . . . . . . . . . . . . . . . . . . . . . Maximum Pulse Width of 250µs (Half Sine) Assume TJ (Initial) = +90oC and TJ (Final) = TJ (Max) = +150oC CAUTION: These devices are sensitive to electrostatic discharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rate of Change of Voltage . Rate of Change of Current . TC = +90oC . . . . . PART NUMBER INFORMATION PART NUMBER MCTV75P60E1 MCTA75P60E1 PACKAGE TO-247 MO-093AA BRAND MV75P60E1 MA75P60E1 JEDEC MO-093AA (5-LEAD TO-218) ANODE ANODE CATHODE GATE RETURN GATE Symbol G A K NOTE: When ordering. . . . . . TSTG TL -600 +5 85 75 2000 120 ±20 ±25 See Figure 11 2000 208 1. . . . . . . . . . . . Copyright © Harris Corporation 1999 File Number 3374. . . . . Non-Repetitive Peak Cathode Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . .6 2-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Lead Temperature for Soldering . . . . . . . .6mm) from case for 10s) NOTE: VRRM IK25 IK90 IKSM IKC VGA VGAM dv/dt di/dt PT TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 -55 to +150 260 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate-Anode Voltage (Peak) . .

-7V TJ = +125oC VKA = -300V TC = +150oC TC = +25oC TC = +150oC TC = +25oC TC = +150oC TC = +25oC MIN TYP MAX 3 100 4 100 1.0 0.5 1. CATHODE CURRENT (A) 100 PULSE TEST PULSE DURATION .2 1. MCTA75P60E1 Electrical Specifications PARAMETER Peak Off-State Blocking Current TC = +25oC Unless Otherwise Specified SYMBOL IDRM TEST CONDITIONS VKA = -600V. IK = IK90 RG = 1Ω.8 1. VGA = +18V.0 1.4 . DC CATHODE CURRENT (A) 100 90 80 70 60 50 40 30 20 10 1 0. MAXIMUM CONTINUOUS CATHODE CURRENT 2-19 .15 10 .2 0. CATHODE CURRENT vs SATURATION VOLTAGE (TYPICAL) FIGURE 2.4 200 UNITS mA µA mA µA V V nA CISS - 10 - nF Current Turn-On Delay Time Current Rise Time Current Turn-Off Delay Time Current Fall Time Turn-Off Energy Thermal Resistance tD(ON)I - 300 - ns tRI tD(OFF)I - 200 700 - ns ns tFI EOFF RθJC - 1.8 2.0 0 25 35 45 55 65 75 85 95 105 115 125 135 145 155 PACKAGE LIMIT IK. CASE TEMPERATURE (oC) FIGURE 1.6 µs mJ oC/W Typical Performance Curves 300 120 110 IK .6 0.Specifications MCTV75P60E1.6 1.4 0. CATHODE VOLTAGE (V) TC.250µs DUTY CYCLE < 2% TJ = +150oC 10 TJ = TJ = +25oC -40oC VTM. VGA = +18V Peak Reverse Blocking Current IRRM VKA = +5V VGA = +18V On-State Voltage VTM IK = IK90.4 1. VGA = -10V Gate-Anode Leakage Current Input Capacitance IGAS VGA = ±20V VKA = -20V.3 1. TJ = +25oC VGA = +18V L = 200µH.

4 0. TURN-OFF DELAY vs CATHODE CURRENT (TYPICAL) 500 TJ = +150oC. RG = 1Ω.8 1.0 1. TURN-ON ENERGY LOSS vs CATHODE CURRENT (TYPICAL) FIGURE 8. RG = 1Ω.0 10.0 10 20 30 40 50 60 70 80 90 IK .8 TJ = +150oC. TURN-OFF ENERGY LOSS vs CATHODE CURRENT (TYPICAL) 2-20 .0 10 20 30 40 50 60 70 80 90 100 110 120 VKA = -200V VKA = -300V TJ = +150oC. L = 200µH VKA = -300V VKA = -200V FIGURE 6.1 10 20 30 40 50 60 70 80 90 IK. CATHODE CURRENT (A) 100 110 120 FIGURE 5.2 0.8 0.2 VKA = -200V VKA = -300V 300 VKA = -200V 200 VKA = -300V 100 0 10 20 30 40 50 60 70 80 90 IK .0 0. TURN-ON RISE TIME vs CATHODE CURRENT (TYPICAL) TJ = +150oC. L = 200µH TD(OFF)I .6 1. FALL TIME (µs) tRI. CATHODE CURRENT (A) IK.6 1. CATHODE CURRENT (A) 100 110 120 FIGURE 7. L = 200µH 2. CATHODE CURRENT (A) FIGURE 3.2 1. RISE TIME (ns) 1. RG = 1Ω.0 VKA = -300V TJ = +150oC. RG = 1Ω.2 1.0 0. TURN-ON SWITCHING LOSS (mJ) 5.0 10 20 30 40 50 60 70 80 90 IK .8 0.0 1. TURN-OFF FALL TIME vs CATHODE CURRENT (TYPICAL) 20. MCTA75P60E1 Typical Performance Curves (Continued) 500 TD(ON)I .4 0.4 1. L = 200µH 400 tFI . RG = 1Ω. L = 200µH EOFF.MCTV75P60E1.6 0. TURN-OFF DELAY (µs) 2.4 1. CATHODE CURRENT (A) 100 110 120 0. TURN-ON DELAY (ns) TJ = +150oC.6 0. TURN-OFF SWITCHING LOSS (mJ) EON. CATHODE CURRENT (A) 100 110 120 1. RG = 1Ω.0 0. L = 200µH 400 300 VKA = -300V 200 VKA = -200V 100 0 10 20 30 40 50 60 70 80 90 100 110 120 IK.0 VKA = -200V 1. TURN-ON DELAY vs CATHODE CURRENT (TYPICAL) FIGURE 4.

The switching power loss (Figure 10) is defined as fMAX2 • (EON + EOFF). TJ = +150oC CS = 1µF. PEAK CATHODE CURRENT (A) EON = tD(ON) I = 0 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 -50 TJ = +150oC. MCTA75P60E1 Typical Performance Curves (Continued) fMAX .0 dv/dt (V/µs) 1000. L = 200µH 10 TURN-OFF SAFE OPERATING AREA 1 10 -150 -250 -350 -450 VKA . The allowable dissipation (PD) is defined by PD = (TJMAX .MCTV75P60E1. VGA = 18V -725 VDRM. fMAX1 is defined by fMAX1 = 0. CATHODE CURRENT (A) 200 IK .PC) / (EON + EOFF). TJ = +150oC CS = 1µF.0 10000. TJ = +25oC -10 CS = 2µF. TJ = +25oC CS = 2µF. fMAX2 is defined by fMAX2 = (PD . The sum of device switching and conduction losses must not exceed PD.0 10. EON is defined as the sum of the instantaneous power loss starting at the leading edge of the input pulse and ending at the point where the anodecathode voltage equals saturation voltage (VAK = VTM). EOFF is defined as the sum of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the point where the cathode current equals zero (IK = 0). Device delay can establish an additional frequency limiting condition for an application other than TJMAX. 2-21 . Because Turn-on switching losses can be greatly influenced by external circuit conditions and components. PEAK TURN OFF VOLTAGE (V) -550 FIGURE 9. tD(ON) I ≠ 0 VKA = -200V VKA = -300V fMAX1 = 0.1µF. TURN-OFF CAPABILITY vs ANODE-CATHODE VOLTAGE -200 CS = 0. tD(ON)I + tD(OFF)I deadtime (the denominator) has been arbitrarily held to 10% of the on-state time for a 50% duty factor. fMAX curves are plotted both including and neglecting turn-on losses.1 1.PC) / ESWITCH PD: ALLOWABLE DISSIPATION PC: CONDUCTION DISSIPATION (PC DUTY FACTOR = 50%) RθJC = 0. The information is based on measurements of a typical device and is bounded by the maximum rated junction temperature.05 / (tD(ON)I + tD(OFF)I). SPIKE VOLTAGE vs di/dt (TYPICAL) Operating Frequency Information Operating frequency information for a typical device (Figure 9) is presented as a guide for estimating device performance for a specific application.5oC/W 100 IK . Other definitions are possible. tD(OFF)I is important when controlling output ripple under a lightly loaded condition. OPERATING FREQUENCY vs CATHODE CURRENT (TYPICAL) TJ = +150oC. MAX OPERATING FREQUENCY (kHz) 100 EON ≠ 0. TJ = +150oC SPIKE VOLTAGE (V) -100 CS = 0. BREAKDOWN VOLTAGE (V) -700 -675 -650 -625 -600 -575 -550 -525 -500 -475 -450 -425 0.0 FIGURE 10.TC) / RΘJC. A 50% duty factor was used (Figure 10) and the conduction losses (PC) are approximated by PC = (VAK • IAK) / (duty factor/100). TJ = +25oC -1 1 6 11 16 21 26 31 di/dt (A/µs) 36 41 46 FIGURE 11.1µF.05(tD(ON) I + tD(OFF) I) fMAX2 = (PD . tD(OFF)I is defined as the 90% point of the trailing edge of the input pulse and the point where the cathode current falls to 90% of its maximum value. VGA = 18V. The operating frequency plot (Figure 9) of a typical device shows fMAX1 or fMAX2 whichever is smaller at each point.0 100. BLOCKING VOLTAGE vs dv/dt FIGURE 12. Other typical frequency vs cathode current (IAK) plots are possible using the information shown for a typical unit in Figures 3 to 8. tD(ON)I is defined as the 10% point of the leading edge of the input pulse and the point where the cathode current rises to 10% of its maximum value.

7kΩ IK + FIGURE 13. 4. If gate protection is required an external zener is recommended. with a metallic wristband. 6.The gates of these devices are essentially capacitors. VSPIKE TEST WAVEFORMS Handling Precautions for MCT's MOS Controlled Thyristors are susceptible to gate-insulation damage by the electrostatic discharge of energy through the devices. Gate Protection . When devices are removed by hand from their carriers. VSPIKE TEST CIRCUIT MAXIMUM RISE AND FALL TIME OF VG IS 200ns VG 10% 90% VG di/dt -VKA 90% IK VSPIKE VTM IK 10% tD(OFF) I tF I tR I tD(ON) I VAK FIGURE 15. the hand being used should be grounded by any suitable means .Never exceed the gate-voltage rating of VGA. These conditions can result in turn-on of the device due to voltage buildup on the input capacitor due to leakage currents or pickup. Devices should never be inserted into or removed from circuits with power on. 2. SWITCHING TEST WAVEFORMS FIGURE 16. 2-22 . When handling these devices.for example.These devices do not have an internal monolithic zener diode from gate to emitter. SWITCHING TEST CIRCUIT FIGURE 14. Gate Voltage Rating . † Trademark Emerson and Cumming. MCT's can be handled safely if the following basic precautions are taken: 1. Exceeding the rated VGA can result in permanent damage to the oxide layer in the gate region. Inc. care should be exercised to assure that the static charge built in the handler's body capacitance is not discharged through the device. all leads should be kept shorted together either by the use of metal shorting springs or by the insertion into conductive material such as *“ECCOSORB LD26” or equivalent.MCTV75P60E1. 7. 3. Prior to assembly into a circuit. 5. MCTA75P60E1 Test Circuits 200µH VG RURG8060 + - IK VK + DUT 20V 10kΩ CS DUT + - 500Ω VA 9V - 4. Gate Termination . Tips of soldering irons should be grounded. Circuits that leave the gate open-circuited or floating should be avoided.

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