# CIT-EEE-09EE48-LAB MANUAL –EXP NO: 11

EXPERIMENT NO : DATE :

DESIGN OF HALF / FULL ADDER, HALF / FULL SUBTRACTOR AND PARALLEL ADDER/SUBTRACTOR

Aim:

To realize half/full adder, half/full subtractor and parallel adder/subtractor using logic gates.

Components required:

Sl. No. 1. 2. 3. 4. 5. 6. 7. 8. 9. NAME OF THE APPARATUS RANGE 330 ohms QUANTITY 1 1 1 1 1 5 5 1 1set

**IC 7486 IC 7408 IC 7432 IC 7404 IC 7483
**

LED Resistors Bread board Connecting wires

.

**Half Adder using basic gates:
**

A combinational circuit that performs the addition of two bits is called half adder. It produces two outputs namely sum and carry. If A and B are the assigned inputs, then the Sum S=A xor B Carry C= A and B Circuit diagram:

1

CIT-EEE-09EE48-LAB MANUAL –EXP NO: 11
Truth Table: A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 C 0 0 0 1
Full Adder using basic gates: A full adder is a combinational circuit that forms the arithmetic sum of three bits. Third input. Two of the input variables. represent the two significant bits to be added. Cn-1. The two outputs are designated by the symbols S for sum and C for carry. represents the carry from the previous lower significant position. It consist of three inputs and two outputs.
Circuit diagram:
2
. denoted by A and B.

CIT-EEE-09EE48-LAB MANUAL –EXP NO: 11
Truth Table: Cn-1 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 C 0 0 0 1 0 1 1 1
Half Subtractor using basic gates:
Half subtractor is the circuit used to subtract two binary bits. The outputs are represented by D which is the difference and Bor which is the borrow. It consists of two inputs namely A and B.
Circuit diagram:
Truth Table:
A 0 0 1 1 B 0 1 0 1 D 0 1 1 0 Bor 0 1 0 0
3
.

denoted by A (minuend) and B (subtrahend). represent the two significant bits to be subtracted. The two outputs are designated by the symbols D for difference and Bor for borrow. represents the carry from the previous the next significant position. Cn-1.CIT-EEE-09EE48-LAB MANUAL –EXP NO: 11
Full Subtractor using basic gates:
A full subtractor is a combinational circuit that forms the arithmetic subtraction of three bits. Two of the input variables. Third input .
Circuit diagram:
Truth Table:
Cn-1 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 Bor 0 1 0 0 1 1 0 1
4
. It consists of three inputs and two outputs.

CIT-EEE-09EE48-LAB MANUAL –EXP NO: 11
Parallel adder using 7483:
Parallel adder is implemented using IC 7483. Added output is denoted by and carry out C4 represents the carry out. Pin Detail:
Circuit Diagram:
`
5
. The resultant output will be the 4 bit added output and a carry out . It can be used to add two 4 bit number along with the input carry. the addend and carry input C0 are the inputs .The augend .

In this subtraction is done using 1’s complement technique. Output obtained is denoted by and C4 represents the carry out. subtrahend is 1’s complemented and fed to the IC 7483. The required result is interpreted in such a way that if i) the carry Cout is 1 then the required output is 1 added to the lsb of ii) the carry Cout is 0 then the required output is the –(1’s complement of )
Circuit Diagram:
6
. The minuend . the subtrahend and carry input C0 are the inputs . By 1’s complement technique.CIT-EEE-09EE48-LAB MANUAL –EXP NO: 11
Truth Table:
A4 0 0 1 1 A3 0 1 0 1 A2 0 0 1 1 A1 1 1 0 1 B4 0 1 1 1 B3 0 0 0 1 B2 1 1 1 1 B1 0 1 0 1 C4 0 1 1 1 S4 0 0 1 1 S3 0 0 1 1 S2 1 0 0 1 S1 1 0 0 0
Parallel subtractor using IC7483:
Parallel subtractor can also be implemented using IC 7483. It can be used to subtract two 4 bit number along with the input carry.

3. How can you implement full adder using half adder and or gate? 4.
7
. half/full subtractor and parallel adder/subtractor are designed and their outputs are verified with their truth table. What is overflow in a adder circuit? Mention its significance. How can a 4 bit adder be implemented using full adder? 5. Give some examples for combinational circuit.CIT-EEE-09EE48-LAB MANUAL –EXP NO: 11
Truth Table:
A4 A3 A2 A1 B4 B3 B2 B1 C4 (Cout) 1 1 0 1 S4 S3 S2 S1
0 0 0 1
0 1 0 0
1 0 1 1
0 1 1 0
0 0 0 0
0 0 1 1
0 1 0 1
1 1 1 0
0 0 1 0
0 0 1 0
0 0 0 1
0 1 1 1
Output obtained S4 0 0 1 0 S3 0 0 1 0 S2 0 0 0 1 S1 0 1 1 1 Sub3 0 0 0 0
Interpreted Output Sub2 0 0 0 1 Sub1 0 1 1 0 Sub0 0 0 0 0
Viva Questions: 1.
Result: Thus half/full adder. What are the universal gates? Why is it so called? 2.