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BCD TO 7-SEGMENT DISPLAY

1. INTRODUCTION

A seven segment is generally available in ten pin package. While eight pins correspond to the eight LEDs, the remaining two pins (at middle) are common and internally shorted. These segments come in two configurations, namely, Common cathode (CC) and Common anode (CA). In CC configuration, the negative terminals of all LEDs are connected to the common pins. The common is connected to ground and a particular LED glows when its corresponding pin is given high. In CA arrangement, the common pin is given a high logic and the LED pins are given low to display a number. Find out more information about a seven segment display and its working. Diagram:

Fig (i): seven segment display

Displaying letters

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LED-based 7-segment display which cycles through the common glyphs of the ten decimal numerals and the six hexadecimal "letter digits" (AF) Hexadecimal digits can be displayed on seven-segment displays. A particular combination of uppercase and lowercase letters are used for AF; this is done to obtain a unique, unambiguous shape for each letter (otherwise, a capital D would look identical to an 0 and a capital B would look identical to an 8). Also the digit 6 must be displayed with the top bar lit to avoid ambiguity with the letter b)

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2. HARDWARE DETAILS

2.1 HELIUM USER MANUAL

BOARD DETAILS:

(fig2 :Board details of CPLD)

Initial Board Settings:


Two jumpers need to be set on the board prior to setup. 1. PWRSEL: The power select jumper. It is located close to the USB connector on the board. PINS Pins 1 & 2 Pins 2 & 3
(Table 1 : PWRSEL)

MODE Externally powered USB powered

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The connector for the external supply can be found close to the to the PWRSEL jumper with the power polarities indicated.

2. CKSEL: The clock select jumper. It is located close to the CPLD. PINS Pins 1 & 2 Pins 2 & 3 (Table 2: CKSEL) MODE Onboard clock External clock

The connector for the external clock (ECLK) can be found close to the to the CKSEL jumper.

INSTALLING THE DRIVERS: 1. Plug in the USB connector to both the board and the PC. The board would be powered ON and the power LED should glow. 2. The Found new hardware wizard will open, which prompts a dialog-box. Select No, not this time and click Next. 3. Select Install from a specific location, and click next. 4. Navigate to the folder containing the CDM drivers. The drivers are provided on the CD and are also available on FTDIs website. 5. The drivers will be installed. 6. This process will run four times- one each for Serial Converter A, B, and twice for the two serial ports.

USING ALTERA QUARTUS: 1. Create a new project from File New Project Wizard. 2. The project name and the top level design entity should have the same name. 3. Follow the onscreen instructions to create a new project. An existing VHDL/ Verilog file can be added to the project if a program file has been already written or else, it may be left blank if you wish to create a new VHDL/ Verilog file in the current project directory. 4. Select the programmable device family as MAX3000A, and EPM3064ALC44-10N from the device list that shows up.

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5. Open a new VHDL/ Verilog file and write the program, in case a new file is to be complied. 6. Compile the design and rectify errors, if any. 7. Once the design is compiled, you can choose what pins to assign as input/output from Pin Planner under the Assignments tab in the Menu bar. Refer to the last section for the I/O pin configuration. 8. Re-run the compiler and make sure that there are no errors. 9. To generate the .svf file, select Programmer under the Tools tab in the Menu bar. Check if the device EPM3064ALC44-10N is recognized in the programmer window. 10. Select the file type as .svf and click Generate.

PROGRAMMING THE CPLD: 1. Open the JTAG shell in the UrJTAG folder. In case the JTAG shell doesnt start and reports an error saying the libusb.dll missing, copy the file from the CD and past it in the system32 folder in the Windows directory. This should solve the error. 2. At the command prompt, type cable ft2232. You will get a message saying connected to libd2xx. 3. The detect command should identify the CPLD device and display its signature. 4. In case you have other devices connected to the JTAG chain, you can choose the appropriate device by specifying the corresponding part number. This is optional in this case, as only one device is present in the JTAG chain. Since the CPLD is the only device in the JTAG chain, you can select it by typing the part 0 command. 5. Type svf<svf file location> on the command prompt. The file will now be loaded, and the output of the VHDL/ Verilog program may be observed on the board.

(fig 3:Programming CPLD)

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I/O configuration:
The pins which have been configured as input and output on the board are as follows:

(Table 3 : I/O configuration)

External I/O:
The following pins are available for interfacing the board with external hardware. PIN 16, 18, 19, 20, 21, 34, 37, 39, 40 and 41. It is recommended to use external power supply when interfacing external hardware to the board.

Clock:
For using the onboard clock, map your clock input to pin 43 of the CPLD which is the Global Clock of the CPLD.

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2.2 PIN DIAGRAM

(Fig 4 : Pin Diagram of MAX 3000A )

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2.3 LOGICAL DIAGRAM

(fig 5 : Logical Diagram)

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3. SOFTWARE DETAILS

QUARTUS II

The Quartus II system includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system. This tutorial makes use of the VHDL design entry method, in which the user species the desired circuit in the VHDL hardware description language. Two other versions of this tutorial are also available; one uses the Verilog hardware description language and the other is based on dening the desired circuit in the form of a schematic diagram. The last step in the design process involves conguring the designed circuit in an actual FPGA device. To show how this is done, it is assumed that the user has access to the Altera DE2 Development and Education board connected to a computer that has Quartus II software installed. A reader who does not have access to the DE2 board will still nd the tutorial useful to learn how the FPGA programming and conguration task is performed.

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3.1 VHDL Code


library ieee; use ieee.std_logic_1164.all; entity bcd27seg is port(bcd:in std_logic_vector(3 downto 0); seg: out std_logic_vector(6 downto 0)); end bcd27seg; architecture design of bcd27seg is begin process(bcd) begin case bcd is when 0000=>segment<=1111110; when 0001=>segment<=0110000; when 0010=>segment<=1101101; when 0011=>segment<=1111001; when 0100=>segment<=0110011; when 0101=>segment<=1011011; when 0110=>segment<=1011111; when 0111=>segment<=1110000; when 1000=>segment<=1111111; when 1001=>segment<=1111011; when others=>segment<=0000000; end case; end process; end design;

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3.2 Truth Table

input
A 0 0 B C D

output a b c d e f 0 0 g 0 1

Digit

0 0

0 0 0 1 1 0 1 1 1 0

0 0 1 1

1 2 3 4 5 6 7 8 9

0 0 1 0 1 1 1 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1
(Table 4 : Truth table)

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4. APPLICATIONS

Seven segment displays can be used to show various other letters of the Latin, Cyrillic and Greek alphabets including punctuation, but few representations are unambiguous and intuitive at the same time. Short messages giving status information (e.g. "no disc" on a CD player) are also commonly represented on 7-segment displays. In the case of such messages it is not necessary for every letter to be unambiguous, merely for the words as a whole to be readable. Similar displays with fourteen or sixteen segments are available allowing less-ambiguous representations of the alphabet. Using a restricted range of letters that look like (upside-down) digits, seven-segment displays are commonly used by school children to form words and phrases using a technique known as "calculator spelling".

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5. REFERENCES

1. Modern Digital Electronics (Director-B M Institute of Engineering and Technology,Sonepat) 2. Digital System Design-2 ( Morres Mano ) 4. www.electrofriends.com/source-codes/digital-electronic 5. Helium v1.0 User manual Virtual Labs, IIT Bombay (Wadhwani Electronics Lab) 6. www.altera.com/literature/manual/archives/intro_to_quartus2.pdf

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