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Chapter 2: OpAmp Basic Stages
2.1 Introduction
An integrated circuit IC is a circuit where an entire circuit is constructed on a single piece of
semiconductor material. One of the commonly used types of IC is the operational amplifier.
The schematic diagram of the 741type OPAmp and its symbol is shown below.
Inverting Input
Non Inverting
Input
V
ee
V
cc
Output
+

Operational Amplifier is a high gain dc differential amplifier capable of performing a wide
range of functions by using external feedback. It is the most flexible linear device. By
controlling the feedback network properties, we can manipulate the overall forward transfer
function of the device and its application.
The majority of commercially available operational amplifiers employ the structure shown
below.
Bias Network Differential Amp
Gain Stage
Level Shifter
Output Stage
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DiffAmp Additional Gain
Buffer & Level
Shifter
Output Deriver
V1
V2
VO
The differential amplifier is used as the input stage to provide the inverting and the non
inverting inputs and the high input resistance as well as voltage gain. The low output
resistance of the opamp is achieved by the emitter follower output stage. The level shifter
adjusts the dc voltages so that the output voltage signal is referenced to ground. The
adjustment of dc level is required because the gain stages are direct coupled. The input and
output stages are required to match the opamp with the external world.
2.2 Differential Amplifiers
Previously in Applied electronics I, we have discussed single stage amplifiers of one input
and one output terminal with limited gain, input resistance and output resistance. Here,
another basic transistor circuit configuration called differential amplifier is introduced,
which can give us high gain and specified input and output resistance values. It is the input
stage for most operational amplifiers and is widely used amplifier building block in analogue
integrated circuit. Unlike the other amplifiers we have discussed so far, it has two input
terminals and one output terminal, where the output signal is the difference of the two input
signals as shown in the difference amplifier block diagram below.
Difference
Amplifier
V
2
V
1
V
O
Figure 2.1: Difference amplifier block diagram
Where the output voltage V
O
There are two different modes of operation of the differential pair:
is given by:
(
1
2
)
1. The differential pair with a commonmode input signal CM:
=
1
+
2
2
2. The differential pair with a differential (mode) input signal:
=
1
2
Thus, the total output voltage is given by
(
1
2
) +
1
+
2
2
Where
and
respectively are the differential gain and the common mode gain.
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The above equations shows that if V
1
=V
2
, the differential mode input signal is zero and the
common mode input signal is V
cm
= V
1
= V
2
The differential amplifier can be implemented with BJ Ts and FETs. We focus on differential
amplifiers implemented using BJ T transistors.
.
2.2.1. Response for differential inputs
Differential mode: This mode of operation exists when the differential amplifier has one
source connected to each input and the two sources are out of phase with each other and of
the same amplitude.
Common mode: This exists if the sources are equal in amplitude and in phase, the two
opposing forces will balance each other, so that they cancel.
Consider the following basic BJ T differential pair configuration
V
B1
V
B2
I
Q1 Q2
i
C1 i
C2
V
C1 V
C2
V
CC
R
C1
R
C2
i
E2
i
E1
V
out
 +
V
EE
Figure 2.2: Basic BJ T differential pair configuration
Following the polarity shown in figure 2.2, the ac output voltage can be expressed as:
=
2
1
The output voltage V
out
Common mode response
is called a differential output since it combines the two ac collector
voltages into one voltage.
First let us consider a circuit in which the two base terminals are connected together and a
common mode voltage V
cm
The voltage at the common emitters is given by KVL in one of the transistor input circuit:
is applied as shown in figure 2.3 below.
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() 2.1
If the transistors Q
1
and Q
2
are identical, the current I
Q
If base currents are negligible then,
1
1
2
2
,
splits evenly between the two
transistors and is given by:
1
=
2
=
2
2.2
Therefore, the collector voltages are given by:
1
=
=
2
2.3
Q1 Q2
V
CC
R
C1
R
C2
+

Vcm
2
Q
I
2
Q
I
Q
I
1 1
2
C
Q
CC C
R
I
V V =
2 2
2
C
Q
CC C
R
I
V V =
2
Q
I
2
Q
I
V
E
V
EE
Figure 2.3: Basic diffamp with applied common mode voltage
From this we conclude that, for an applied common mode voltage,
1
=
2
2
=
2
2.4
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This show the voltages at the bases of Q
1
and Q
2
are no longer equal. Since the emitters are
common, the base to emitter voltages of Q
1
and Q
2
are not the same. We have increased V
B1
and decreased V
B2
, giving us V
BE1
>V
BE2
, as a result i
C1
increases by I above its quiescent
value and i
C2
Q1 Q2
V
CC
R
C1
R
C2
I
I
Q
+
2
I
I
Q
2
Q
I
(
(


.

\

+ =
1 1
2
C
Q
CC C
R I
I
V V
(
(


.

\

=
2 2
2
C
Q
CC C
R I
I
V V
I
I
Q
+
2
I
I
Q
2
V
E
V
EE
2
d
v
2
d
v
+
+
  1 BE
V 2 BE
V
decreases by I below its quiescent value. This is shown in figure 2.4 below.
Figure 2.4: Basic differential amplifier with applied differential mode
Hence, there exists a potential difference between the two collector terminals which is given as
follows:
2
1
=
2
2
2
+
1
=
2
+
1
,
1
=
2
=
2
1
= 2
2.5
This proves that a voltage difference is created between the two collector terminals (V
C2
and
V
C1
2.2.2. Small signal analysis
) by applying a differential mode input voltages.
Consider the following small signal circuit configuration.
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V
B1
V
B2
R
i1
R
i2
V
1 V
2
R
C1
R
C2
g
m1
V
1
g
m2
V
2
E
+

+

Figure 2.5: Small signal model of bipolar pair
Take the requirement that the input signals do not affect the bias currents of transistors Q
1
and Q
2
For differential operation V
significantly. I.e. both transistors must exhibit approximately equal trans
conductance. And for small differential inputs the tail node maintains constant voltage (which
results in a state called virtual ground).
B1
and V
B2
represent small changes in each input and they should
satisfy V
B1
= V
B2
Note: The emitter current source I
.
Q
To analyse the small signal operation let us take KVL around the input network and KCL at
node E.
is replaced with an open circuit.
1
1
=
=
2
2
2.11
1
+
1
1
+
2
2
+
2
2
= 0 2.12
Let R
i1
= R
i2
and g
m1
= g
m2
Since V
, then equation 2.12 yields:
1
=
2
B1
=  V
B2
This would result in:
=
1
1
= 0
, equation 2.11 will become:
2
1
= 2
1
Thus, for small signal analysis of the circuit the emitter voltage remains constant if the two
inputs vary differentially and by a small amount.
With the assumption taken to analyse the above circuit and the result obtained, node E can be
shorted to ac ground reducing the differential pair of figure 2.5 to two half circuits, with each
half resembling common emitter stage as shown in figure 2.6 below.
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V
B1
V
B2
R
i1
R
i2
V
1 V
2
R
C1
R
C2
g
m1
V
1
g
m2
V
2
+

+

Figure 2.6: Simplified small signal model
With this simplified model, we can write:
1
=
1
1
2.13
Substituting for V
1
= V
B1
, g
m1
=g
m2
=g
m
and R
C1
= R
C2
= R
C
Then, the differential voltage gain of the differential pair is:
=
1
2
1
2
=
1
2
2.15
,
1
=
2.14()
2
=
2.14()
Common mode gain (A
C
The small signal equivalent model for the common mode signal is:
)
R
i1
R
i2
V
1 V
2
R
C
R
C
g
m1
V
1
g
m2
V
2
E
+

+

V
O1
+

V
cm
V
O2
+

Figure 2.7: Small signal pair of common mode circuit
The common mode gain A
c
of transistor Q
1
in the above common mode circuit is given by:
=
1
=
1
,
1
=
2
=
2.16
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This results to:
=
1
1
2.17
By symmetry of the two transistors the total gain of common mode pair is zero.
V
cm
R
i1
V
1
R
C1
g
m1
V
1
+

2R
E
Figure 2.8: Small signal model for the common mode circuit when Re is added
But if an emitter resistor is connected to the emitter node E of the above figure 2.8, the one sided gain
A
C
For large values of and dividing by R
is simply given by:
=
1
=
1
1
+ 2(1 +)
(
1
)
=
1
2(1 +)
+
1
2.18
Because the same signal is applied for Q
i1
1
2
+ 1
1
2
, 2
1 2.19
1
and Q
2
both V
o1
and V
o2
are out of phase with V
cm
2.2.3. Common mode rejection ratio (CMRR)
.
It is defined as the ratio between the differential gain and the common mode gain, indicates
the ability of the amplifier to accurately cancel voltages that are common to both inputs.
=
For an ideal diffamp A
c
For the differential amplifier shown in figure 2.2 the one sided differential and common
mode gains are given by:
is zero and CMRR goes to infinite.
, = 20 log
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2
And
=
1
2(1 + )
+
1
Using these equations the CMRR can be expressed as:
=
=
1
2
2(1 +)
1
+1 2.20
The common mode gain decreases as
increases.
Hence, the higher the differential gain with respect to the common mode gain, the better the
performance of the diffamp in terms of the rejection of the common mode signals.
Example 1:
Determine the differential and common mode gains of the diffamp for the figure 2.2, with
parameters
= 10,
= 10, = 0.8,
= 25, and again take the assumption that the source resistance of each
transistor is zero.
Solution:
From equation 2.15, the differential mode gain for the one sided output is
1
2
,
1
=
1
1
,
1
=
1
1
,
1
=
1
Therefore,
1
2
,
1
=
1
1
2
,
1
=
2
1
4
Substituting the values of
1
and and taking
= 26, we get
=
0.8 12
4 0.026
= 92.3
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From equation 2.18, the common mode gain is
=
1
2(1 + )
+
1
Rewriting the above equation and using
=
1
2(1 + )
+ 2
=
100 0.8 12
2(1 +100)25 +2 100 26mV
= 0.237
As it is seen in the above result, the common mode gain is significantly less than the
differentialmode gain, but it is not zero because our current source is not ideal.
And the CMRR is given by
=
=
92.3
0.237
= 389
Expressing this in decibel,
= 20 log
10
389 = 51.8
The CMRR of diffamp can be improved by increasing the current source output resistance.
Input and output impedances
For the differential pair configuration and its equivalent model shown in figure 2.9 below, we
can write the input impedance as follows:
1
=
=
2
2
And also we have from KVL loop between V
1
, node E and V
2
From this it follows that
= 2
1
:
=
1
2
,
1
=
2
= 2
1
This implies that as if the two base emitter junctions appear in series. And hence, the result is
called the differential input impedance of the circuit.
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Q
1
Q
2
V
CC
R
C
R
C
Q
I
V
E
I
X
V
X
R
i1
R
i2
V
1 V
2
R
C
R
C
g
m1
V
1
g
m2
V
2
E
+

+

V
X
I
X
I
X
Figure 2.9: Method for calculation of differential input impedance and its equivalent model.
The output impedance for the differential mode is 2R
C
. But if R
C
is derived from an active
load, the output resistance r
o
of the BJ T cannot be ignored rather it must be included as given
below:
= 2(
//
)
Example 2:
The differential amplifier of figure example 2, shown below uses transistors with B=100.
Evaluate the following:
a. The input differential resistance
b. The overall differential gain
1
=
2
=
=
25
0.5
= 50
The input differential resistance can now be found as:
= 2( +1)(
) = 2(101)(50 +150)
= 40
b. The voltage gain from the signal source to the bases of Q
1
and Q
2
=
40
40 +5 +5
= 0.8
is:
The voltage gain from the bases to the output is
=
=
2
2(
)
=
2 10
2(50 +150)
= 50
The overall differential voltage gain can now be found as
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= 0.8 50 = 40
c. Assuming perfect symmetry, except mismatch in the collector resistances, the
common mode gain is given by:
Where
= 0.02
=
10
2 200
0.02 = 510
4
d.
= 20 log
10
= 20 log
10
40
510
4
= 98
Input Offset voltage of the differential pair
Consider the basic BJ T differential pair with both input grounded, as shown in figure 2.10
below.
I
Q1 Q2
i
C1 i
C2
V
CC
R
C1 R
C2
i
E2 i
E1

+
V
O
I
Q1 Q2
i
C1 i
C2
V
CC
R
C1 R
C2
i
E2 i
E1
 +
0V
+

V
OS
(a)
(b)
Figure 2.10: (a) The BJ T differential pair with both input grounded, (b) Application of the
input offset voltage V
OS
As we have seen until now, if the two sides of the differential pair were perfectly matched,
the current I would split evenly in both sides and V
.
O
would be zero. But practical circuits
exhibit mismatches that result in a dc output voltage V
OS
, even with both inputs grounded.
We call V
O
To obtain the input offset voltage V
the output dc offset voltage.
OS
we divide V
O
by the differential gain A
d
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If we apply a voltage  V
OS
The factors which contribute to the dc offset voltage of bipolar differential amplifier are
mismatches in load resistors (R
between the input terminals of the differential amplifier, then the
output voltage will be reduced to zero as shown in figure 2.10(b).
C1
and R
C2
), from junction area, and other mismatches in Q
1
and Q
2
2.3. Constant Current Sources
.
Frequently in practice, Re is replaced by a transistor circuit. They are widely used as emitter
sources for differential amplifiers and also to bias transistors. Now lets consider the circuit
shown below.
Q1 Q2
V
CC
R
C
R
C
3
I
I
B1
V
B1
V
B2
V
EE
R
1
R
3
R
2
I
E2 I
E1
I
O
D
Q
3
R
S1
R
S2
I
C1
I
C2
+
 1 BE
V
+

2 BE
V
I
B2
V
O1
V
O2
+

+

V
S2
V
S1
Figure 2.13: Differential amplifier with constant current stage in the emitter circuit
On figure 2.13 Q
3
Now applying KVL to the base of Q
acts as a constant current source.
3
3
=
1
1
+
2
+
1
+
2
3
:
3
+
3
=
+(
)
2
1
+
2
If the circuit parameters are chosen so that
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1
+
2
=
3
3
(
1
+
2
)
Since this current is independent of the signal voltages, then Q
3
acts to supply the diffamp
consisting of Q
1
and
Q
2
with the constant current I
O
2.4. Current Mirror
.
The principle of a current mirror is that a current fed in at the input of the current mirror
circuit will produce an identical value of current in the second.
Lets consider the following current mirror circuit.
V
O
Q
3
Q
4
I
I
C


.

\

+
1
1
C
I
C
I 2
C
I
C
I


.

\

+
1
1
C
I
I
O
=I
C
+

V
BE
Figure 2.14: BJ T current mirror
If is sufficiently high, so that we can neglect the base currents, the reference current I is
passed through the diode connected transistor Q
3
and thus establishes a corresponding
voltage V
BE
, which in turn is applied between base and emitter of Q
4
. Hence, if Q
3
is
matched with Q
4
, the collector current of Q
4
will be equal to that of Q
3
However, for finite transistor, if transistors Q
; i.e.
=
3
and Q
4
are matched and have the same V
BE
Then, a node equation at the collector of Q
,
their collector currents will be equal i.e
3
Since
+
2
1 +
2
O
Now, consider the following circuit which employs a symmetrical differential pair Q
and the reference current I is given by:
1 +
2
=
1
1 +
2
1
andQ
2
along with a current mirror load Q
3
and Q
4
.
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Q
1 Q
2
V
CC
I
Q
3
Q
4
V
B1
V
B2
V
out
+

V
EE
2
d
m
v
g
2
d
m
v
g
2
d
m
v
g
Figure 2.15: Differential pair with active load
The current mirror active load is a way to accomplish high gain for a single stage differential
amplifier. The NPN transistors Q
1
and Q
2
shown in figure 2.15 above make up the
differential amplifier and Q
3
and Q
4
Darlington Connection
(PNP) make up the current mirror. The current mirror
acts as the collector load and provide a high effective collector load resistance, increasing the
gain.
If we connect two transistors together as shown below then it is called Darlington pair. It
behaves like a single transistor with an effective current gain approximately equal to the
product of the current gains of the two transistors. The base emitter on voltage of the pair is
twice the base emitter on voltage of a single transistor and the saturation voltage is greater
than that of a single transistor by an amount equal to the base emitter on voltage. If a small
signal Ii is input to the base, the collector current of transistor Q1 is
1
. The latter becomes the base current of transistor Q2 and hence the
collector current of Q2 is
2
(
1
+1)
2
(
1
+1)
+
1
Therefore, this circuit can be very useful in high current stages where a large gain is required.
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B
C
E
Q1
Q2
Figure 2.16: Darlington circuit
2.5. Level Shifter and Buffer Circuits
In integrated circuits the use of coupling capacitors is always avoided and to offset any direct
voltage level present between say, two amplifier stages, different methods are employed. One
of these methods is to use an emitter follower that can serve as a voltage shifter as shown in
the following figures.
V
i
R
1
R
2
V
O
V
CC
(a)
V
i
R
1
V
O
V
CC
(b)
I
O
V
i
R
2
V
O
V
CC
(c)
+

V
Z
Figure 2.14: Level shifter circuits
If the output
0.7. If
this shift is not sufficient, the output may be taken at the junction of two resistors in the
emitter leg (a). The voltage shift is then increased by the drop across R
1
. The disadvantage
with this arrangement is that the signal voltage suffers attenuation
2
1
+
2
. This difficulty is
avoided by replacing R
2
by a current source I
O
An avalanche diode can also be used to translate a voltage (c). Then the shift will be
= (
= (
1
)
and there is no ac attenuation for a very high resistance current source.
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2.6. Output Driver Circuits
An output voltage must be capable of supplying the load current and must have a low output
resistance. A common configuration for the output stage of an op amp is the emitter follower
with complementary transistors. If the input signal V
i
goes positive the npn transistor Q
1
acts as a source to supply current to the load R
L
and the pnp transistor Q
2
is cutoff. On the
other hand, if V
i
becomes negative, Q
1
is cutoff and Q
2
acts as a sink to remove current from
the load, that is to decrease I
L
R
L
Q
1
Q
2
+V
CC
npn
pnp
I
L
V
CC
V
i
V
O
.
Figure 2.15: Complementary class B emitter follower output stage