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IntroductiontoMultigateMOSFETs

TsuJaeKingLiu
DepartmentofElectricalEngineeringandComputerSciences
UniversityofCalifornia,Berkeley,CA947201770USA
October3,2012
6
th
AnnualSOIFundamentalsClass
MOSFETFundamentals
Sisubstrate
Gate
Source Drain
GATELENGTH,L
g
GATEOXIDETHICKNESS,T
ox
0.25micronMOSFETXTEM
http://www.eetimes.com/design/automotivedesign/4003940/LCDdriverhighlyintegrated
MetalOxideSemiconductor
FieldEffectTransistor:
2
MOSFETOperation:GateControl
CurrentbetweenSourceandDrain
iscontrolledbytheGatevoltage.
gateoxide
P N+
Gate
N+
NchannelMOSFET
crosssection
Desired
characteristics:
HighONcurrent
LowOFFcurrent
ElectronEnergyBandProfile
i
n
c
r
e
a
s
i
n
g

E
distance
n(E) exp(E/kT)
Source
Drain
V
DD
I
ON
I
OFF
Inverseslopeis
subthreshold swing,S
[mV/dec]
log I
D
increasing
V
GS
V
TH
GATEVOLTAGE
0
L
eff
Nchannel&PchannelMOSFETs
operateinacomplementarymanner
CMOS=ComplementaryMOS
Source Drain Body
3
inv D
Q v W I =
DRAINVOLTAGE,V
DS
D
R
A
I
N

C
U
R
R
E
N
T
,

I
D
q
) (
TH GS ox inv
V V C Q
eff
v
Substrate
Gate
Source Drain
MOSFETinONState(V
GS
>V
TH
)
4
velocity inversionlayerchargedensity width
mobility
gateoverdrive
gateoxide
capacitance
CMOSDevicesandCircuits
0 1
1 0
STATICMEMORY(SRAM)CELL
D S
G
D
S
G
CIRCUITSYMBOLS
Nchannel
MOSFET
Pchannel
MOSFET
GND
V
DD
S
S
D
D
CMOSINVERTERCIRCUIT
V
IN
V
OUT
V
OUT
V
IN
0
V
DD
V
DD
INVERTER
LOGICSYMBOL
BITLINE
WORDLINE
BITLINE
CMOSNANDGATE
NOTAND(NAND)
TRUTHTABLE
5
or or
M.H.Naetal.,IEDMTechnicalDigest,pp.121124,2002
NMOSDRAINVOLTAGE=V
OUT
V
IN
=V
DD
V
IN
=0.83V
DD
V
IN
=0.75V
DD
V
IN
=0.5V
DD
N
M
O
S

D
R
A
I
N

C
U
R
R
E
N
T
I
H
I
L
V
DD
0.5V
DD
I
DSAT
V
2
I
H
(DIBL=0)
I
EFF
=
I
H
+I
L
2
t
pHL
t
pLH
V
1
TIME
V
DD
V
DD
/2
V
1
V
2
V
3
CMOSinverterchain:
GND
V
DD
S
S
D
D
V
IN
V
OUT
V
3
EffectiveDriveCurrent(I
EFF
)
6
logI
D
V
GS
V
DD
I
ON
ThegreaterthecapacitivecouplingbetweenGateandchannel,the
bettercontroltheGatehasoverthechannelpotential.
Body
Gate
Drain
C
ox
C
dep
higherI
ON
/I
OFF
forfixedV
DD
,orlowerV
DD
toachievetargetI
ON
/I
OFF
reduceddraininducedbarrierlowering(DIBL):
Source
Source
Drain increasing
V
DS
ox
total
C
C
S
logI
D
V
GS
increasing
V
DS
I
OFF
ImprovingI
EFF
7
CMOSTechnologyScaling
Gatelengthhasnotscaledproportionatelywithdevice
pitch(0.7xpergeneration)inrecentgenerations.
Transistorperformancehasbeenboostedbyothermeans.
90nmnode 65nmnode 45nmnode 32nmnode
T.Ghani etal.,
IEDM 2003
K.Mistry etal.,
IEDM 2007
P.Packan etal.,
IEDM 2009
XTEMimageswiththesamescale
courtesyV.Moroz (Synopsys,Inc.)
(afterS.Tyagi etal.,IEDM 2005)
8
P.Packan etal.(Intel),IEDMTechnicalDigest,pp.659662,2009
Strainedchannelregions
eff
|
Highkgatedielectricandmetalgateelectrodes C
ox
|
CrosssectionalTEMviewsofIntels32nmCMOSdevices
MOSFETPerformanceBoosters
9
A.Asenov,Symp.VLSITech.Dig.,p.86,2007
ProcessInducedVariations
Subwavelengthlithography:
Resolutionenhancement
techniquesarecostlyandincrease
processsensitivity
SiO
2
Gate
Source Drain
A.Brownetal.,
IEEETrans.
Nanotechnology,
p.195,2002
Randomdopant fluctuations(RDF):
Atomisticeffectsbecome
significantinnanoscale FETs
courtesyMikeRieger (Synopsys,Inc.)
10
Gatelineedgeroughness:
photoresist
BulkMOSFETDesignOptimization
TomaximizeI
EFF
andminimizeV
TH
variation,heavydoping
nearthesurfaceofthechannelregionshouldbeavoided.
UseasteepretrogradechanneldopingprofiletosuppressI
OFF
( )
Si ox ox Si
ox Si
ox
Si
t t
t t
c c c
c

/ 1 2 +
=
ox Si
ox
Si
t t
c
c

2
=
Double-Gate FET
Scale length:
Ground-Plane FET Structure: Double-Gate FET
Scale length:
Ground-Plane FET Structure:
Source
Drain
EnergyBandProfile:
(OFFState)
longer
R.H.Yanetal.,IEEETrans.ElectronDevices,Vol.39,pp.17041710,1992
t
Si
isacritical
designparameter!
11
ThinBodyMOSFETs
UltraThinBody(UTB)
BuriedOxide
SiSubstrate
Source Drain
Gate
t
Si
L
g
DoubleGate(DG)
Gate
Source Drain
Gate
t
Si
L
g
R.H.Yanetal.,IEEETED1992 B.Yuetal.,ISDRS1997 12
WhyThinBodyStructures?
Physicallylimitthedepthofthechannelregiontoeliminatesub
surfaceleakagepathsandachievegoodelectrostaticintegrity
Drain Source
Gate
L
g
UltraThinBody
MOSFET:
BuriedOxide
Source Drain
Gate
Substrate
Siliconon
Insulator(SOI)
Wafer
13
Bodydopingcanbeeliminatedift
Si
issufficientlythin
higherI
ON
duetohighercarriermobility
reducedimpactofrandomdopantfluctuations(RDF)
Effectoft
Si
onOFFstateLeakage
I
OFF
=19A/m I
OFF
=2.1nA/m
LeakageCurrent
Density[A/cm
2
]
@V
DS
=0.7V
10
6
10
1
3x10
2
0.0
4.0
8.0
12.0
16.0
20.0
G
G
S D
G
G
S D
SiThickness[nm]
L
g
=25nm;t
ox,eq
=12
t
Si
=10nm t
Si
=20nm
14
RelaxingtheBodyThinnessRequirement
O.Faynot,IEEEIntlSOIConference,2011
Thinnerburiedoxide(BOX)reducedDIBL
ReversebackbiasingfurtherreductionofSCE
15
ImpactofBOXThickness t
Si
ReductionwithL
g
Scaling
ThresholdVoltage(V
TH
)Adjustment
T.Ohtouetal.,IEEEEDL28,p.740,2007
T
BOX
= 10nm
V
TH
canbeadjustedviasubstratedoping,forreducedo
VTH
:
S.Mukhopadhyayetal.,IEEEEDL27,p.284,2006
V
TH
canbeadjustedviasubstratedoping,forreducedo
VTH
:
V
TH
canbedynamicallyadjustedviabackbiasing.
Reversebackbiasing(toincreaseV
TH
)isbeneficialforloweringSCE.
16
DoubleGateMOSFETStructures
L.Geppert,IEEESpectrum,October2002 17
PLANAR:
VERTICAL FIN:
DoubleGateFinFET
PlanarDGFET
Gate
Source Drain
Gate
t
Si
FinWidth=t
Si
L
g
GATE
SOURCE
DRAIN
20nm
10nm
Y.K.Choietal.,
IEDMTechnicalDigest,2001
15nmL
g
FinFET:
FinHeight
H
FIN
=W/2
D.Hisamoto etal.,IEDM
TechnicalDigest,1998
N.Lindert etal.,IEEE
ElectronDevice Letters,p.
487,2001
FinFET
Source
Drain
Gate
L
g
18
Usespacerstodefinefins
FinPatterningbySpacerLithography
Fin
hardmask
spacer
PlanView
Notethatgatelineedge
roughnessisnotan
issueforFinFETs
Y.K.Choi etal.,
IEEETrans.Electron
Devices,Vol.49,
pp.436441,2002
o
CD
=1.3nm
o
CD
=3.6nm
BetterCDcontrolis
achievedwithspacer
lithography
BOX
SOI
3DView
spacer resist
sacrificial
Gate
Drain Source
Usespacerstodefinefins,andphotoresist todefine
source/draincontactpadregions:
19
ImpactofFinLayoutOrientation
(Seriesresistanceismore
significantatshorterL
g
.)
Ifthefinisoriented||or to
thewaferflat,thechannel
surfacesliealong(110)planes.
Lowerelectronmobility
Higherholemobility
Ifthefinisoriented45 tothe
waferflat,thechannelsurfaces
liealong(100)planes.
L. Chang et al., SISPAD, 2004
20
ThegateelectrodesofadoublegateFETcanbeisolated
byamaskedetch,toallowforseparatebiasing.
Onegateisusedforswitching.
TheothergateisusedforV
TH
control.
IndependentGateOperation
Source
Drain
Back
Gated
FET
Gate1
Gate2
L.Mathewetal.(FreescaleSemiconductor),
2004 IEEEInternationalSOIConference
D.M.Friedetal.(CornellU.),
IEEEElectronDeviceLetters,
Vol.25,pp.199201,2004
21
FinFET Layout
LayoutissimilartothatofconventionalMOSFET,except
thatthechannelwidthisquantized:
BulkSiMOSFET
Source
Drain
Source
Gate
Gate
Source
Drain
Source
FinFET
P
fin
Intel
Corp.
TheS/Dfinscanbemergedbyselectiveepitaxy:
M.Guillorn etal.,Symp.VLSITechnology2008
22
FinPitch
Limitedbylithographiccapability
Constrainssource/drainimplanttiltangle
Tradeoff:performancevs.layoutefficiency
FinWidth
Determinesshortchanneleffects
FinFET DesignTradeOffs
P
fin
FinHeight
Limitedbyetchtechnology
Tradeoff:layoutefficiency
vs. designflexibility
ParasiticgateresistanceandcapacitancedependonP
fin
Source
Drain
Gate
FinWidth=t
Si
L
g
FinHeight
H
FIN
=W/2
23
ImpactofRandomVariations@25nmL
g
RDFinducedvariationsweresimulatedusingKMCmodel
GateLERinducedvariationsweresimulatedbysamplingprofiles
fromanSEMimageofaphotoresistline
u
M
variationswereestimatedbasedonDadgour etal.,2008IEDM
24
C. Shin et al., IEEE Intl SOI Conference, 2009
t
Si
=2L
g
/3 t
Si
=6nm
t
BOX
=10nm
MultigateMOSFETs
I.Ferain,C.A.Colinge,J.P.Colinge,Nature 479,310316(2011)
SOIMultiGateMOSFETDesigns
afterYangandFossum,IEEETrans.ElectronDevices,Vol.52,pp.11591164,2005
H
S
i
/

L
e
f
f
W
Si
/L
eff
bodydimensions
requiredfor
DIBL=100mV/V
UTBFET
UltrathinSOI
H
Si
~L
g
/5
FinFET
Narrowfin
W
Si
~L
g
/2
TriGateFET
Relaxedfindimensions
W
Si
>L
g
/2;H
Si
>L
g
/5
T
ox
=1.1nm
26
DoubleGatevs.TriGateFET
TheDoubleGateFETdoesnotrequireahighlyselective
gateetch,duetotheprotectivedielectrichardmask.
Additionalgatefringingcapacitanceislessofanissuefor
theTriGateFET,sincethetopfinsurfacecontributesto
currentconductionintheONstate.
DoubleGateFET TriGateFET
channel
afterM.Khare,2010IEDMShortCourse 27
22nmTriGateFETs
C.Auth etal.,Symp.VLSITechnology2012
L
g
=3034nm;W
fin
=8nm;H
fin
=34nm
Highk/metalgatestack,EOT=0.9nm
Channelstraintechniques
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TransferCharacteristics
NMOS PMOS
SOIMOSFETEvolution
Thegateallaround(GAA)structureprovidesforthegreatest
capacitivecouplingbetweenthegateandthechannel.
http://www.electroiq.com/content/eiq-2/en/articles/sst/print/volume-51/issue-5/features/nanotechnology/fully-gate-all-around-silicon-nanowire-cmos-devices.html
29
Summary
Powerdensityandvariabilitynowlimitconventional
bulkMOSFETscaling.
MultigateMOSFETstructurescanachievesuperior
electrostaticintegritythantheconventionalplanarbulk
MOSFETstructureandhenceofferapathwaytolower
V
DD
,reduceV
TH
variability,andextendtransistor
scaling.
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