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White Paper: FPGAs

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WP237 (v1.0) February 27, 2006

What are OFFSET Constraints?
By: Chris Zeh

A fundamental timing constraint is the OFFSET constraint. This paper discusses the overall purpose of OFFSET constraints, the specific paths that are covered by OFFSET constraints, and the differences between the OFFSET IN and OFFSET OUT constraints. Additionally, examples of timing reports are included with the common application of the OFFSET IN and OFFSET OUT constraints.

Why Use OFFSET Constraints?
The OFFSET constraint is a fundamental timing constraint. OFFSET constraints are used to define the timing relationship between an external clock pad and its associated data-in or data-out pad. This relationship is also known as constraining the Pad-toSetup or Clock-to-Out paths on the device. These constraints are important for specifying timing interfaces with external components.
Pad to Setup or OFFSET IN BEFORE constraint is used to ensure that the external clock and external input data meet the setup time on the internal flip-flop. Clock-to-Out or OFFSET OUT AFTER constraint is used to control the setup/hold requirement of the downstream devices, as well as the external output data pad and the external clock pad.

The OFFSET IN BEFORE and OFFSET OUT AFTER constraints allows you to specify the internal data delay from the input pads or to the output pads with respect to the clock. Alternatively, the OFFSET IN AFTER and OFFSET OUT BEFORE constraints allows you to specify external data and clock relationship for the timing on the path to
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WP237 (v1.0) February 27, 2006

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Why Use OFFSET Constraints?

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the input pads and to the output pads for the Xilinx device. The timing software determines the internal requirements without requiring a FROM PADS TO FFS or FROM FFS TO PADS constraint. See Figure 1 and Figure 2.

Figure 1: Timing Reference Diagram of OFFSET IN Constraint

Figure 2: Timing Reference Diagram of OFFSET OUT Constraint

You can use these FROM:TO constraint options in the following situations: • • Calculate whether a setup time is violated at a flip-flop whose data and clock inputs are derived from external nets Specify the delay of an external output net derived from the Q output of an internal flip-flop that is clocked from an external device pin Includes clock path delay in the analysis for each individual synchronous element Includes paths for all synchronous element types (FFS, RAMS, LATCHES, and etc.) Utilizes a global syntax that allows all inputs or outputs to be constrained with respect to an external clock Analyzes setup and hold time violation on inputs

The OFFSET constraint provides the following advantages: • • • •

WP237 (v1.0) February 27, 2006

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What Paths are Covered by OFFSET Constraints? R The OFFSET constraint automatically accounts for the following clocking path delays: • • Provides accurate timing information and uses the jitter defined on the associated PERIOD constraint Increases the amount of time for input signals to arrive at synchronous elements (clock and data paths are in parallel) ♦ Subtracts the clock path delay from the data path delay for inputs • Reduces the amount of time for output signals to arrive at output pins (clock and data paths are in series) ♦ Adds the clock path delay to the data path delay for outputs • • Includes clock phase introduced by a DLL/DCM for each individual synchronous element defined by the associated PERIOD constraint Includes clock phase introduced by a rising or falling clock edge The initial clock edge for analysis of OFFSET constraints is defined by the HIGH/LOW keyword of the PERIOD constraint: • • HIGH keyword => the initial clock edge is rising LOW keyword => the initial clock edge is falling What Paths are Covered by OFFSET Constraints? The OFFSET constraints cover the following and are shown in Figure 3: • • From input pads to synchronous elements (OFFSET IN) From synchronous elements to output pads (OFFSET OUT) If the clock that clocks a synchronous element does not come through an input pad – for example.xilinx. If the OFFSET constraint is used to analyze multiple clock phases or clock edges. Figure 3: Circuit Diagram of OFFSET Constraints The OFFSET constraint is analyzed with respect to only a single clock edge. as in WP237 (v1. 2006 www. it is derived from another clock – then the OFFSET constraint will fail to return any paths during timing analysis.com 3 .0) February 27.

The rising and falling groups require different group OFFSET constraints. when the internal clock is a “divide by two” version of the external clock. The OFFSET constraint does not optimize paths clocked by an internally generated clock. and the original requirement of the OFFSET OUT with the internal clock was 10 ns. not a group OFFSET constraint.com 4 . and then to create group or net-specific OFFSET constraint for I/O with special timing requirements. The register group can be used to identify path source or destination that has different requirements from or to a single pad on a clock edge. This priority rule allows you to start with global OFFSETs. even though these registers have the same data and clock source. Net-specific OFFSET overrides both global and group OFFSET. which is useful if a clock is used on the rising and falling edge for inputs and outputs. You can group and constrain the pads and registers all at once. WP237 (v1. You can specify OFFSET constraints in three levels of coverage. Group OFFSET allows you to group pads or registers to use the same requirement. then the requirement of the OFFSET OUT with the external clock is 20 ns. For example. you can use the following options: • • Create a FROM:TO or multi-cycle constraint on these paths Determine if the internal clock is related to an external clock signal: Change the requirement based upon the relationship between the two clocks.What Paths are Covered by OFFSET Constraints? R source synchronous designs or Dual-Data Rate application. TIMEGRP C = FALLING FFS. To obtain an I/O timing analysis on internal clocks or derived clocks. A group OFFSET overrides a global OFFSET specified for the same I/O. and C are different time groups (TIMEGRP AB = RISING FFS.0) February 27. You can use the pad group to identify path sources or destinations that have different requirements from or to a group of pads on the same clock edge. registers A. taking into account the clock delay. 2006 www. You can use FROM:TO or multi-cycle constraints for these paths. B. In Figure 4. Using wildcards in net-specific OFFSET constraint creates multiple net-specific OFFSET constraints. as follows: • • • A Global OFFSET applies to all inputs or outputs for a specific clock A Group OFFSET identifies a group of input or outputs clocked by a common clock that have the same timing requirement A Net-Specific OFFSET specifies the timing by each input or output OFFSET constraints with a more specific scope override a more general scope.). then the OFFSET constraint must be manually adjusted by the clock phase. Use global and group OFFSET constraints to reduce memory usage and runtime. A group OFFSET constraint can include both a register group and a pad group.xilinx. This allows you to perform two different timing analyses for these registers.

Clock arrival takes into account any clock phase generated by the DLL/DCM or clock edge. the OFFSET IN value should be adjusted by an additional 5 ns: Original Constraint: NET "PAD_IN" OFFSET = IN 10 BEFORE "PADCLKIN". When creating pad-to-setup requirements. It takes into account the clock delay. the OFFSET constraint will not be used during timing driven optimization of the design. the clock inputs referenced by the OFFSET constraints must be explicitly assigned to a global clock pin (using either a BUFG symbol or applying the BUFG=CLK constraint to an ordinary input). 2006 www. You can visualize this as the time that the data arrives at the edge of the device before the next clock edge arrives at the device. Note: The clock net name required for OFFSET constraints is the clock net name attached to the IPAD. The OFFSET IN is an external clock-to-data relationship specification. then the OFFSET value should be adjusted by a quarter of the PERIOD constraint value. If the timing report does not display a clock arrival time. refer to the schematic in Figure 3. This “OFFSET = IN 2 ns BEFORE clock_pad” constraint reads that the data WP237 (v1. For example. Modified Constraint: NET "PAD_IN" OFFSET = IN 15 BEFORE "PADCLKIN". and DLL/DCM introduced clock phase when analyzing the setup requirement (data_delay + setup – clock_delay – clock_arrival).What is the OFFSET IN Constraint? R Figure 4: OFFSET with Different TIMEGRPs For CPLD designs. then the timing analysis tools did not analyze a PERIOD constraint for that specific synchronous element. make sure to incorporate any phase or PERIOD adjustment factor into the value specified for an OFFSET IN constraint. If the net from the CLK90 pin of the DLL/DCM clocks your register. not "CLK90". clock edge. What is the OFFSET IN Constraint? The OFFSET IN constraint is used to define the Pad-To-Setup timing requirement.0) February 27. if the PERIOD constraint value is 20 ns and is from the CLK90 of the DCM. For the following example.xilinx.com 5 . it is "PADCLKIN". In this case. Otherwise. OFFSET IN BEFORE The OFFSET IN BEFORE constraint defines the time available for data to propagate from the pad and setup at the synchronous element.

0) February 27. 2006 www. The following equation defines the hold relationship: TClock – Tdata + Thold <= Toffset_IN_BEFORE_V ALID The following are examples of the OFFSET IN with the VALID keyword: • • TIMEGRP DATA_IN OFFSET IN = 1 VALID 3 BEFORE CLK TIMEGRP FF_RISING. See Figure 1 and Figure 5.TClock <= Toffset_IN_BEFORE The OFFSET IN requirement value is used as a setup time requirement of the FPGA during the setup time analysis. TIMEGRP DATA_IN OFFSET IN = 4 VALID 3 BEFORE CLK TIMEGRP FF_FALLING. See Figure 6. Figure 6: OFFSET IN Constraint with VALID Keyword WP237 (v1. Figure 5: Circuit Diagram with Calculation Variables for OFFSET IN BEFORE Constraints The following equation defines the setup relationship: TData + TSetup . the VALID value is equal to the OFFSET time requirement. some time period (2 ns) BEFORE the reference clock edge arrives at the clock pad.What is the OFFSET IN Constraint? R will be valid at the input data pad. and the timing analysis tools perform a hold-time analysis. which specifies a zero hold-time requirement. By default. The VALID keyword is used in conjunction with the requirement to create a hold-time requirement during a hold-time analysis. The VALID keyword specifies the duration of the incoming data valid window.xilinx. The tools automatically calculate and control internal data and clock delays to meet the flip-flop setup time.com 6 .

The equation used in timing analysis is as follows: Slack = (Requirement . Simple Example A simple example of the OFFSET IN constraint has an initial clock edge at 0 ns based upon the PERIOD constraint. If the data delay is longer than the clock delay. which is specified with the HIGH keyword of the PERIOD constraint.(Data Path .xilinx.What is the OFFSET IN Constraint? R The OFFSET Constraint is analyzed with respect to the rising clock edge. with a 50% duty cycle. The following is an example of the OFFSET IN with the HIGH/LOW keyword: TIMEGRP DATA_IN OFFSET IN = 1 VALID 3 BEFORE CLK LOW. The prorated clock path delays are not used for device families that are older than Virtex™-II. The resulting timing report displays the data path. if the PERIOD constraint has the HIGH keyword and the OFFSET has the LOW keyword. The prorated data delays are not used for device families older than Virtex-II. the end result is a smaller hold time.0) February 27. 2006 www. The longer the clock path delay. the clock path.Clock Path . The prorated data delays are similar to the prorated values in the setup analysis. The timing report displays the initial clock edge as the clock arrival time. An example report is shown below. In Figure 7. then the timing analysis tools did not recognize a PERIOD constraint for that particular synchronous element. The equation for external hold included in the OFFSET IN analysis of the FPGA is: Clock Path Delay plus Flip-Flop Hold time minus the prorated version of the Data Delay. the smaller the external setup time. The general prorating factors are 85% for Global Routing and 80% for Local Routing. The prorated clock path delay is used to obtain an accurate setup time analysis. The OFFSET HIGH/LOW keyword can be used to override the HIGH/LOW keyword defined by the PERIOD constraint. For example.Clock Arrival)) Figure 7: Timing Diagram of Simple OFFSET IN Constraint WP237 (v1.com 7 . and the clock arrival time (shown in bold). The equation for external setup included in the OFFSET IN analysis of the FPGA is Data Delay plus the Flip-Flop Setup time minus the prorated version of the Clock Path Delay. when the signal is capturing data on the rising and falling clock edges or producing data on rising and falling clock edges. If the timing report does not display a clock arrival time. the OFFSET requirement is 3 ns before the initial clock edge. This is extremely useful for DDR design. the falling edged synchronous elements will have the clock arrival time set to zero.

O net (fanout=1) Tbgcko_O 1.784ns (Levels of Logic = 1) -0.901 reset_IBUF OutAz_0_OBUF my_oddrA_ODDR_inst/FF0 ----------------------------------------------Total --------------------- 2.CLKFX net (fanout=1) Tdmcko_CLKFX 0.368 0.285ns logic.CLKIN DCM_ADV_X0Y4. 2006 www.SR OLOGIC_X1Y188.168ns (-4.com 8 .CLK net (fanout=40) Tosrck 1. 4.191ns (requirement -(data path .168ns (Levels of Logic = 3) 0.136ns route) (59.clock arrival + uncertainty)) reset (PAD) my_oddrA_ODDR_inst/FF0 (FF) clock0_ddr_bufg rising at 0. The timing report displays the clock arrival time for each edge of the clock.0) February 27.2% logic.clock path .568 MY_ddr_dcm/CLKIN_IBUFG_OUT MY_ddr_dcm/DCM_ADV_INST MY_ddr_dcm/DCM_ADV_INST BUFGCTRL_X0Y19.846 clock0_ddr_bufg --------------------- ----------------------------------------------Total -0.What is the OFFSET IN Constraint? R Timing Report Example Slack: Source: Destination: Destination Clock: Requirement: Data Path Delay: Clock Path Delay: Clock Uncertainty: -0.639 ------------------- clock0 clock0 MY_ddr_dcm/CLKIN_IBUFG_INST DCM_ADV_X0Y4. WP237 (v1.I Tiopi 0.8% route) Clock Path: clock0 to my_oddrA_ODDR_inst/FF0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------E19.I Tiopi 0. 40.000ns 3.000ns 2.903 -5. The first clock edge is at 0 ns based upon the PERIOD constraint.239ns Data Path: reset to my_oddrA_ODDR_inst/FF0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------K14. and the second clock edge is at half the PERIOD constraint.747 ------------------reset reset reset_IBUF OLOGIC_X1Y188.136 0.I0 BUFGCTRL_X0Y19.117ns route) Two-Phase Example A two-phase or both clock edges example of the OFFSET IN constraint has an initial clock edge that correlates to the two edges of the clock. 1.644 MY_ddr_dcm/CLKFX_BUF MY_ddr_dcm/CLKFX_BUFG_INST MY_ddr_dcm/CLKFX_BUFG_INST OLOGIC_X1Y188.CLK net (fanout=24) 1.xilinx.784ns (1.648ns logic.

177 DataD_9_IBUF TmpAa<1> SumAa<1>1 TmpAa_1 ----------------------------------------------Total --------------------------- 2. as in Dual-Data Rate.clock arrival + uncertainty)) DataD<9> (PAD) TmpAa_1 (FF) clock0_ddr_bufg falling at 0. the clock arrival time for the falling edge synchronous elements will be a zero and the rising edge synchronous elements will be at half the PERIOD constraint. If both edges are used.0) February 27.492ns (0.239ns Data Path: DataD<9> to TmpAa_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------R9. OFFSET = IN 3 ns BEFORE clock LOW Figure 8: Timing Diagram with Two-Phase OFFSET IN Constraints Timing Report Example Slack: Source: Destination: Destination Clock: Requirement: Data Path Delay: Clock Path Delay: Clock Uncertainty: 0.038ns (Levels of Logic = 3) 0. 2006 www. An example timing report is shown below. In Figure 8. the LOW keyword on the OFFSET IN.com 9 . If the PERIOD constraint had the HIGH keyword.000ns 2.606ns route) WP237 (v1. the following constraints would produce the same example report: • • ΤIMESPEC TS_clock = PERIOD clock 10 ns HIGH 50%. 1.(data path .CLK net (fanout=1) Tas 1.What is the OFFSET IN Constraint? R The resulting timing report displays the data path.231ns (requirement . the PERIOD constraint has the clock arrival on the falling edge.I Tiopi 0. In this example. then two OFFSET constraints are created. based upon the LOW keyword.000ns 3. So.clock path .606 0. and the clock arrival time (shown in bold). one for each clock edge.709 ------------------DataD<9> DataD<9> DataD_9_IBUF SLICE_X67Y142.F4 SLICE_X67Y142.xilinx. the OFFSET requirement is 3 ns before the initial clock edge. the clock path.886ns logic.492ns (Levels of Logic = 2) -0.

the timing report displays the clock arrival time as the phaseshifted amount. CLK90. Since the clock is phaseshifted by the DCM.639 ------------------clock0 clock0 MY_ddr_dcm/CLKIN_IBUFG_INST DCM_ADV_X0Y4.038ns (-4.644 MY_ddr_dcm/CLKFX_BUF MY_ddr_dcm/CLKFX_BUFG_INST MY_ddr_dcm/CLKFX_BUFG_INST SLICE_X67Y142. the OFFSET requirement is 3 ns before the initial clock edge.com 10 . If the CLK90 output is used.247ns route) Phase-Shifted Example A DCM phase-shifted clock. Figure 9: Timing Diagram for Phase-shifted Clock In OFFSET IN Constraint WP237 (v1. example of the OFFSET IN constraint has an initial clock edge at 0 ns based upon the PERIOD constraint.O net (fanout=1) Tbgcko_O 1. The resulting timing report displays the data path.285ns logic.5 ns.976 clock0_ddr_bufg --------------------------- ---------------------------------------------Total -0. and the clock arrival time (shown in bold).6% logic. In this example.I Tiopi 0. 2006 www. then the phase-shifted amount will be a quarter of the PERIOD.4% route) R Clock Path: clock0 to TmpAa_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------E19. In Figure 9.568 MY_ddr_dcm/CLKIN_IBUFG_OUT MY_ddr_dcm/DCM_ADV_INST MY_ddr_dcm/DCM_ADV_INST BUFGCTRL_X0Y19.CLKFX net (fanout=1) Tdmcko_CLKFX 0. An example timing report is shown below.CLK net (fanout=24) 1.CLKIN DCM_ADV_X0Y4.0) February 27.368 0.What is the OFFSET IN Constraint? (35. the PERIOD constraint has the initial clock arrival on the rising edge. 4. but the clock arrival value is at 2.xilinx.903 -5.I0 BUFGCTRL_X0Y19. the clock path. 64.

clock path .SR OLOGIC_X1Y188.I Tiopi 0.000ns 2.136 0. then the WP237 (v1. the timing report displays the clock arrival time as the phase-shifted amount.784ns (Levels of Logic = 1) -0.285ns logic.846 clock0_ddr_bufg --------------------------- ----------------------------------------------Total -0.784ns (1.568 MY_ddr_dcm/CLKIN_IBUFG_OUT MY_ddr_dcm/DCM_ADV_INST MY_ddr_dcm/DCM_ADV_INST BUFGCTRL_X0Y19.903 -5. 2006 www.308ns (requirement -(data path .368 0.0) February 27.168ns (Levels of Logic = 3) 0. 1.com 11 .CLK net (fanout=40) Tosrck 1.2% logic.168ns (-4.747 ------------------reset reset reset_IBUF OLOGIC_X1Y188.I Tiopi 0.clock arrival + uncertainty)) reset (PAD) my_oddrA_ODDR_inst/FF0 (FF) clock90_bufg rising at 2. Since the clock is phase-shifted by the DCM.xilinx.CLKIN DCM_ADV_X0Y4.644 MY_ddr_dcm/CLKFX_BUF MY_ddr_dcm/CLKFX_BUFG_INST MY_ddr_dcm/CLKFX_BUFG_INST OLOGIC_X1Y188.500ns 3.901 reset_IBUF OutAz_0_OBUF my_oddrA_ODDR_inst/FF0 ------------------------------------------------Total --------------------------- 2.639 ------------------clock0 clock0 MY_ddr_dcm/CLKIN_IBUFG_INST DCM_ADV_X0Y4.CLKFX net (fanout=1) Tdmcko_CLKFX 0.What is the OFFSET IN Constraint? R Timing Report Example Slack: Source: Destination: Destination Clock: Requirement: Data Path Delay: Clock Path Delay: Clock Uncertainty: -2.136ns route) (59.239ns Data Path: reset to my_oddrA_ODDR_inst/FF0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------K14.O net (fanout=1) Tbgcko_O 1.I0 BUFGCTRL_X0Y19.8% route) Clock Path: clock0 to my_oddrA_ODDR_inst/FF0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------E19. 4. 40. If the CLK0 output is phase-shifted by a user-specified amount.117ns route) Fixed Phase-Shifted Example A DCM fixed phase-shifted clock example of the OFFSET IN constraint has an initial clock edge at 0 ns based upon the PERIOD constraint.CLK net (fanout=24) 1.648ns logic.

Figure 10: Timing Diagram of Fixed Phase-shifted Clock in OFFSET IN Constraint Timing Report Example Slack: Source: Destination: Destination Clock: Requirement: Data Path Delay: Clock Path Delay: Clock Uncertainty: -4. the clock path.606 0.492ns (0.038ns (Levels of Logic = 3) 0. and the clock arrival time (shown in bold).clock arrival + uncertainty)) DataD<9> (PAD) TmpAa_1 (FF) clock1_fixed_bufg rising at 4.6% logic. 1.239ns Data Path: DataD<9> to TmpAa_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------R9. In this example. An example timing report is shown below.000ns 2.F4 SLICE_X67Y142.606ns route) (35. but the clock arrival value is at the fixed phase-shifted amount.269ns (requirement -(data path .886ns logic.xilinx.clock path .0) February 27.492ns (Levels of Logic = 2) -0. The resulting timing report displays the data path.4% route) WP237 (v1. the OFFSET requirement is 3 ns before the initial clock edge.500ns 3.177 DataD_9_IBUF TmpAa<1> SumAa<1>1 TmpAa_1 ----------------------------------------------Total --------------------------- 2.709 ------------------DataD<9> DataD<9> DataD_9_IBUF SLICE_X67Y142.I Tiopi 0. as seen in the example timing report.CLK net (fanout=1) Tas 1. 2006 www. the PERIOD constraints has the initial clock arrival on the rising edge.com 12 . In Figure 10. 64.What is the OFFSET IN Constraint? R phase-shifted amount will be a percentage of the PERIOD.

This will compensate for the clock arrival time associated with the falling edge synchronous elements. The timing analysis tools do not automatically adjust any of the clock phases during analysis. So.com 13 . so the constraints must be manually adjusted. During the timing analysis.CLKFX net (fanout=1) Tdmcko_CLKFX 0. the second OFFSET IN constraint will have a different requirement. This option can only be used if the duty cycle on the clock is 50/50. and the clock arrival time (shown in bold). The only addition is the LOW keyword (if the PERIOD constraint has the HIGH keyword).CLKIN DCM_ADV_X0Y4. if you have the original requirement as 3 ns with a PERIOD of 10 ns. the clock path. If the PERIOD constraint has the LOW keyword. The falling edge OFFSET IN constraint requirement should be the “original requirement” minus half of the PERIOD constraint. then the OFFSET constraint would use the LOW keyword. the clock arrival time for the falling edge needs to be managed.0) February 27.O net (fanout=1) Tbgcko_O 1.368 0. Then create an OFFSET IN constraint for each time group.I Tiopi 0. In this example the PERIOD constraint has the clock arrival on both the rising edge and falling edge. so you need to subtract that difference from the original requirement. the OFFSET requirement is 3 ns before the initial clock edge.I0 BUFGCTRL_X0Y19.903 -5.CLK net (fanout=24) 1. The timing analysis tools offer two options to manage the falling edge clock arrival time. the falling edge OFFSET IN constraint requirement is -2 ns.What is the OFFSET IN Constraint? Clock Path: clock0 to TmpAa_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------E19. the difference between the rising and falling edges of the clock is added to the falling-edge-data-path analysis.976 clock0_ddr_bufg --------------------------- R ----------------------------------------------Total -0.285ns logic. which correlates to the two clock edges. The first option is to create two time groups.639 ------------------clock0 clock0 MY_ddr_dcm/CLKIN_IBUFG_INST DCM_ADV_X0Y4.644 MY_ddr_dcm/CLKFX_BUF MY_ddr_dcm/CLKFX_BUFG_INST MY_ddr_dcm/CLKFX_BUFG_INST SLICE_X67Y142. In Figure 11.xilinx.247ns route) Dual-Data Rate Example A Dual-Data Rate example of the OFFSET IN constraint has an initial clock edge at 0 ns and half the PERIOD constraint. 4. 2006 www.038ns (-4. The resulting timing report displays the data path. The negative value is legal in the constraints language. WP237 (v1. The timing report displays the clock arrival time for each edge of the clock.568 MY_ddr_dcm/CLKIN_IBUFG_OUT MY_ddr_dcm/DCM_ADV_INST MY_ddr_dcm/DCM_ADV_INST BUFGCTRL_X0Y19. one for rising edge synchronous elements and the second for the falling edge synchronous elements. Since the data is being clocked in on both edges of the clock. An example timing report is shown below. so the clock arrival value is 0 ns and 5 ns. The second option is to create one time group and one corresponding OFFSET IN constraint with the original constraint requirement.

clock arrival + uncertainty)) DataA<3> (PAD) TmpAa_3 (FF) clock0_ddr_bufg rising at 0.762 ------------------DataA<3> DataA<3> DataA_3_IBUF SLICE_X69Y140. 2006 www.What is the OFFSET IN Constraint? R Figure 11: Timing Diagram for Dual Data Rate in OFFSET IN Constraint Timing Report Example for OFFSET = IN 3 ns BEFORE Clock Slack: Source: Destination: Destination Clock: Requirement: Data Path Delay: Clock Path Delay: Clock Uncertainty: 0.177 DataA_3_IBUF TmpAa<3> SumAa<3>1 TmpAa_3 ----------------------------------------------Total --------------------------- 2.xilinx.com 14 .6% route) Clock Path: clock0 to TmpAa_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) WP237 (v1.715ns route) (35.CLK net (fanout=2) Tas 1.4% logic.(data path .101ns (requirement .239ns Data Path: DataA<3> to TmpAa_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------AF20.006ns (Levels of Logic = 3) 0.000ns 2.0) February 27.939ns logic.000ns 3.F4 SLICE_X69Y140.654ns (0.715 0.clock path .654ns (Levels of Logic = 2) -0. 1.I Tiopi 0. 64.

I Tiopi 0.008 clock0_ddr_bufg --------------------------- R ------------------------------------------------Total -0.006ns (-4.6% route) Clock Path: clock0 to TmpAa_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------E19. 64. 1.clock arrival + uncertainty)) DataA<3> (PAD) TmpAa_3 (FF) clock0_ddr_bufg falling at 5.006ns (Levels of Logic = 3) 0.CLK net (fanout=24) 2.000ns -2.177 DataA_3_IBUF TmpAa<3> SumAa<3>1 TmpAa_3 ----------------------------------------------Total --------------------------- 2.644 MY_ddr_dcm/CLKFX_BUF MY_ddr_dcm/CLKFX_BUFG_INST MY_ddr_dcm/CLKFX_BUFG_INST SLICE_X69Y140.I0 BUFGCTRL_X0Y19.000ns 2.CLK net (fanout=2) Tas 1.com 15 .368 0.CLKIN DCM_ADV_X0Y4.xilinx.715ns route) (35. 4.279ns route) Timing Report Example for OFFSET = IN -2 ns BEFORE Clock Slack: Source: Destination: Destination Clock: Requirement: Data Path Delay: Clock Path Delay: Clock Uncertainty: -2.0) February 27.762 ------------------DataA<3> DataA<3> DataA_3_IBUF SLICE_X69Y140.939ns logic.CLKFX net (fanout=1) Tdmcko_CLKFX 0.I Tiopi 0.285ns logic.What is the OFFSET IN Constraint? ------------------------------------------------E19.639 ------------------clock0 clock0 MY_ddr_dcm/CLKIN_IBUFG_INST WP237 (v1. 2006 www.639 ------------------clock0 clock0 MY_ddr_dcm/CLKIN_IBUFG_INST DCM_ADV_X0Y4.715 0.239ns Data Path: DataA<3> to TmpAa_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------AF20.903 -5.F4 SLICE_X69Y140.I Tiopi 0.654ns (0.4% logic.654ns (Levels of Logic = 2) -0.O net (fanout=1) Tbgcko_O 1.clock path .568 MY_ddr_dcm/CLKIN_IBUFG_OUT MY_ddr_dcm/DCM_ADV_INST MY_ddr_dcm/DCM_ADV_INST BUFGCTRL_X0Y19.755ns (requirement -(data path .

This “OFFSET = OUT 2 ns AFTER clock_pad” constraint reads that the WP237 (v1. 4. AFTER the reference clock edge is recognized by the upstream device.O net (fanout=1) Tbgcko_O 1.CLKIN DCM_ADV_X0Y4. be sure to incorporate any phase or PERIOD adjustment factor into the value specified for an OFFSET OUT constraint.TClock <= TPeriod – Toffset_IN_AFTER A PERIOD or FREQUENCY constraint is required for OFFSET IN constraints with the AFTER keyword. The OFFSET OUT constraint is an external clock-to-data specification and takes into account the clock delay. Clock arrival time takes into account any clock phase generated by the DLL/DCM or clock edge.279ns route) OFFSET IN AFTER The OFFSET IN AFTER constraint describes the time used by the data external to the FPGA. If your register is clocked by the net from the CLK90 pin of the DLL.I0 BUFGCTRL_X0Y19. which has a PERIOD of 20 ns.568 MY_ddr_dcm/CLKIN_IBUFG_OUT MY_ddr_dcm/DCM_ADV_INST MY_ddr_dcm/DCM_ADV_INST BUFGCTRL_X0Y19.368 0. Modified Constraint: NET "PAD_OUT" OFFSET = OUT 10 AFTER "PADCLKIN".CLK net (fanout=24) 2. If the timing report does not display a clock arrival time. 2006 www.285ns logic.006ns (-4. This “OFFSET = IN 2 ns AFTER clock_pad” constraint reads that the data to be registered in the FPGA is available on the FPGA’s input pad. For the following example. To adhere to the OFFSET constraint syntax.644 MY_ddr_dcm/CLKFX_BUF MY_ddr_dcm/CLKFX_BUFG_INST MY_ddr_dcm/CLKFX_BUFG_INST SLICE_X69Y140. clock edge. You can visualize this time as the data leaving the edge of the device after the current clock edge arrives at the edge of the device.903 -5. OFFSET IN subtracts this time from the PERIOD declared for the clock to determine the time available for the data to propagate from the pad to the setup at the synchronous element. assume no skew on CLK between the devices (see Figure 1).com 16 . some time period (2ns). then the timing analysis tools did not analyze a PERIOD constraint for that specific synchronous element.xilinx. The following equation defines this relationship: TData + TSetup .CLKFX net (fanout=1) Tdmcko_CLKFX 0.0) February 27.What is the OFFSET OUT Constraint? DCM_ADV_X0Y4. the OFFSET value should be adjusted by 5 ns less than the original constraint: Original Constraint: NET "PAD_OUT" OFFSET = OUT 15 AFTER "PADCLKIN".008 clock0_ddr_bufg --------------------------- R ------------------------------------------------Total -0. What is the OFFSET OUT Constraint? The OFFSET OUT constraint is used to define the clock-to-pad timing requirements. When you create clock-to-pad requirements. and DLL/DCM introduced clock phase when analyzing the clock-to-out requirements (clock_delay + clock_to_out + data_delay + clock_arrival). OFFSET OUT AFTER The OFFSET OUT AFTER constraint defines the time available for the data to propagate from the synchronous element to the pad. refer to Figure 2. You can visualize this time as the difference of data arriving at the edge of the device after the current clock edge arrives at the edge of the device.

the falling edged synchronous elements will have the clock arrival time set to zero. with a 50% duty cycle. The timing report displays the initial clock edge as the clock arrival time. the PERIOD constraint has the HIGH keyword and the OFFSET has the LOW keyword. For example. If the timing report does not display a clock arrival time. the clock path. An example timing report is shown below.com 17 . at the clock pad. then the timing analysis tools did not recognize a PERIOD constraint for that particular synchronous element. AFTER the reference clock pulse is recognized by the FPGA. and the clock arrival time (shown in bold). WP237 (v1. some time period (2 ns). Figure 12: Circuit Diagram with Calculation Variables for OFFSET OUT AFTER Constraints The following equation defines this relationship: TQ + TClock2Out + TClock <= Toffset_OUT_AFTER The analysis of this constraint involves ensuring that the maximum delay along the reference path (CLK_SYS to COMP) and the maximum delay along the data path (COMP to Q_OUT) do not exceed the specified offset. The OFFSET HIGH/LOW keyword can be used to override the HIGH/LOW keyword defined by the PERIOD constraint.What is the OFFSET OUT Constraint? R data to be registered in the downstream device is available on the FPGA’s data output pad. when the signal is capturing data on the rising and falling clock edges or producing data on a rising and falling clock edges. The following is an example of the OFFSET OUT with the HIGH/LOW keyword: TIMEGRP DATA_OUT OFFSET OUT = 10 AFTER CLK LOW. See Figure 2 and Figure 12.xilinx.0) February 27. The resulting timing report displays the data path. 2006 www. This is very useful for DDR design. Simple Example A simple example of the OFFSET OUT constraints has the initial clock edge at 0 ns based upon the PERIOD constraint.

xilinx.(Clock Arrival + Clock Path + Data Path)) Figure 13: Timing Diagram of simple OFFSET OUT Constraint Timing Report Example Slack: Source: Destination: Source Clock: Requirement: Data Path Delay: Clock Path Delay: Clock Uncertainty: -0.718 0.280ns (-4.What is the OFFSET OUT Constraint? R In Figure 13.000ns 3.000ns 3.700 MY_Std_dcm/CLK0_BUF MY_Std_dcm/CLK0_BUFG_INST MY_Std_dcm/CLK0_BUFG_INST OLOGIC_X2Y187.035 -6.CLKIN DCM_ADV_X0Y6. 5. the OFFSET requirement is 3 ns.com 18 .CLK0 net (fanout=1) Tdmcko_CLK 1.280ns (Levels of Logic = 3) 0.0) February 27.945ns logic.O net (fanout=1) Tbgcko_O 1.CLK net (fanout=9) 2.865ns (requirement -(clock arrival + clock path + data path + uncertainty)) OutD_7 (FF) OutD<7> (PAD) clock3_std_bufg rising at 0.I0 BUFGCTRL_X0Y26.420 MY_Std_dcm/CLKIN_IBUFG_OUT MY_Std_dcm/DCM_ADV_INST MY_Std_dcm/DCM_ADV_INST BUFGCTRL_X0Y26.405ns (Levels of Logic = 1) 0.180ns Clock Path: clock3 to OutD_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------D20.I Tiopi 0. The equation used in timing analysis is as follows: Slack = (Requirement .225ns route) Data Path: OutD_7 to OutD<7> Location Delay type Delay(ns) Physical Resource Logical Resource(s) WP237 (v1.775 ------------------clock3 clock3 MY_Std_dcm/CLKIN_IBUFG_INST DCM_ADV_X0Y6.472 clock3_std_bufg --------------------------- ------------------------------------------------Total 0. 2006 www.

9% logic.3. the PERIOD constraint has the clock arrival on the falling edge. 2006 www. 0.O D4.403ns logic. 0. the clock path.997 OutD_7 OutD<7> OutD_7_OBUF OutD<7> ------------------------------------------------Total --------------------------- R 3. An example timing report is shown below. In Figure 14. The timing report displays the clock arrival time for each edge of the clock.002 2.xilinx.OQ Tockq 0.com 19 .865ns (requirement -(clock arrival + clock path + data path + uncertainty)) OutD_7 (FF) OutD<7> (PAD) clock3_std_bufg falling at 0.0) February 27. Consequently. and the clock arrival time (shown in bold).000ns . the OFFSET requirement is 3 ns.PAD net (fanout=1) Tioop 0.1% route) Two-Phase Example A two-phase (use of both edges) example of the OFFSET OUT constraint has the initial clock edge that correlates to the two edges of the clock.280ns (Levels of Logic = 3) 0. In this example. The resulting timing report displays the data path.What is the OFFSET OUT Constraint? ------------------------------------------------OLOGIC_X2Y187.405ns (3. based upon the LOW keyword.000ns 3.002ns route) (99.180ns Clock Path: clock3 to OutD_7 WP237 (v1.405ns (Levels of Logic = 1) 0. the clock arrival time for the falling edge synchronous elements will be zero and the rising edge synchronous elements will be at half the PERIOD constraint. The first clock edge is at 0 ns based upon the PERIOD constraint and the second clock edge is at half the PERIOD constraint. Figure 14: Timing Diagram of Two-Phase in OFFSET OUT Constraint Timing Report Example Slack: Source: Destination: Source Clock: Requirement: Data Path Delay: Clock Path Delay: Clock Uncertainty: -0.406 ------------------OutD_7 OutD_7 D4.

xilinx.403ns logic.CLK net (fanout=9) 2. The clock arrival time corresponds to the phase shifting amount.775 ------------------clock3 clock3 MY_Std_dcm/CLKIN_IBUFG_INST DCM_ADV_X0Y6.035 -6.9% logic.0) February 27. the timing report displays the clock arrival time as the phase-shifted amount.405ns (3.472 clock3_std_bufg --------------------------- R ------------------------------------------------Total 0.420 MY_Std_dcm/CLKIN_IBUFG_OUT MY_Std_dcm/DCM_ADV_INST MY_Std_dcm/DCM_ADV_INST BUFGCTRL_X0Y26.718 0.406 ------------------OutD_7 OutD_7 D4. CLK90.com 20 .5 ns in this case. 5.OQ Tockq 0.1% route) Phase-Shifted Example A DCM phase-shifted.CLKIN DCM_ADV_X0Y6.What is the OFFSET OUT Constraint? Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------D20.CLK0 net (fanout=1) Tdmcko_CLK 1.225ns route) Data Path: OutD_7 to OutD<7> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------OLOGIC_X2Y187. 0. then the phase-shifted amount will be a quarter of the PERIOD.280ns (-4. 0.002 2. which is 2. An example timing report is shown below. the clock path.997 OutD_7 OutD<7> OutD_7_OBUF OutD<7> ------------------------------------------------Total --------------------------- 3.O D4.I0 BUFGCTRL_X0Y26. Since the clock is phase-shifted by the DCM. 2006 www. example of the OFFSET OUT constraint has the initial clock edge at 0 ns based upon the PERIOD constraint.PAD net (fanout=1) Tioop 0. The resulting timing report displays the data path. the OFFSET requirement is 5 ns. and the clock arrival time (shown in bold).002ns route) (99. In Figure 15.945ns logic. If the CLK90 output is used.700 MY_Std_dcm/CLK0_BUF MY_Std_dcm/CLK0_BUFG_INST MY_Std_dcm/CLK0_BUFG_INST OLOGIC_X2Y187. WP237 (v1.O net (fanout=1) Tbgcko_O 1.I Tiopi 0.

CLK0 net (fanout=1) Tdmcko_CLK 1.472 clock3_std_bufg --------------------------- ------------------------------------------------Total 0.500ns 5.035 -6. 5.945ns logic.180ns Clock Path: clock3 to OutD_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------D20.420 MY_Std_dcm/CLKIN_IBUFG_OUT MY_Std_dcm/DCM_ADV_INST MY_Std_dcm/DCM_ADV_INST BUFGCTRL_X0Y26.280ns (Levels of Logic = 3) 0.What is the OFFSET OUT Constraint? R Figure 15: Timing Diagram of Phase-shifted Clock in OFFSET OUT Constraint Timing Report Example Slack: Source: Destination: Source Clock: Requirement: Data Path Delay: Clock Path Delay: Clock Uncertainty: -1.0) February 27.CLKIN DCM_ADV_X0Y6.718 0.I Tiopi 0.225ns route) Data Path: OutD_7 to OutD<7> Location Delay type Delay(ns) Physical Resource WP237 (v1.000ns 3.com 21 .xilinx.700 MY_Std_dcm/CLK0_BUF MY_Std_dcm/CLK0_BUFG_INST MY_Std_dcm/CLK0_BUFG_INST OLOGIC_X2Y187.775 ------------------clock3 clock3 MY_Std_dcm/CLKIN_IBUFG_INST DCM_ADV_X0Y6.280ns (-4. 2006 www.365ns (requirement -(clock arrival + clock path + data path + uncertainty)) OutD_7 (FF) OutD<7> (PAD) clock3_std_bufg rising at 2.O net (fanout=1) Tbgcko_O 1.I0 BUFGCTRL_X0Y26.CLK net (fanout=9) 2.405ns (Levels of Logic = 1) 0.

The clock arrival time corresponds to the phase-shifting amount.002ns route) (99. based upon the PERIOD constraint.280ns (Levels of Logic = 3) WP237 (v1.000ns 3.OQ Tockq 0. 0.600ns 5. If the CLK0 output is phase-shifted by a user-specified amount. The resulting timing report displays the data path.O D4.1% route) Fixed Phase-Shifted Example A DCM fixed phase-shifted example of the OFFSET OUT constraint has the initial clock edge at 0 ns. Since the clock is phase-shifted by the DCM. the PERIOD constraint has the initial clock arrival on the rising edge. the clock path.com 22 . Figure 16: Timing Diagram of Fixed Phase-shifted Clock in OFFSET OUT Constraint Timing Report Example Slack: Source: Destination: Source Clock: Requirement: Data Path Delay: Clock Path Delay: 0.What is the OFFSET OUT Constraint? Logical Resource(s) ------------------------------------------------OLOGIC_X2Y187.9% logic.(clock arrival + clock path + data path + uncertainty)) OutD_7 (FF) OutD<7> (PAD) clock3_std_bufg rising at 0. 0. In this example.406 ------------------OutD_7 OutD_7 D4. and the clock arrival time (shown in bold).002 2. the OFFSET requirement is 5 ns. but the clock arrival value is at the fixed phase-shifted amount (as seen in the example timing report). the timing report displays the clock arrival time as the phase-shifted amount.535ns (requirement .405ns (Levels of Logic = 1) 0.0) February 27.xilinx. An example timing report is shown below.997 OutD_7 OutD<7> OutD_7_OBUF OutD<7> ------------------------------------------------Total --------------------------- R 3.PAD net (fanout=1) Tioop 0.405ns (3. In Figure 16. 2006 www. then the phase-shifted amount will be a percentage of the PERIOD.403ns logic.

the clock arrival time for the falling edge needs to be managed. and the clock arrival time (shown in bold).225ns route) Data Path: OutD_7 to OutD<7> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------OLOGIC_X2Y187.CLKIN DCM_ADV_X0Y6. The falling edge OFFSET OUT constraint requirement should WP237 (v1. 2006 www. Since the data is being clocked in on both edges of the clock.280ns (-4.472 clock3_std_bufg --------------------------- ------------------------------------------------Total 0. The resulting timing report displays the data path. which correlates to the two edges of the clock. The first option is to create two time groups.405ns (3.406 ------------------OutD_7 OutD_7 D4. The timing report will display the clock arrival time for each edge of the clock.What is the OFFSET OUT Constraint? Clock Uncertainty: 0. The timing analysis tools offer two options to manage the falling edge clock arrival time.997 OutD_7 OutD<7> OutD_7_OBUF OutD<7> ------------------------------------------------Total --------------------------- 3.180ns R Clock Path: clock3 to OutD_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------D20.403ns logic.PAD net (fanout=1) Tioop 0.O net (fanout=1) Tbgcko_O 1. An example timing report is shown below.945ns logic.O D4.CLK net (fanout=9) 2.I0 BUFGCTRL_X0Y26. Then create an OFFSET OUT constraint for each time group.035 -6.700 MY_Std_dcm/CLK0_BUF MY_Std_dcm/CLK0_BUFG_INST MY_Std_dcm/CLK0_BUFG_INST OLOGIC_X2Y187.420 MY_Std_dcm/CLKIN_IBUFG_OUT MY_Std_dcm/DCM_ADV_INST MY_Std_dcm/DCM_ADV_INST BUFGCTRL_X0Y26. 0.002ns route) (99.9% logic.0) February 27. 0. the second OFFSET OUT constraint will have a different requirement.1% route) Dual-Data Rate Example A dual-data rate example of the OFFSET OUT constraint has the initial clock edge at 0 ns and half the PERIOD constraint. The timing analysis tools do not automatically adjust any of the clock phases during analysis. 5.I Tiopi 0.xilinx. so the constraints must be manually adjusted.002 2.775 ------------------clock3 clock3 MY_Std_dcm/CLKIN_IBUFG_INST DCM_ADV_X0Y6. one for rising edge synchronous elements and the second for the falling edge synchronous elements. the clock path.com 23 .718 0.CLK0 net (fanout=1) Tdmcko_CLK 1.OQ Tockq 0.

then the OFFSET constraint has the LOW keyword. So.What is the OFFSET OUT Constraint? R be the “original requirement” plus half the PERIOD constraint. The second option is to create one time group and one corresponding OFFSET OUT constraint with the original constraint requirement.000ns 3.768 ------------------clock0 clock0 MY_ddr_dcm/CLKIN_IBUFG_INST WP237 (v1.372ns (Levels of Logic = 1) 0. the falling edge OFFSET OUT constraint requirement is 8 ns. Figure 17: Timing Diagram of Dual Data Rate in OFFSET OUT Constraint Timing Report Example of OFFSET = OUT 3 ns AFTER Clock Slack: Source: Destination: Source Clock: Requirement: Data Path Delay: Clock Path Delay: Clock Uncertainty: -0. and that difference is added to the original requirement.172ns (Levels of Logic = 3) 0. This will compensate for the clock arrival time associated with the falling edge synchronous elements.com 24 . This option can only be used if the duty cycle on the clock is 50/50. the difference between the rising and falling edges of the clock is subtracted from the falling-edge-data-path analysis. During the timing analysis. In Figure 17. If the PERIOD constraint has the LOW keyword.0) February 27.239ns Clock Path: clock0 to OutA_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------E19. the OFFSET requirement is 3 ns. if you have the original requirement as 3 ns with a PERIOD of 10. The only addition is the LOW keyword (if the PERIOD constraint has the HIGH keyword).783ns (requirement -(clock arrival + clock path + data path + uncertainty)) OutA_4 (FF) OutA<4> (PAD) clock0_ddr_bufg rising at 0.000ns 3. 2006 www.I Tiopi 0.xilinx.

172ns (-4.495 clock0_ddr_bufg --------------------------- R ---------------------------------------------Total 0.487 0.260 MY_ddr_dcm/CLKIN_IBUFG_OUT MY_ddr_dcm/DCM_ADV_INST MY_ddr_dcm/DCM_ADV_INST BUFGCTRL_X0Y19.com 25 .I0 BUFGCTRL_X0Y19.0) February 27.982 -6.9% logic.372ns (3.700 MY_ddr_dcm/CLKFX_BUF MY_ddr_dcm/CLKFX_BUFG_INST WP237 (v1.OQ Tockq 0.O net (fanout=1) Tbgcko_O 1. 2006 www.CLKFX net (fanout=1) Tdmcko_CLKFX 0.982 -6.CLK net (fanout=26) 2.406 ------------------OutA_4 OutA_4 AG6.172ns (Levels of Logic = 3) 0.O net (fanout=1) Tbgcko_O 1.What is the OFFSET OUT Constraint? DCM_ADV_X0Y4. 0.260 MY_ddr_dcm/CLKIN_IBUFG_OUT MY_ddr_dcm/DCM_ADV_INST MY_ddr_dcm/DCM_ADV_INST BUFGCTRL_X0Y19.002ns route) (99.PAD net (fanout=1) Tioop 0.372ns (Levels of Logic = 1) 0.700 MY_ddr_dcm/CLKFX_BUF MY_ddr_dcm/CLKFX_BUFG_INST MY_ddr_dcm/CLKFX_BUFG_INST OLOGIC_X2Y83.000ns 8.xilinx.239ns Clock Path: clock0 to OutA_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------E19.487 0.O AG6.CLKFX net (fanout=1) Tdmcko_CLKFX 0.000ns 3.370ns logic. 0.I0 BUFGCTRL_X0Y19.CLKIN DCM_ADV_X0Y4.964 OutA_4 OutA<4> OutA_4_OBUF OutA<4> ----------------------------------------------Total --------------------------- 3.783ns (requirement -(clock arrival + clock path + data path + uncertainty)) OutA_4 (FF) OutA<4> (PAD) clock0_ddr_bufg falling at 5. 4.792ns logic.1% route) Timing Report Example of OFFSET = OUT 8 ns AFTER Clock Slack: Source: Destination: Source Clock: Requirement: Data Path Delay: Clock Path Delay: Clock Uncertainty: -0.964ns route) Data Path: OutA_4 to OutA<4> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------OLOGIC_X2Y83.002 2.I Tiopi 0.CLKIN DCM_ADV_X0Y4.768 ------------------clock0 clock0 MY_ddr_dcm/CLKIN_IBUFG_INST DCM_ADV_X0Y4.

com 26 .1% route) OFFSET OUT BEFORE The OFFSET OUT BEFORE constraint defines the time used by the data external to the FPGA.406 ------------------OutA_4 OutA_4 AG6. The following equation defines this relationship: TQ + TClock2Out + TClock <= TPeriod – Toffset_OUT_BEFORE The analysis of the OFFSET OUT constraint involves ensuring that the maximum delay along the reference path (CLK_SYS to COMP) and the maximum delay along the data path (COMP to Q_OUT) do not exceed the clock period minus the specified offset.372ns (3.964ns route) Data Path: OutA_4 to OutA<4> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------OLOGIC_X2Y83.964 OutA_4 OutA<4> OutA_4_OBUF OutA<4> ----------------------------------------------Total --------------------------- 3.xilinx. OFFSET subtracts this time from the clock PERIOD to determine the time available for the data to propagate from the synchronous element to the pad.002ns route) (99.002 2. 0.792ns logic. This “OFFSET = OUT 2 ns BEFORE clock_pad” constraint reads that the data to be registered in the downstream device is available on the FPGA’s output pad. OFFSET Constraint Syntax This syntax is simple and easy to understand. For more information.CLK net (fanout=26) 2.OFFSET Constraint Syntax MY_ddr_dcm/CLKFX_BUFG_INST OLOGIC_X2Y83.495 clock0_ddr_bufg --------------------------- R ----------------------------------------------Total 0. refer to the Constraints Guide in the OFFSET constraints section. A PERIOD or FREQUENCY is required for OFFSET OUT constraints with the BEFORE keyword. some time period. 0. WP237 (v1. To adhere to the OFFSET constraint syntax. You can visualize this time as the data leaving the edge of the device before the next clock edge arrives at the edge of the device.0) February 27. BEFORE the clock pulse is recognized by the downstream device. 2006 www.PAD net (fanout=1) Tioop 0.370ns logic.9% logic. assume no skew on CLK between the devices (see Figure 3). 4.O AG6.172ns (-4.OQ Tockq 0.

2006 www.0 Initial Xilinx release.0) February 27.com 27 .xilinx.Revision History R Revision History The following table shows the revision history for this document. Date 02/27/2006 Version 1. Revision WP237 (v1.